Semiconductor devices and methods of making the same include a first lower device and a second lower device on a substrate. A first upper device is over the first lower device and a second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.
H10N 69/00 - Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group
G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
H01P 3/02 - Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01P 5/02 - Coupling devices of the waveguide type with invariable factor of coupling
A method includes, in response to receiving an incoming service request and establishing a call chain of pods of a service mesh network, setting a retry locker parameter to a locked state for each pod in the call chain. A locked retry locker parameter prevents the pod from initiating retries of a service request. The method includes, in response to determining that a pod in the call chain is unavailable, setting the retry locker parameter to an unlocked state for a previous pod just prior to the pod that is unavailable. The unlocked state allows a retry to the pod that is unavailable. In response to the previous pod reaching a retry limit, the method includes setting the retry locker parameter to unlocked for each pod in the call chain and sending a service termination message to a service requester.
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
H04L 67/566 - Grouping or aggregating service requests, e.g. for unified processing
H04L 69/40 - Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection
4.
QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING
An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.
A method to test an OS kernel interface, such as an eBPF helper function. The interface has a grammar that defines the kernel interface. Testing is carried out using eBPF code that invokes and tests the interface using a fuzzing engine. To facilitate the process, additional user space code is configured to generate at least one kernel event that triggers the eBPF code to run, and to transform inputs from the fuzzing engine according to the grammar that defines the kernel interface. After loading the eBPF code into the OS kernel, the user space code issues the kernel event that causes the eBPF code to run. In response, and as the fuzzing engine executes, the eBPF code records arguments sent to the OS kernel through the kernel interface. The arguments are passed through a data structure shared by the eBPF code and the user space code. By recording the arguments and other diagnostic information, the security of the kernel interface is evaluated.
Improving the runtime and discovery recovery performance for cloud-based logical volume management systems when performing mirror write operations. A mirror write consistency check (MWCC) policy that incorporates aspects of Active MWCC policies and Passive MWCC policies are utilized to more efficiently ensure that data is properly mirrored from a first copy of a logical volume to the second copy of a logical volume (as well as to potentially multiple other copies of the logical volume).
Systems and methods for operating a beamforming circuit are described. A processor can activate a transmitting element among a plurality of transmitting elements of a beamforming circuit. The processor can activate a receiving element among a plurality of receiving elements of a beamforming circuit. The processor can receive a direct current (DC) signal that represents phase and amplitude of the activated transmitting element and the activated receiving element. The processor can adjust a setting of the beamforming circuit to receive additional DC signals that represent phases and amplitudes of the activated transmitting element and the activated receiving element under the adjusted setting. The processor can determine calibration values for the beamforming circuit based on the DC signal and the additional DC signals.
H04B 7/0408 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas using two or more beams, i.e. beam diversity
8.
SEMICONDUCTOR BACKSIDE TRANSISTOR INTEGRATION WITH BACKSIDE POWER DELIVERY NETWORK
A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 23/528 - Layout of the interconnection structure
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
9.
CONTEXTUAL VIRTUAL REALITY RENDERING AND ADOPTING BIOMARKER ANALYSIS
According to one embodiment, a method, computer system, and computer program product for biometric mixed-reality emotional modification is provided. The present invention may include collecting, by a plurality of biosensors, biometric information on a user during a mixed-reality session, wherein the biometric information comprises biomarkers; identifying, by one or more machine learning models, a mental state of the user based on the biometric information; and responsive to determining that the mental state does not match an intended emotion associated with a mixed-reality experience, modifying the mixed-reality experience with one or more virtual content elements.
An embodiment includes analyzing text content of a user query to identify via natural language processing (NLP) a query topic. The embodiment maps the query topic to a topic cluster at a node of a hierarchical model of a text database. The embodiment generates query demand data indicative of demand for the topic cluster based on user queries. The embodiment identifies the topic cluster as a topic-cache candidate based on the query demand data. The embodiment compares an amount of memory required for storing text associated with the first topic cluster to available cache memory. The embodiment caches the text of the topic cluster candidate upon determining that there is sufficient available cache memory space.
A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source/drain.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.
A computer-implemented method for executing a serverless workload on a transient infrastructure is disclosed. The method comprises receiving a request for executing a workload and at least one policy, selecting an infrastructure component of the transient infrastructure for an execution of the workload, wherein the transient infrastructure is implemented utilizing a plurality of geographically distributed computing nodes, and executing the workload on the transient infrastructure. Furthermore, the method comprises upon receiving an interfering event during the execution of the workload causing a stop of the workload execution, freezing the execution of the workload, storing intermediate results and statuses of the workload execution in a cross-domain storage system, terminating the execution of the workload, and continuing the workload execution using the intermediate results and under a constraint defined by the at least one policy.
Using exported data of a machine learning model and a model training environment specification, a resource usage specification and a code module usage specification of the model are identified. A code module installation specification is determined from a code module requirements specification and a target execution environment specification. The code modules specified by the code module installation specification are caused to be installed in the target execution environment. Using data of the updated target execution environment, the updated target execution environment is validated for execution of the model. Execution of the model in the updated target execution environment is simulated. The model is deployed in the updated target execution environment responsive to the simulating being successful.
Mechanisms are provided for dispatching requests to service instances based on data storage boundaries. A request specifying an identity is received and dispatched to a service instance of a data storage boundary, where each data storage boundary is defined by a regulation or policy restricting data storage of specific types of data to computing devices within a specified boundary. A feedback response, specifying a target location, is received from the service instance in response to determining that the service instance cannot access the data because the data is associated with a different data storage boundary. A dynamic dispatch rule specifying the identity and the target location is generated and a subsequent request specifying the identity is processed by executing this dynamic dispatch rule to dispatch the subsequent request directly to a service instance associated with the target location.
A nanosheet diode includes a bookend structure and a central structure. The bookend includes a first semiconductor that is doped as one of the anode and the cathode of the diode, and includes a left block, a right block, and a first stack of spaced-apart nanosheets that horizontally connect the left and right blocks. The central structure includes a second semiconductor that is doped as the other of the anode and the cathode of the diode, and includes a front block, a rear block, and a second stack of nanosheets that are interleaved crosswise into spaces between the first stack of spaced-apart nanosheets and that horizontally connect the front and rear blocks. The bookend structure directly contacts top, bottom, and end surfaces of the second stack of nanosheets of the central structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region (28) located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region (46) located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure (32) located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure (52) located adjacent to at least one of the second source/drain regions of at one of the second FETs.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
To limit resistance variability across a resistive random-access memory (RRAM) call, the disclosure includes an RRAM cell with a resistance spreading layer within the RRAM cell between the top and bottom electrodes of the RRAM cell. The resistance spreading layer is in series with and has no impedance with a filament forming layer of the RRAM cell. The resistance spreading layer may be below the filament forming layer or the resistance spreading layer may be above the filament forming layer. The resistance spreading layer may further be in series with and has no impedance with the bottom electrode or the top electrode.
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
19.
AUTO-WRAPPERING TOOLS WITH GUIDANCE FROM EXEMPLAR COMMANDS
Information received from a graphical user interface (GUI) and a list of user-curated command line patterns are received by an auto-wrapper system, wherein the auto-wrapper system is associated with an analytics workflow service. A module including a parameter space having one or more parameters and options used in the list of user-curated command line patterns is generated, by the auto-wrapper system, wherein content for each parameter is derived from the parameter's presence in the list of user-curated command line patterns combined with the information received from a GUI.
Aspects of the present disclosure relate generally to software development environments and, more particularly, to systems, computer program products, and methods of automating software development, security, and operations (DevSecOps). For example, a computer- implemented method includes receiving, by a processor, a plurality of infrastructure as code files specifying a configuration of a runtime environment for a deployable image of source code in a continuous integration and continuous delivery pipeline for a cloud platform; generating, by the processor, compliance code for at least one file of the plurality of infrastructure as code files; building, by the processor, the deployable image of the source code in the continuous integration and continuous delivery pipeline according to the configuration specified by the plurality of infrastructure as code files and the compliance code; and deploying, by the processor, an instance of the image in the runtime environment.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
21.
SUB-EUV PATTERNING HEATERS FOR BAR MUSHROOM CELL PCM
A phase change material (PCM) memory cell having a metal heater element of sub-EUV dimension. The PCM memory cell includes a bottom electrode of a metal-containing material, a memory cell structure including a phase change material; and a metal heater element of sub-extreme ultraviolet (sub-EUV) dimension situated between and electrically connecting the bottom electrode and PCM memory cell structure. The metal heater element is formed of a circular via structure of sub-EUV dimension and has a seamless metal-nitride fill material. The circular via structure of sub-extreme ultraviolet (sub-EUV) dimension further includes a metal-nitride liner of sub-EUV dimension, the metal-nitride liner of sub-EUV dimension including a thicker metal-nitride liner bottom surface portion and thinner sidewall metal-nitride portions. The thicker metal-nitride liner bottom surface portion improves heat insulation and provides for high resistance/low power switching and reduced amorphous phase change material volumes.
A semiconductor device that includes a first via connecting a backside of the semiconductor device to a frontside of the semiconductor device, and a second via connecting the backside of the semiconductor device to the frontside of the semiconductor device. The first via and the second via are directly connected to at least one different wiring level on the frontside or the backside.
Examples described herein provide a computer-implemented method that includes training a machine learning model. The model is trained by generating a set of training queries using at least one of a query workload and relationships between tables in a database, building a query graph for each of the set of training queries, computing, for each training query of the set of training queries, a selectivity based at least in part on the query graph, and building, based at least in part on the set of training queries, an initial join result distribution as a collection of query graphs.
Deriving insights from time series data can include receiving subject matter expert (SME) input characterizing one or more aspects of a time series. A model template that specifies one or more components of the time series can be generated by translating the SME input using a rule-based translator. A machine learning model based on the model template can be a multilayer neural network having one or more component definition layers, each configured to extract one of the one or more components from time series data input corresponding to an instantiation of the time series. With respect to a decision generated by the machine learning model based on the time series data input, a component-wise contribution of each of the one or more components to the decision can be determined. An output can be generated, the output including the component-wise contribution of at least one of the one or more components.
G06N 3/0442 - Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
25.
TRANSFORMING AN APPLICATION INTO A MICROSERVICE ARCHITECTURE
A system transforms an application for a distributed computing environment is provided. The system comprises one or more memories, and at least one processor coupled to the one or more memories. The system analyzes a description of user intent to extract information for transforming the application. The extracted information indicates functionalities for the distributed computing environment. A plurality of software artifacts of the application are mapped to the functionalities. The plurality of software artifacts form different groups of software artifacts. Remaining software artifacts of the application are assigned into the different groups based on a remaining software artifact corresponding to a mapped software artifact of a group. The different groups correspond to microservices for the distributed computing environment. The microservices for the distributed computing environment are presented based on the different groups.
An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via that couples at least one front end of line transistor to the backside power rail; wherein the backside contact via comprises a pillar based memory device.
A semiconductor device and methods forming the device is disclosed. The semiconductor device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode (136,236) on the MTJ stack. At least one of the bottom electrode and the top electrode (136,236) includes doped SiGeSn.
A controller obtains data stored in one or more data structures generated based on a defined task to be performed for a selected event. The data includes a set of constraints for the defined task. One or more task solutions generated for the defined task using the provided data are obtained. A determination is made as to whether the one or more task solutions include a task solution that satisfies one or more defined criteria. Based on determining that the one or more task solutions do not include the task solution that satisfies the one or more defined criteria, the set of constraints is automatically adjusted to provide an adjusted set of constraints. The adjusted set of constraints is to be automatically provided to a solution generator to be used to obtain the task solution that satisfies the one or more defined criteria.
A computer implemented method includes receiving a list of areas on a subject tape to be read, wherein each area of the list of areas is indicated by a first record number and a last record number corresponding to the area, identifying parameters of a tape drive configured to read the subject tape, wherein the identified parameters of the tape drive contribute to a speed with which the tape drive can read the list of areas, creating a directed graph of the areas on the subject tape based on the identified parameters, wherein the directed graph indicates how long the tape drive will take to read the areas on the subject tape, and determining a fastest reading order of the areas on the subject tape, based, at least in part, on the directed graph and the identified parameters. A computer program product and computer system are also disclosed.
A method, computer system, and a computer program product for ontology adaptation is provided. The present invention may include constructing a process ontology for an industrial floor. The present invention may include generating a digital twin of the industrial floor. The present invention may include performing a simulation of the digital twin using the process ontology. The present invention may include generating one or more new process ontologies based on inefficiencies identified during the simulation. The present invention may include providing one or more recommendations to a user.
G06Q 10/0637 - Strategic management or analysis, e.g. setting a goal or target of an organisation; Planning actions based on goals; Analysis or evaluation of effectiveness of goals
31.
VIRTUAL MACHINE FAILOVER WITH DISAGGREGATED SHARED MEMORY
According to an aspect, a computer-implemented method includes operating a program on a virtual machine on a first device having a local cache memory. Based on a determination that an epoch timer has not expired, aspects include writing one or more updates to the local cache memory and transmitting evicted items from the local cache memory to a shared memory device that is separate from the first device. Based on a determination that an epoch timer has expired, aspects include flushing the local cache memory to the shared memory device, transmitting a virtual CPU state of the virtual machine to the shared memory device, and resetting the epoch timer.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
32.
HETEROGENEOUS GATE ALL AROUND DIELECTRIC THICKNESS
A semiconductor includes a first GAA FET (303) and second GAA FET (305). The second GAA FET includes a first gate dielectric (391) and second gate dielectric (472) within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor (392) within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor (395) within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A 3D compute-in-memory accelerator system (100) and method for efficient inference of Mixture of Expert (MoE) neural network models. The system includes a plurality of compute-in-memory cores (102), each in-memory core including multiple tiers of in-memory compute cells (106). One or more tiers of in-memory compute cells correspond to an expert sub-model of the MoE model. One or more expert sub¬ models are selected (106A) for activation propagation based on a function-based routing (115), the tiers of the corresponding experts being activated based on this function. In one embodiment, this function is a hash-based tier selection function used for dynamic routing of inputs and output activations. In embodiments, the function is applied to select a single expert or multiple experts with input data- based or with layer-activation-based MoEs for single tier activation. Further, the system is configured as a multi-model system with single expert model selection or with a multi-model system with multi-expert selection.
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
G06G 7/16 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division
A voltage source watchdog comprising a passive device is placed in series between a voltage source and a load. The passive device includes an electromigration (EM) joint of known materials that will create an electromigration void after a specified amount of current passes through the EM joint. After a known amount of current as passed through, a void is created and a voltage will no longer be sensed, thus providing a sure safety mode situation. When the voltage source is a battery, the battery life may be extended by selectively enabling voltage measurement operations for the proposed watchdog.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
35.
LOW LOSS TRAVELLING WAVE PARAMETRIC DEVICES USING PLANAR CAPACITORS
A travelling wave parametric device (TWPD) and a method of manufacturing a TWPD, which includes forming a superconducting junction (160) on a substrate. Trenches are etched away through a metal surface and into a layer of dielectric material. The trenches define a plurality of fingers positioned in an interdigitated arrangement of capacitors defined by a metal and a dielectric material (160) that remains from the etched away metal surface and the layer of dielectric material.
A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
37.
GENERATING DC OFFSETS IN FLUX-TUNABLE TRANSMONS WITH PERSISTENT CURRENT LOOPS
A quantum circuit device (200) includes a qubit chip including a plurality of qubits (220) and a plurality of flux tunable couplers (225). A plurality of fixed frequency qubits are arranged in in a lattice structure, wherein each pair of the plurality of fixed frequency qubits is coupled to one flux tunable coupler. A wiring layer is coupled to the qubit chip, and the wiring layer includes a loop (210) constructed of a superconducting material that is inductively coupled to the flux tunable couplers. A flux bias line (205) is constructed of a superconducting material that is different than the superconducting material of the loop, wherein the flux bias line is inductively coupled to both the loop and the flux tunable couplers.
A method, computer system, and computer program product for self-development of resources are provided. The method may include receiving data relating to an activity and a first robotic device assigned to perform the activity. The method may also include creating a knowledge corpus of a second set of one or more robotic devices capable of performing the activity. The method may further include executing a digital twin simulation of a digital twin model of the first robotic device performing the activity. The method may also include in response to determining the first robotic device is unable to complete the activity without incident, identifying within the second set of one or more robotic devices a most comparable robotic device to the first robotic device. The method may further include predicting a modification of the first robotic device. The method may also include attaching one or more resources printed by a 3D printer to the first robotic device.
An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.
A grain-boundary self-aligned resistive memory structure is provided enabling the closely-packed formation of multiple, oxide-based, ReRAM elements in parallel, each with its own compliance resistor. The structure is capable of forming multiple filaments, one per element, with the aim of reducing the variability in the composite ReRAM cell.
A method for acoustic damping of sound clips includes identifying an audio clip for a location of a user in an environment and fragmenting the audio clip into a plurality of sound clips. The method further includes, responsive to determining at least one sound clip from the audio clip requires acoustic damping, performing the acoustic damping on the at least one sound clip, where a damping ratio for the at least one sound clip is altered. The method further includes responsive to determining to stitch the plurality of sound clips, stitching the plurality of sounds clips to form the audio clip, where the plurality of sound clips includes the at least one sound clip with the acoustic damping. The method further includes displaying a visual representation of the audio clip with the plurality of sound clips.
xyy cladded channels, Si channels, or the like) (382, 386, 390). The GAA FETs may have different channel structures, such as relatively different channel lengths. The heterogenous channels may provide improved GAA FET device performance by allowing an ability to tune or adjust channel mobility of GAA FETs in similar region types in different locations or when utilized in different applications.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers. The second cell includes at least one of a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell.
A non-volatile memory (NVM) structure is provided including a proximity heater or a localized heater that is configured to generate Joule heating to increase temperature of a ferroelectric material layer of a ferroelectric memory device higher than a Currie temperature of the ferroelectric material layer. The Joule heating is trigged when tampering in the NVM structure is detected and as a result of the Joule heating memory erasure can occur.
A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.
Techniques and couplers for managing coupling between qubits are presented. A first tuneable coupler qubit (TCQ) can comprise a first frequency mode and a second frequency mode. A second TCQ can comprise a third frequency mode and a fourth frequency mode. First TCQ can be selectively coupled to a first qubit based on the first frequency mode and selectively coupled to the second TCQ based on the second and third frequency modes. Second TCQ can be selectively coupled to a second qubit based on the fourth frequency mode. When certain respective magnetic fluxes are applied to first and second TCQs, ZZ interaction between the first and second qubits can be suppressed. When respective modified magnetic fluxes are applied to first and second TCQs to excite respective frequency modes, coupling can occur, and ZZ interaction and an entangled gate can be created between the first and second qubits.
A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery network (BSPDN) and a second S/D epi region having a second contact directly contacting a first sidewall, a second sidewall, and a top surface of the second S/D epi region, the second contact electrically connected to back-end-of-line (BEOL) components.
A semiconductor structure including a fin of a vertical transistor structure, a top source drain region on a top side of the fin, a bottom source drain region on a bottom side of the fin, and a backside contact below and contacting the bottom source drain region.
A device comprises a data quantum bit, a first quantum bit coupler, a second quantum bit coupler, and an auxiliary quantum bit. The first quantum bit coupler is coupled to the data quantum bit. The second quantum bit coupler is coupled to the first quantum bit coupler. The auxiliary quantum bit is coupled to the second quantum bit coupler. The first quantum bit coupler is configured to operate in a state to suppress interaction between the data quantum bit and the auxiliary quantum bit. The first quantum bit coupler and the second quantum bit coupler are each configured to operate in a respective state to enable interaction between the data quantum bit and the auxiliary quantum bit and entangle a state of the data quantum bit with a state of the auxiliary quantum bit.
A method for minimizing data transfer and storage utilization on cloud object storage systems is disclosed. In one embodiment, such a method replicates a file from a production system to a cloud object storage system. The method determines whether a number of hard links associated with the file is greater than one. In the event the number is greater than one, the method creates, on the cloud object storage system, a special object for the file and associates the file with the special object. Upon creating a hard link on the production system in association with the file, the method replicates the hard link from the production system to the cloud object storage system without replicating data associated with the file. A metadata reference to the special object is added to the hard link on the cloud object storage system. A corresponding system and computer program product are also disclosed.
Container data sharing is provided. A second container of a cluster of containers is started to process a service request in response to detecting a failure of a first container processing the service request. The service request and data generated by the first container that failed stored on a physical external memory device is accessed. The service request and the data generated by the first container that failed is loaded on the second container from the physical external memory device via a dedicated hardware link for high-speed container failure recovery.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
52.
COLLABORATIVE COMPUTATION ACROSS BLOCKCHAIN NETWORKS
A system and method for a multi-party computation (MPC) is provided. In implementations, a method includes identifying a blockchain network and a computing device to perform an MPC based on an index; generating an MPC request including a function to be performed by the blockchain network and the computing device, data required for the function, and a verification policy defining a verification protocol to be performed by the blockchain network and the computing device; sending the MPC request to the blockchain network and the computing device; and receiving responses from a representative computing node of the blockchain network and the computing device, wherein each of the responses includes: an output of an MPC protocol performed by the blockchain network and the computing device to jointly compute the function while keeping the inputs private from one another and private from the computing system; and a proof based on the verification policy.
A computer-implemented method, system and computer program product for applying hypervisor-based containers to a cluster of a container orchestration system. A container runtime of a worker node in the cluster of the container orchestration system issues a request to create a sandbox environment to store a pod containing one or more containers. Upon creating the sandbox environment for each pod to improve isolation, a network tunnel is created between the worker node and the sandbox environment without packet encapsulation in which the sandbox environment shares the same Internet Protocol (IP) address as the other end of the network tunnel in the worker node. Packets may then be routed (forwarded) from the worker node to the sandbox environment via the network tunnel using source routing. By utilizing such source routing, packet looping is prevented. In this manner, hypervisor-based containers may be applied to a cluster of a container orchestration system.
A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first dielectric material and the second caps comprise a second dielectric material different from the first dielectric material.
Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.
A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.
H01L 23/528 - Layout of the interconnection structure
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
57.
SERVERLESS COMPUTING-BASED, CONTINUOUS GATEWAY WATCH FOR DATA CHANGE
A serverless computing-based, continuous gateway watch of a data store for data change process is provided. The process includes the gateway interface of the computing environment receiving a watch request from a user system to monitor the data store for data change. Based on receiving the watch request, the gateway interface invokes a serverless setup service to establish a connection between the gateway interface and the data store of the computing environment to be monitored for data change. Based on receiving, at the gateway interface, a data change indication from the data store, the gateway interface invokes a serverless message process service to mutate the data change indication from the data store into a mutated data change message indicative of a data change at the data store for return to the user system pursuant to the watch request, with the serverless message process service terminating thereafter.
Provided is a damper system for an electronic equipment rack. The damper system may include an electronic equipment rack, a battery back-up unit, and a plurality of rails disposed within the electronic equipment rack. The battery back-up unit is slidably secured to the plurality of rails and tuned to dampen seismic oscillations of the electronic equipment rack during an earthquake. The battery back-up unit is also able to provide power to the electronic equipment disposed in the rack during a power outage.
A semiconductor device includes a ferroelectric random-access memory (FeRAM) cell. The FeRAM includes a ferroelectric dielectric that is annealed to attain its ferroelectric phase by an induced current flow and heating process. The current flow may be induced though a temporary wire that causes heating of the FeRAM cell. The resulting heating or anneal of the ferroelectric dielectric may crystalize the ferroelectric dielectric to embody or result in having ferroelectric properties. The induced current flow and heating process is substantially local to the FeRAM cell, and to ferroelectric dielectric therein, as opposed to a global heating or annealing process in which the entire semiconductor device, or a relatively larger region of semiconductor device, is heated to the requisite annealing temperature of ferroelectric dielectric.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
A semiconductor structure is provided in which a phase change memory (PCM) device region including a PCM is located in a back side of a wafer. A PCM device back side source/drain contact structure connects the PCM to a first source/drain structure of a first field effect transistor (FET) that is present in a front side of the wafer, the second source/drain structure of the first FET is connected to a front side BEOL structure by a front side source/drain contact structure. A logic device region and/or an analog device region can be located laterally adjacent to the PCM device region. A back side power distribution network can be present in the logic device region and/or an analog device region.
An example operation may include one or more of receiving a message from an agent installed at a data replication server, the message comprising a status identifier of a checksum validation of a data replication operation, identifying a latency value associated with the data replication server, determining whether a data loss has occurred based on the status identifier of the checksum validation and the latency value, and in response to a determination that the data loss has occurred, transmitting a notification of the data loss to a computing system associated with the data replication server.
Provisioning business functions is provided. A runtime binary activation code is sent to a nodal edge server that has a needed runtime binary for a set of edge devices to perform a business function. A secure shell protocol connection with root operating system access is established to the nodal edge server that has the needed runtime binary to execute the runtime binary activation code.
Provided are a tape guide roller and tape drive having a guide roller having magnets and bushings to stabilize a roller barrel for a tape medium. The tape guide roller has a roller barrel extending around a vertical axis. The tape medium passes across the roller barrel to guide the tape medium on a tape path. A plurality of magnets positioned with respect to the vertical axis provide an axial force to stabilize the tape guide roller axially.
A memory device (380) and method of forming a projection liner (175) under a mushroom phase change memory device with sidewall electrode (145A, 145B, 145C) process scheme to provide self-aligned patterning of resistive projection liner during sidewall electrode formation.
H10N 70/20 - Multistable switching devices, e.g. memristors
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
65.
CRYOGENIC FILTER MODULES FOR SCALABLE QUANTUM COMPUTING ARCHITECTURES
One or more systems, devices, and/or methods of use provided herein relate to signal filters for scalable quantum computing architectures. According to one embodiment, a device can comprise a circuit board comprising a plurality of layers, wherein various ones of the plurality of layers comprises a different absorptive material, and a plurality of signal lines that pass through the circuit board, wherein a first layer of the circuit board is comprised of a first material that filters a first signal line that traverses through at least the first layer of the plurality of layers.
An example operation may include one or more of identifying an external system that passes an input attribute to a process based on a workflow representation of the process, building a simulator of the external system based on attributes of the external system identified from the workflow representation, simulating future values of the input attribute to be passed to the process by the external system based on the simulator of the external system and a previous simulation run of the process performed via a workflow software application, and executing a new simulation of the process via the workflow software application based on the simulated future values of the input attribute.
Method, computer program product, and computer system are provided. A first migration of a running logical partition (LPAR) is performed from a first-generation computer to a second-generation computer. Availability of a facility differs between the first-and second-generation computers. Upon completion of the first migration, an operating system of the running LPAR detects whether a required facility in use on the first-generation computer is available on the second-generation computer. Operating system takes an action to continue an orderly execution of the LPAR, the operating system, and threads of an application in the LPAR depending on the availability of the required facility. A second migration is performed of the running LPAR from the second-generation computer back to the first-generation computer. The required facility is available on the first-generation computer. The operating system restores access to threads of the application to the required facility.
An approach forming semiconductor structure composed of a first plurality of vertical transport field-effect transistors (11B) in a lower semiconductor layer and a second plurality of vertical transport field-effect transistors (11A) in an upper semiconductor layer. The second plurality of vertical transport field-effect transistors is horizontally offset from the first plurality of vertical transport field-effect transistors by a horizontal distance that is one-half of a contacted gate pitch between adjacent vertical transport field-effect transistors in the same semiconductor layer.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
69.
INTEGRATION OF NANOSHEETS WITH BOTTOM DIELECTRIC ISOLATION AND IDEAL DIODE
Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Backside and frontside contact structures wrapping around source/drain regions provide increased contact areas for electrical connections and allow increased silicide areas. Sidewall metallization of epitaxially grown source/drain regions provides source/drain sidewall contacts that enable wrap-around contact formation on both the front side and the back side of a semiconductor device layer. Front side and back side contact metallization over the source/drain sidewall contacts allows wrap-around contact structures on both sides of the device layer.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 23/528 - Layout of the interconnection structure
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
71.
VERTICAL FIELD-EFFECT TRANSISTOR WITH ISOLATION PILLARS
A semiconductor device includes a first vertical field-effect transistor comprising a first set of vertical fins and a second set of vertical fins separated by a first isolation pillar structure. The semiconductor device further includes a second vertical field-effect transistor adjacent to the first vertical field-effect transistor, the second vertical field-effect transistor comprising a first set of vertical fins and a second set of vertical fins separated by a second isolation pillar structure.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
72.
LOW VOLTAGE SIGNAL PATH IN A RADIO FREQUENCY SIGNAL GENERATOR
A device comprises a voltage-mode filter circuit, a current-mode output circuit, and a regulation circuit. The voltage-mode filter circuit is configured to generate a voltage signal on an output terminal thereof. The current-mode output circuit comprises an input transistor which comprises a gate terminal coupled to the output terminal of the voltage-mode filter circuit, and a source terminal coupled to a regulated node. The regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage for the input transistor to generate a current for biasing the current-mode output circuit.
A system and method for flushing the electrolyte out of an electrolyte flushable battery apparatus during a thermal runaway event. At least one condition of the electrolyte flushable battery apparatus is monitored to detect a potential thermal runaway event based on the at least one condition exceeding a threshold value. In response the inlet valve and outlet valves on the battery apparatus are opened. A flushing liquid is flushed or pumped through the battery apparatus where the flushing liquid enters the apparatus through the inlet valve and leaves the apparatus through the outlet valve. The flushing liquid is then stored in a reservoir.
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
According to one embodiment, a method, computer system, and computer program product for item management is provided. The present invention may include identifying all items within sensor feeds of a sensor set within a venue; creating a list comprising entries for the identified items, the entries comprising a name, location and presence of the items; based on continuously monitoring the sensor feeds, dynamically updating the list to track the location and/or presence of the items in real time; responsive to receiving a query from a user requesting a lost item, selecting an item in the list that matches the name of the lost item; and guiding the user to the location of the selected item.
A method, computer system, and computer program product area provided. A computer transmits a query command to a storage descriptor area of a first disk. The first disk belongs to a dual-site data replication system. The dual-site data replication system provides active-active access to a volume of data stored in an active disk and replicated in a backup disk. The computer receives a response to the query command. The response indicates the active disk and the backup disk for the dual-site data replication system. The computer controls an additional copy of the volume of data at a further remote site based on the active disk.
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
One or more systems, devices, methods of use and/or methods of fabrication herein relate to superconducting monolithic microwave integrated circuits. According to an embodiment, a device comprises a monolithic microwave integrated circuit comprising a superconducting layer coupled to a first circuit element and to a second circuit element, wherein a material of the superconducting layer comprises Tantalum Nitride.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10N 69/00 - Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group
Embodiments of present invention provide a phase change memory (PCM) device. The PCM device includes a first PCM cell with the first PCM cell including an L-shaped phase change element, the L-shaped phase change element having a horizontal portion and a vertical portion on top of the horizontal portion; a selector underneath the horizontal portion of the L-shaped phase change element; a top electrode in contact with a top surface of the vertical portion of the L-shaped phase change element; and a bottom electrode in contact with the selector; and a second PCM cell. A method of manufacturing the PCM device is also provided.
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
A ferroelectric random-access memory (FeRAM) cell (10) is provided. The FeRAM cell (10) includes a vertical channel (310) between a bottom source/drain region and a top source/drain region (630); a gate oxide (320) surrounding the vertical channel (310); and a ferroelectric layer (400) surrounding the gate oxide (320), wherein the ferroelectric layer (400) has two or more sections of different horizontal thicknesses between the bottom source/drain region and the top source/drain region (630). A method of manufacturing the FeRAM cell (10) is also provided.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
79.
AUTHENTICATING KEY-VALUE DATA PAIRS FOR PROTECTING NODE RELATED DATA
A computer-implemented method according to one embodiment includes using a first symmetric key to encrypt a second symmetric key. The first symmetric key is securely loaded inside a hardware security module (HSM) by a key management service before the encryption of the second symmetric key, and a cloud provider only has access to encrypted bits of the first symmetric key. Key data of a key-value-pair of the second symmetric key is used as additional authenticated data (AAD) for the encryption of the second symmetric key. The second symmetric key is used to encrypt value data of the key-value-pair. The method further includes storing the encrypted second symmetric key, the AAD used in the encryption of the second symmetric key, and tag bits created during the encryption of the second symmetric key, to thereafter use for verifying node related data.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
One or more systems, devices, and/or methods of manufacture and/or use provided herein relate to a quantum computing process to achieve higher connectivity of qubits to more than nearest neighbors and/or to a plurality of nearest neighbors. A system can comprise a tunable first coupler coupled to a first qubit, a tunable second coupler coupled to a second qubit, and a junction coupling the first coupler and the second coupler being both parametrically drivable. The first coupler and the second coupler can comprise superconducting quantum interference devices or Josephson junctions. The junction can comprise a central hub or central node separately coupled to the first coupler and the second coupler. The first coupler and the second coupler can be configured to capacitively or inductively couple the first qubit and the second qubit to one another to perform a control-Z (CZ) gate or an iSWAP gate.
Systems, compute-implemented methods, and computer program products to facilitate automated waveform validation are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a waveform comparison component that compares a digital conversion of an analog signal to a reference signal.
Backside contacts wrapping around source/drain regions provide increased contact areas for electrical connections between field-effect transistors and metallization layers. Cavities formed within a device layer expose sidewalls of selected source/drain regions. The backside contacts extend within such cavities and adjoin the sidewall surfaces and bottom surfaces of the selected source/drain regions.
B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
83.
STACKED TRANSISTOR LAYOUT FOR IMPROVED CELL HEIGHT SCALING
A semiconductor structure according to the invention includes a first source region and a first drain region forming a first L-shaped layout, and a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
84.
USER AUTHENTICATION BASED ON PERIODIC SAMPLING OF LOCATION COORDINATES
According to one embodiment, a method, computer system, and computer program product for user authentication. The embodiment may include receiving, from a first device, multiple location coordinates of the first device. The embodiment may include storing, on a second device, a second moving window comprising last n location coordinates of the multiple location coordinates. The embodiment may include receiving, from the first device, a request to access the second device, wherein the request comprises log-in credentials and a first hash value. The embodiment may include computing, on the second device, a second hash value based on the second moving window. The embodiment may include verifying the log-in credentials. The embodiment may include comparing the first hash value and the second hash value. In response to the first and the second hash values being equal, and the log-in credentials being verified, the embodiment may include granting access.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
A processor includes an execution unit for executing a message padding instruction including an operand field indicating a register buffering a message block segment of a message block to be padded and a mode field indicating which hash functions is to be applied to the message block. The execution unit includes a padding circuit configured to receive a message block segment from a register indicated by the operand field, where the message block spans multiple registers in a register file. Based on which hash function is indicated by the mode field, the padding circuit selects a byte location in the message block segment at which to insert at least one padding byte and inserts the at least one padding byte at the byte location within the message block segment. The message block segment as padded by the at least one padding byte is written back to the register file.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G09C 1/00 - Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
86.
HARDWARE-BASED IMPLEMENTATION OF SECURE HASH ALGORITHMS
A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
87.
DISTRIBUTION OF A CRYPTOGRAPHIC SERVICE PROVIDED PRIVATE SESSION KEY TO NETWORK COMMUNICATION DEVICE FOR SECURED COMMUNICATIONS
A secure communication tunnel between user space software and a client device can be established. A private session key can be accessed from a cryptographic service. The private session key can be communicated from the user space software to a network communication device. Outbound session backets can be communicated from the user space software to the network communication device. The network communication device can be configured to generate encrypted outbound session packets by encrypting the outbound session packets using the private session key; communicate to the client device, via the secured communication tunnel, the encrypted outbound session packets; receive from the client device, via the secured communication tunnel, inbound session packets; generate decrypted inbound session packets by decrypting the inbound session packets using the private session key; and communicate the decrypted inbound session packets.
A back side contact structure is provided that directly connects a first electrode (52) of a MRAM, which is present in a back side of a wafer, to a source/drain structure (36) of a transistor. The back side contact is self-aligned to the source/drain structure (36) of the transistor as well as to the first electrode (52) of the MRAM. The close proximity between the MRAM and the source/drain structure (36) increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.
Edge service deployment with network slice invocation is provided, which includes obtaining one or more service-related parameters for network slice invocation to support an edge service instance, and requesting a network slice from a network based on the obtained one or more service-related parameters. The requesting from the network is via a collaboration platform. Further, the edge service deployment and network slice invocation includes receiving from the network, based on requesting of the network slice, network slice invocation codes, and initiating activating of the edge service instance over the network slice of the network using the network slice invocation codes.
A protocol stack can be offloaded to a network communication device. A private session key can be communicated from the user space software to a network communication device via an application programming interface. Outbound session backets can be communicated from the user space software to the network communication device. The network communication device can be configured to process headers in the outbound session packets, generate encrypted outbound session packets by encrypting the outbound session packets using the private session key, and communicate to a client device via the secured communication tunnel, the encrypted outbound session packets. The network communication device also can receive from the client device, via the secured communication tunnel, inbound session packets, generate decrypted inbound session packets by decrypting the inbound session packets using the private session key, process headers in the inbound session packets, and communicate to the user space software, the decrypted inbound session packets.
A computer-implemented method includes receiving an initial request from a client, splitting the initial request into a plurality of split requests based on a business logic, acquiring mapping information associated with the plurality of split requests, determining, based, at least in part, on the mapping information, respective split requests included in the plurality of split requests that are candidates for merger into a merged request, merging the respective split requests that are determined to be candidates for merger into one or more merged requests, and sending the one or more merged requests to one or more nodes capable of processing the one or more merged requests.
Runtime binary migration is provided. A slice of a 5G network is provisioned based on time period and bandwidth requirements in accordance with a service level agreement corresponding to a customer requesting performance of a business function transaction. A runtime binary for invoking the slice of the 5G network is migrated to a nodal edge server for a set of edge devices associated with the nodal edge server to perform the business function transaction using the slice of the 5G network.
H04L 41/0806 - Configuration setting for initial configuration or provisioning, e.g. plug-and-play
H04L 41/0853 - Retrieval of network configuration; Tracking network configuration history by actively collecting configuration information or by backing up configuration information
A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a Galois multiply instruction. The execution unit includes a carryless multiplier configured to multiply operands of the Galois multiply instruction to generate a product. The execution unit further includes a modular reduction circuit configured to receive the product and determine, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product. The execution unit is configured to store the reduced product to the architected register file as a result of the Galois multiply instruction.
G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic
94.
PREEMPTING A QUANTUM PROGRAM IN A QUANTUM COMPUTING DEVICE
A method and quantum computing device for preempting a quantum program. A first quantum circuit is executed by a quantum processor to process a first job of the quantum program for a number of shots, where the number of shots defines how many times a quantum circuit is to be repeatedly executed. The execution of the first quantum circuit to process the first job is then preempted, such as to allow a higher priority and/or shorter-running job to be processed. Upon preempting the execution of the first quantum circuit, the quantum processor executes a second quantum circuit to process a second job (e.g., higher priority and/or shorter-running job to be processed). Upon completion or preemption of the execution of the second quantum circuit to process the second job, the quantum processor completes the execution of the first quantum circuit to process the first job.
A virtual topology is provided in response to an allocation request. The virtual topology is a synchronized subgraph of the physical topology. The synchronized subgraph virtual topology mirrors the physical topology in terms of tree structure. However, merely sharing the physical topology with users/customers is not feasible, as it may reveal additional infrastructure details such as MAC addresses, IP addresses, and the like, that can compromise security and/or jeopardize multi-tenant operations. Disclosed embodiments create virtual topology structures with obfuscated node data, so that important data such as physical IP addresses and/or MAC addresses are hidden from the end-users. Thus, disclosed embodiments provide the benefits of performance enhancement that comes from sharing the topology without the downside of compromising security by revealing physical topology details.
Approaches presented herein enable provisional scheduling of resources in a cloud computing environment. More specifically, a first group request to host an application is obtained. This first group request includes one or more virtual units, which each have one or more topological constraints. One or more resources are scheduled for each of the virtual units. This scheduling includes provisionally allocating the resources to each of the virtual units according to the topological constraints. Each resource comprises a respective weight. In response to obtaining a second group request, the resources are provisionally re-allocated to one or more virtual units of the second group request according to one or more topological constraints of the second group request and the respective weight of each of the resources. This re-allocating minimizes a summation of each respective weight of the resources. A new respective weight is then assigned to each of the resources.
A processor may identify that content is generated for a communication between IoT devices. The processor may identify a source device and a target device of the IoT devices. The processor may analyze the content. The processor may determine a sensitivity of the content. The processor may assign, based on the determining, a security level to either of the source device or the target device.
Techniques are presented for physically incapacitating data storage functionality of a computer data storage device for preventing access of data stored on the device. A security breach can be detected of a device housing a component communicable with a computer and where digital data is storable on the component. A mechanism can be activated for physically disabling the component in the device, in response to the detecting of the security breach. The incapacitating of the component can be a result of the mechanism physically contacting the component, in response to the activation of the mechanism, and the incapacitating of the component renders digital data stored on the component unretrievable by a computer.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Aspects of the present disclosure relate to in-air control regions. Communication between an electronic pen and a device can be established. Two or more in-air control regions above the device can be defined, each in-air control region specifying a set of functions that can be performed by the electronic pen. A determination can be made that the electronic pen is within a first in-air control region of the two or more in-air control regions, the first in-air control region specifying a first set of functions that can be performed by the electronic pen. In response to input received from the electronic pen within the first in-air control region, at least one function of the first set of functions can be executed.
G06F 3/0354 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
100.
ADJUSTABLE RETENTION DEVICE FOR HEAT SINK ASSEMBLY
A heat sink retention device for retaining a heat sink, including a spring, proximate an electronic device in a circuit board. The device includes a first component configured to be attached to a circuit board, and a second component configured to be adjustably attached to the first component, and including an opening configured to retain a portion of a spring of a heat sink. When the first and second components are attached together and the first component is attached to the circuit board, the heat sink retention device is adapted to allow application of a force on the spring in order to retain the heat sink proximate an electronic device mounted on the circuit board.