National Taiwan University

Taiwan, Province of China

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H01L 29/66 - Types of semiconductor device 148
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 85
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate 82
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions 60
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1.

BIOCHIP AND METHOD FOR TRACKING POSTOPERATIVE RECURRENCE STATUS OF PATIENT WITH LUNG ADENOCARCINOMA

      
Application Number 18352651
Status Pending
Filing Date 2023-07-14
First Publication Date 2024-07-18
Owner
  • National Taiwan University (Taiwan, Province of China)
  • Phoenix Silicon International Co. (Taiwan, Province of China)
  • MacKay Medical College (Taiwan, Province of China)
Inventor
  • Pan, Szu-Hua
  • Hsu, Yuan-Ling
  • Li, Ching-Wen
  • Ko, How-Wen
  • Hung, Chung-Lieh

Abstract

The present invention provides a biochip for tracking postoperative recurrence status of a patient with lung adenocarcinoma. The biochip comprises a bare plate layer, the bare plate layer comprises a sensing electrode, and the sensing electrode comprises a biological agent capable of measuring an expression amount of a GPNMB gene. The present invention further provides a method for tracking the postoperative recurrence status of a patient with lung adenocarcinoma. The method comprises the following steps: step one, providing a sample from a patient with lung adenocarcinoma; step two: contacting the sample with a carrier capable of detecting an expression amount of a GPNMB gene; and step three: analyzing a change of the expression amount of the GPNMB gene to track the postoperative recurrence status of the patient with lung adenocarcinoma. The present invention utilizes a mass production capability of a semiconductor lithography process to control a chip cost, achieves an effect of a quick examination by using one drop of blood, can track the postoperative recurrence status of a patient with lung adenocarcinoma in real time so as to perform early treatment, and reduces a medical cost of the patient with lung adenocarcinoma.

IPC Classes  ?

  • G01N 33/574 - Immunoassay; Biospecific binding assay; Materials therefor for cancer

2.

Method of Data Analysis for Long-Term Blood Glucose Concentration Trend

      
Application Number 18113692
Status Pending
Filing Date 2023-02-24
First Publication Date 2024-07-18
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Sun, Chi-Kuang
  • Ye, Xu-Hao
  • Wang, Tzung-Dau

Abstract

A method of data analysis is provided. The method is used for finding a long-term trend of blood glucose concentration. The method builds a model for estimating long-term glycemic variability and long-term blood glucose trajectory. Based on single-erythrocyte-level glycated hemoglobin distribution, the glycemic variability is analyzed. A first analysis method is to give a number. The number shows the level of the historical glycemic variabilities. A second analysis method is to restore the blood glucose trajectory over the past 20 weeks. Based on the single-erythrocyte-level glycated hemoglobin distribution, the present invention easily assesses blood-glucose-related clinical information for about 150 days. Hence, an important complement is obtained for diabetes-related or glucose-monitoring-related clinical applications.

IPC Classes  ?

  • A61B 5/145 - Measuring characteristics of blood in vivo, e.g. gas concentration, pH-value

3.

CURRENT AND RESISTANCE SENSOR

      
Application Number 18335688
Status Pending
Filing Date 2023-06-15
First Publication Date 2024-07-11
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Yang, Chii-Shen
  • Chen, Yu-Hung

Abstract

The present invention provides a current and resistance sensor, comprising: a photo-induced-voltage-generating solution chamber for receiving a photoreceptor-protein-containing solution; and a compound layer on one side of the photo-induced-voltage-generating solution chamber, wherein the compound layer is responsive to changes in the amount of protons in the solution, and the compound layer is provided with a gap corresponding in position to the photo-induced-voltage-generating solution chamber and is thus rendered discontinuous within the photo-induced-voltage-generating solution chamber. The present invention provides a new device and method for monitoring the interactions between biomolecules in real time. The assembly process of the current and resistance sensor is simple, and the sensor can detect small current changes because of the stable nanoampere current output by the photoreceptor protein. In addition, the substance to be tested can be measured without any processing.

IPC Classes  ?

  • G01N 33/487 - Physical analysis of biological material of liquid biological material
  • G01N 33/58 - Chemical analysis of biological material, e.g. blood, urine; Testing involving biospecific ligand binding methods; Immunological testing involving labelled substances
  • G01N 33/68 - Chemical analysis of biological material, e.g. blood, urine; Testing involving biospecific ligand binding methods; Immunological testing involving proteins, peptides or amino acids

4.

ULTRASOUND IMAGE DETECTION SYSTEM AND METHOD THEREOF BASED ON ARTIFICIAL INTELLIGENCE (AI) AUTOMATIC LABELING OF ANATOMICAL STRUCTURES

      
Application Number 18406883
Status Pending
Filing Date 2024-01-08
First Publication Date 2024-07-11
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chen, Wen-Shiang
  • Chen, Chung-Ping
  • Chu, Hsin-Yuan

Abstract

Provided are an ultrasound image detection system and a method thereof based on artificial intelligence (AI) automatic labeling of anatomical structures, including: a receiving module, an image recognition module having an object detection model, an image processing module and a display module, wherein the image recognition module utilizes the object detection model to perform object detection on the image to be recognized, which is received by the receiving module, and then obtains a plurality of object recognition images with object detection results. Then, the image processing module detects missed anatomical structures according to the object detection results of the plurality of object recognition images, thereby outputting an object detection image. Additionally, the display module displays the object detection image. Therefore, the anatomical structures in the ultrasound image can be automatically and instantly recognized by AI so as to provide accurate judgment basis for medical personnel.

IPC Classes  ?

  • G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
  • A61B 8/00 - Diagnosis using ultrasonic, sonic or infrasonic waves
  • A61B 8/08 - Detecting organic movements or changes, e.g. tumours, cysts, swellings
  • G06V 10/77 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using data integration or data reduction, e.g. principal component analysis [PCA] or independent component analysis [ICA] or self-organising maps [SOM]; Blind source separation
  • G06V 10/774 - Generating sets of training patterns; Bootstrap methods, e.g. bagging or boosting
  • G06V 10/776 - Validation; Performance evaluation

5.

POLYCLONAL ANTIBODY TARGETING SODIUM ION CHANNEL, PHARMACEUTICAL COMPOSITION COMPRISING POLYCLONAL ANTIBODY TARGETING SODIUM ION CHANNEL, AND METHOD FOR TREATING AND/OR PREVENTING CARDIAC ARRHYTHMIA BY USING POLYCLONAL ANTIBODY TARGETING SODIUM ION CHANNEL

      
Application Number 18121285
Status Pending
Filing Date 2023-03-14
First Publication Date 2024-06-27
Owner National Taiwan University (Taiwan, Province of China)
Inventor Tsai, Chia-Ti

Abstract

The present disclosure provides a polyclonal antibody targeting sodium ion channel, which binds to a sodium Nav1.5 channel. The present disclosure also provides a pharmaceutical composition including the polyclonal antibody targeting sodium ion channel, and a method for treating and/or preventing cardiac arrhythmia by using the polyclonal antibody targeting sodium ion channel.

IPC Classes  ?

  • C07K 16/28 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from animals or humans against receptors, cell surface antigens or cell surface determinants
  • A61K 9/00 - Medicinal preparations characterised by special physical form
  • A61P 9/06 - Antiarrhythmics

6.

AUTOMATIC CALCULATION METHOD OF GRAY-TO-WHITE-MATTER RATIO FOR HEAD COMPUTED TOMOGRAPHY OF PATIENTS WITH CARDIAC ARREST

      
Application Number 18393588
Status Pending
Filing Date 2023-12-21
First Publication Date 2024-06-27
Owner
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY HOSPITAL (Taiwan, Province of China)
Inventor
  • Huang, Chien-Hua
  • Chi, Chien-Yu
  • Wang, Liang-Wei
  • Su, Yu-Jen
  • Wang, Weichung
  • Tsai, Hsin-Han
  • Hsu, Cheyu

Abstract

An automatic calculation method of gray-to-white-matter ratio for head computed tomography of patients with cardiac arrest is disclosed and includes an image registration step, a K-means segmentation step, a segmentation refinement step and a GWR calculation step. Measure the gray-white-matter ratio through brain computed tomography early after cardiac arrest to automatically identify the corpus callosum, caudate nucleus, putamen, and posterior branch of the internal brain cyst. It is a 3D three-dimensional structure rather than a manually selected flat circular area to evaluate the effectiveness of predicting neurological prognosis at discharge.

IPC Classes  ?

  • G06T 7/00 - Image analysis
  • G06T 5/40 - Image enhancement or restoration by the use of histogram techniques
  • G06T 7/11 - Region-based segmentation
  • G16H 30/40 - ICT specially adapted for the handling or processing of medical images for processing medical images, e.g. editing
  • G16H 50/30 - ICT specially adapted for medical diagnosis, medical simulation or medical data mining; ICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for individual health risk assessment

7.

SEMICONDUCTOR CHIP WITH EMBEDDED MICROFLUIDIC CHANNELS AND METHOD OF FABRICATING THE SAME

      
Application Number 18393670
Status Pending
Filing Date 2023-12-22
First Publication Date 2024-06-27
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Chien, Jun-Chau
  • Weng, Wei-Yang

Abstract

A semiconductor chip with embedded microfluidic channels includes a semiconductor substrate, a circuit structure layer, a first microfluidic channel and a micro via hole. The circuit structure layer includes a first metal layer, a first insulation layer and a second metal layer sequentially disposed on a substrate surface of the semiconductor substrate along a stacking direction. A plurality of first bridge patterns penetrates the first insulation layer, and are each electrically connected to the first metal layer and/or the second metal layer. The first microfluidic channel and the micro via hole are embedded in the circuit structure layer. In the stacking direction, a first height of the first microfluidic channel is equal to a first thickness of the first metal layer. In any direction parallel to the substrate surface, a hole width of the micro via hole is equal to a pattern width of each of the first bridge patterns.

IPC Classes  ?

  • B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
  • B81B 1/00 - Devices without movable or flexible elements, e.g. microcapillary devices
  • C12M 1/34 - Measuring or testing with condition measuring or sensing means, e.g. colony counters
  • C12M 3/06 - Tissue, human, animal or plant cell, or virus culture apparatus with filtration, ultrafiltration, inverse osmosis or dialysis means

8.

METHOD FOR PREPARING SEMICONDUCTOR LAYER

      
Application Number 18109430
Status Pending
Filing Date 2023-02-14
First Publication Date 2024-06-27
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chou, Yi-Chia
  • Huang, Chang-Hsun

Abstract

A method for preparing a semiconductor layer comprises the following steps: providing a mica substrate; depositing a plurality of semiconductor films on the mica substrate to form a semiconductor substrate; and cooling the semiconductor substrate at a cooling rate to separate the plurality of semiconductor films from the mica substrate to obtain a semiconductor layer, wherein the cooling rate ranges from 10° C./min to 50° C./min. Herein, the plurality of semiconductor films comprise a first semiconductor film and a second semiconductor film, the first semiconductor film is formed at a first temperature, the second semiconductor film is formed at a second temperature, the first temperature is lower than the second temperature, and the first semiconductor film is disposed between the mica substrate and the second semiconductor film.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

9.

PHYSICALLY UNCLONABLE FUNCTION CELL AND OPERATION METHOD OF THE SAME

      
Application Number 18600230
Status Pending
Filing Date 2024-03-08
First Publication Date 2024-06-27
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chung, Chia-Che
  • Tsen, Chia-Jung
  • Tsou, Ya-Jui
  • Liu, Chee-Wee

Abstract

A device is provided. The device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.

IPC Classes  ?

  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H03K 19/1776 - Structural details of configuration resources for memories

10.

ELECTRONIC DEVICE WITH CONDUCTIVE RESONATOR

      
Application Number 18443839
Status Pending
Filing Date 2024-02-16
First Publication Date 2024-06-06
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Li, Jiun-Yun
  • Chen, Shih-Yuan
  • Chang, Yao-Chun
  • Huang, Ian
  • Chen, Chiung-Yu

Abstract

An electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is over the depletion gates. The conductive resonator is over the depletion gates and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are on opposite sides of the accumulation gate. The third portion interconnects the first and second portions of the conductive resonator and across the depletion gates. A bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate.

IPC Classes  ?

  • G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
  • B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
  • H10N 60/01 - Manufacture or treatment
  • H10N 60/80 - Constructional details

11.

QUANTUM COMPUTATION DEVICE AND OPERATION THEREOF

      
Application Number 18366577
Status Pending
Filing Date 2023-08-07
First Publication Date 2024-05-30
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Goan, Hsi-Sheng
  • Huang, Chia-Hsien

Abstract

A method is provided, including: applying a magnetic field according to a two-qubit gate operation performed with a quantum device; transmitting a voltage signal to a gate structure, arranged above first and second quantum dots in the quantum device, to generate a coupling signal that includes a first sine squared wave; and performing, by the magnetic field and the coupling signal, the two-qubit gate operation to the first and second qubits in the first and second quantum dots.

IPC Classes  ?

  • H03K 19/195 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
  • G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

12.

Method for promoting the stemness and/or transdifferentiation of acinar cells

      
Application Number 18057051
Status Pending
Filing Date 2022-11-18
First Publication Date 2024-05-23
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Lou, Pei-Jen
  • Young, Tai-Horng
  • Cheng, Ching-Chia
  • Lin, Mei-Chun
  • Chen, Hisn-Lin

Abstract

The present application provides a method for promoting the sternness and/or transdifferentiation of acinar cells, comprising the following steps: providing an acinar cell, transfecting a plasmid into the acinar cell, and culturing the transfected acinar cell, wherein the plasmid contains a genetic material for overexpression of N-acetylglucosaminyltransferase V (GnT-V).

IPC Classes  ?

13.

COMBINED USE OF RARE-EARTH ELEMENT DOPED CALCIUM CARBONATE PARTICLES WITH ULTRASOUND FOR REDUCING LOCAL FAT

      
Application Number 17989541
Status Pending
Filing Date 2022-11-17
First Publication Date 2024-05-23
Owner
  • National Health Research Institutes (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Lin, Feng-Huei
  • Chen, Gin-Shin
  • Shih, Ping-Yu
  • Chen, Ching-Yun
  • Lin, Li-Ze
  • Kuan, Che-Yung
  • Chen, Zhi-Yu
  • Yang, I-Hsuan

Abstract

The present invention relates to a method for reducing localized fat deposits in a subject in need thereof in need thereof by topically treating the subject with rare-earth element doped calcium carbonate particles in combination with low-intensity ultrasound. The rare-earth element doped calcium carbonate particles have good biocompatibility and can increase reactive oxygen species (ROS) production and produce carbon dioxide (CO2) and calcium ions (Ca2+) in the region of administration under the ultrasonic irradiation. The method of the present invention is effective in inducing adipocyte necrosis, inhibiting adipogenesis, and decreasing body weight and useful for body sculpture.

IPC Classes  ?

  • A61K 41/00 - Medicinal preparations obtained by treating materials with wave energy or particle radiation
  • A61K 33/10 - Carbonates; Bicarbonates
  • A61N 7/00 - Ultrasound therapy

14.

METHOD OF OPERATING MEMORY CELL

      
Application Number 18191668
Status Pending
Filing Date 2023-03-28
First Publication Date 2024-05-23
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
  • National Taiwan Normal University (Taiwan, Province of China)
Inventor
  • Hsiang, Kuo-Yu
  • Lee, Min-Hung

Abstract

A method of operating a memory cell includes the following steps. A first plurality of bias operations is performed to the memory cell using a first voltage, wherein the memory cell comprises a variable resistance pattern, and the first voltage of each cycle of the first plurality of bias operations has a same first polarity. The memory cell is determined whether reaches a fatigue threshold. After the determination determines that the memory cell reaches the fatigue threshold, a second plurality of bias operations is performed to the memory cell using a second voltage, wherein the second voltage of each cycle of the second plurality of bias operations has a same second polarity, and the second polarity is opposite to the first polarity.

IPC Classes  ?

  • G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

15.

SEMICONDUCTOR DEVICE AND FORMATION METHOD

      
Application Number 18410409
Status Pending
Filing Date 2024-01-11
First Publication Date 2024-05-09
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Ye, Hung-Yu
  • Huang, Yu-Shiang
  • Tu, Chien-Te
  • Liu, Chee-Wee

Abstract

A device includes a first channel structure, a second channel structure, and a gate structure. The first channel structure connects a first source region and a first drain region, and includes alternating stacking first semiconductor layers and second semiconductor layers. The second semiconductor layers have a width smaller than a width of the first semiconductor layers. The second channel structure connects a second source region and a second drain region. The second channel structure includes alternating stacking third semiconductor layers and fourth semiconductor layers. The fourth semiconductor layers have a width smaller than a width of the third semiconductor layers. The gate structure wraps around the first and second channel structures.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/8234 - MIS technology

16.

ELECTROLYTIC CELL AND ELECTROLYTIC CELLS IN SERIES, WHICH CAN BE USED AS CHLORALKALI ELECTROLYTIC CELL AND PROCESS CO2

      
Application Number 18314362
Status Pending
Filing Date 2023-05-09
First Publication Date 2024-05-09
Owner
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
  • FORMOSA PLASTICS CORPORATION (Taiwan, Province of China)
Inventor
  • Chen, Hao-Ming
  • Chen, Tai-Lung
  • Hung, Wan-Tun
  • Chen, Yu-Cheng
  • Huang, Kuo-Ming
  • Yen, Fu-Da
  • Liao, Che-Jui

Abstract

An electrolytic cell includes a cation exchange membrane, a cathode compartment, and an anode compartment. The cathode compartment includes a gas diffusion electrode and a flow channel element, in which the flow channel element is between the cation exchange membrane and the gas diffusion electrode, and has a plurality of flow channels arranged in parallel with each other. The anode compartment includes an anode mesh, in which the cation exchange membrane is between the anode mesh and the flow channel element. A distance between the anode mesh and the gas diffusion electrode is substantially equal to the sum of a first thickness of the cation exchange membrane and a second thickness of the flow channel element. The novel electrolytic cell can combine with a chloralkali electrolytic cell to deal with gaseous CO2 and produce products, e.g., synthesis gas, for other purposes.

IPC Classes  ?

  • C25B 1/23 - Carbon monoxide or syngas
  • C25B 1/26 - Chlorine; Compounds thereof
  • C25B 5/00 - Electrogenerative processes, i.e. processes for producing compounds in which electricity is generated simultaneously
  • C25B 9/63 - Holders for electrodes; Positioning of the electrodes
  • C25B 11/032 - Gas diffusion electrodes
  • C25B 11/081 - Electrodes formed of electrocatalysts on a substrate or carrier characterised by the electrocatalysts material consisting of a single catalytic element or catalytic compound the element being a noble metal
  • C25B 11/091 - Electrodes formed of electrocatalysts on a substrate or carrier characterised by the electrocatalysts material consisting of two or more catalytic elements or catalytic compounds
  • C25B 13/00 - Diaphragms; Spacing elements
  • C25B 15/08 - Supplying or removing reactants or electrolytes; Regeneration of electrolytes

17.

pH-RESPONSIVE HYDROGEL AND MANUFACTURING METHOD THEREOF

      
Application Number 18075339
Status Pending
Filing Date 2022-12-05
First Publication Date 2024-04-18
Owner
  • National Health Research Institutes (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Lin, Feng-Huei
  • Tang, Rui-Chian
  • Chen, Tzu-Chien

Abstract

A pH-responsive hydrogel, which is synthesized by using mixed pectin and sucralfate treated with a small amount of acid to form a pH-responsive hydrogel. The pH-responsive hydrogel can form a temporary coating on the surface of the gastrointestinal tract to reduce excessive nutrient absorption, and exhibits excellent barrier properties and mucosal adhesion effects, which are useful for reducing blood sugar rise and weight gain, the liver fat accumulation, body fat accumulation and blood low-density lipoprotein that have a significant effect. In addition, the technical principles disclosed in the pH-responsive hydrogel should be applied to other polymer materials to manufacture different pH-responsive hydrogels.

IPC Classes  ?

18.

TRANSMISSION DEVICE FOR SUPPRESSING GLASS FIBER EFFECT

      
Application Number 18058381
Status Pending
Filing Date 2022-11-23
First Publication Date 2024-04-18
Owner
  • UNIMICRON TECHNOLOGY CORP. (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Wang, Chin-Hsun
  • Wu, Ruey-Beei
  • Chen, Ching-Sheng
  • Hung, Chun-Jui
  • Liao, Wei-Yu
  • Chang, Chi-Min

Abstract

A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.

IPC Classes  ?

19.

TRANSMISSION DEVICE

      
Application Number 18058799
Status Pending
Filing Date 2022-11-25
First Publication Date 2024-04-18
Owner
  • UNIMICRON TECHNOLOGY CORP. (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Wang, Yu-Kuang
  • Wu, Ruey-Beei
  • Chen, Ching-Sheng
  • Huang, Chun-Jui
  • Liao, Wei-Yu
  • Chang, Chi-Min

Abstract

A transmission device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.

IPC Classes  ?

20.

REACTION PLATFORM FOR ACCELERATED BIOCHEMICAL REACTION

      
Application Number 18358320
Status Pending
Filing Date 2023-07-25
First Publication Date 2024-04-18
Owner
  • National Taiwan University (Taiwan, Province of China)
  • National Taiwan University Hospital (Taiwan, Province of China)
  • Academia Sinica (Taiwan, Province of China)
Inventor
  • Wang, An-Bang
  • Chen, Shih-Yu
  • Su, Tung-Hung
  • Chu, Chia-Chi
  • Yen, Chia-Chien
  • Chiang, Yu-Wei

Abstract

The present invention relates to a reaction platform, which comprises: a machine body with a bottom plate for placing non-porous substrates; and a coater module configured on the top of the machine body and capable of maintaining a preset of a predetermined height for moving along the surface of non-porous substrate, wherein the coater module has one or more slits, and a target liquid can be directly injected or sucking in from the outside of the coater module through the slit, and spreading the target liquid onto a surface of the non-porous substrate while moving along the non-porous substrate; wherein the surface of the non-porous substrate has a target to be coated. The reaction platform of the present invention can not only save time, labor and cost, but also have accurate and reproducible experimental results, showing better results than traditional methods.

IPC Classes  ?

21.

METHOD FOR NON-RESIST NANOLITHOGRAPHY

      
Application Number 18525131
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-04-11
Owner
  • Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Chen, Miin-Jang
  • Tsai, Kuen-Yu
  • Liu, Chee-Wee

Abstract

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks

22.

MESOSCALE NONLINEAR OPTICAL GIGASCOPE SYSTEM WITH REAL-TIME GIGAPIXEL MOSAIC-STITCHING AND DIGITAL DISPLAY

      
Application Number 17963201
Status Pending
Filing Date 2022-10-11
First Publication Date 2024-04-11
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Sun, Chi-Kuang
  • Borah, Bhaskar Jyoti

Abstract

A mesoscale nonlinear optical gigascope (mNLOG) system is provided to assist with rapid gigapixel resonant-raster laser-scanning and post-processing-free digital display of a centimeter-scale biological specimen in real-time. The mNLOG system enables a half-a-micron digital resolution with satisfied Nyquist-Shannon criterion while providing an aliasing-free optically-sectioned cumulative point-scanning area ranging from 1 square millimeter (mm) up-to 400 square mm. The mNLOG system is configured to perform a rapid artifact-compensated two-dimensional large-field mosaic-stitching (rac2D-LMS) process, so as to provide post-processing-free gigapixel mosaic-stitching and real-time digital display with a sustained effective data throughput of at least 500 Megabits per second (Mbps).

IPC Classes  ?

  • G02B 1/00 - Optical elements characterised by the material of which they are made; Optical coatings for optical elements

23.

Rapid fresh digital-pathology method

      
Application Number 17963247
Status Pending
Filing Date 2022-10-11
First Publication Date 2024-04-11
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Sun, Chi-Kuang
  • Borah, Bhaskar Jyoti
  • Tseng, Yao-Chen

Abstract

A rapid fresh digital-pathology (RFP) method for assessing an excised unfixed biological specimen stained with hematoxylin (H) or eosin (E) or both hematoxylin and eosin (HE) staining dyes. The RFP method is assisted by a rapid tissue staining (RTS) procedure which is performed on the excised unfixed biological specimen, involving a short fixation; an H-staining; a rinsing; a bluing; an E-staining; a rinsing; and finally, a covering of a stained specimen with a coverslip. The RFP method is further assisted by a multimodal nonlinear optical laser-raster-scanning approach to provide with a nonlinear multi-harmonic generation and/or a nonlinear multi-photon excitation fluorescence signal(s) for multichannel digitization and real-time digital display of H- or E- or HE-specific histopathological features while providing a centimeter-scale imaging area, a submicron digital resolution, and a sustained effective data throughput of at least 500 Megabits per second (Mbps).

IPC Classes  ?

24.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

      
Application Number 18163019
Status Pending
Filing Date 2023-02-01
First Publication Date 2024-03-28
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chou, Chun-Yi
  • Chuu, Chih-Piao
  • Chen, Miin-Jang

Abstract

A method includes following steps. A first precursor is pulsed over a substrate such that first precursor adsorbs on a first region and a second region of the substrate. A first plurality of the first precursor adsorbing on the first region is then removed using a plasma, while leaving a second plurality of the first precursor adsorbing on the second region. A second precursor is then pulsed to the substrate to form a monolayer of a film on the second region and a material on the first region. The material is then removed using a plasma. The substrate is biased during removing the material.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/40 - Oxides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/56 - After-treatment

25.

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18182991
Status Pending
Filing Date 2023-03-13
First Publication Date 2024-03-28
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Lin, Shih-Yen
  • Tsai, Po-Cheng

Abstract

A memory device includes a substrate, a 2-D material channel layer, a 2-D material charge storage layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The 2-D material channel layer is over the substrate. The 2-D material charge storage layer is over the 2-D material channel layer. The 2-D charge storage layer and the 2-D material channel layer include the same chalcogen atoms. The source/drain contacts are over the 2-D material channel layer. The gate dielectric layer covers the source/drain contacts and the 2-D material charge storage layer. The gate electrode is over the gate dielectric layer.

IPC Classes  ?

  • H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

26.

PCR DETECTION DEVICE AND SYSTEM

      
Application Number 17935917
Status Pending
Filing Date 2022-09-27
First Publication Date 2024-03-28
Owner
  • National Taiwan University (Taiwan, Province of China)
  • Taipei Medical University (Taiwan, Province of China)
Inventor
  • Sheen, Horn-Jiunn
  • Wei, Pei-Kuen
  • Fan, Yu-Jui
  • Juan, Po-Han
  • Huang, Yung-Yu

Abstract

The present disclosure provide a detection device of microfluidic polymerase chain reaction (PCR) and a detection system including the same. This all-in-one device and system may be used to detect at least one biological detection chip, so that can amplify gene fragments at the front-end and detect them at the back-end immediately, decreasing the time required for the analysis, enabling real-time, low-cost, and rapid detection of various viruses, such as EBV and COVID-19, without compromising accuracy or sensitivity.

IPC Classes  ?

  • B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
  • B01L 7/00 - Heating or cooling apparatus; Heat insulating devices
  • C12M 1/38 - Temperature-responsive control

27.

PIEZOELECTRIC MATERIAL COMPOSITE MEMBRANE ACOUSTIC COMPONENT WITH BROADBAND AND HIGH SOUND QUALITY AND MANUFACTURING METHOD THEREOF

      
Application Number 17981078
Status Pending
Filing Date 2022-11-04
First Publication Date 2024-03-28
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Huang, Yu-Hsi
  • Huang, Yu-Chen

Abstract

A piezoelectric material composite membrane acoustic component with broadband and high sound quality comprises a vibrating membrane which is an electrically conductive membrane, a supporting frame having a hollow portion penetrating the supporting frame, a piezoelectric plat set including a first-piezoelectric-plate and a second-piezoelectric-plate formed on and electrically connected to the first-piezoelectric-plate and an AC power. A fixing portion of the vibrating membrane is fixed by the supporting frame. Each of the first-piezoelectric-plate and the second-piezoelectric-plate includes a top-electrode-layer, a piezoelectric-layer and a bottom-electrode-layer. The bottom-electrode-layer of the first-piezoelectric-plate is fixed on and electrically connected to a piezoelectric-plate fixing portion of the vibrating membrane. A spacing portion of the vibrating membrane is between the fixing portion and the piezoelectric-plate fixing portion. The AC power includes a first electrode and a second electrode electrically connected to the top-electrode-layer of the first-piezoelectric-plate and the vibrating membrane, respectively.

IPC Classes  ?

  • H10N 30/20 - Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
  • H10N 30/092 - Forming composite materials
  • H10N 30/85 - Piezoelectric or electrostrictive active materials

28.

GENE THERAPY FOR AADC DEFICIENCY

      
Application Number 18524967
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-03-28
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Pykett, Mark
  • Thorn, Richard
  • Hwu, Wuh-Liang ("paul")

Abstract

The present invention is directed to compositions and methods for treating aromatic L-amino acid decarboxylase (AADC) deficiency. This invention includes a method of treating AADC deficiency in a pediatric subject, comprising the steps of: (a) providing a pharmaceutical formulation comprising an rAAV2-hAADC vector, (b) stereotactically delivering the pharmaceutical formulation to at least one target site in the brain of the subject in a dose of an amount at least about 1.8×1011 vg; wherein delivering the pharmaceutical formulation to the brain is optionally by frameless stereotaxy, and optionally wherein the dose is an amount of at least about 2.4×1011 vg and in some embodiments wherein the pharmaceutical formulation comprises a rAAV2-hAADC vector concentration of about 5.7×1011 vg/mL. This invention is also directed to methods for treating aromatic L-amino acid decarboxylase (AADC) deficiency, wherein the method optionally further comprises the step of administering a therapeutically effective dose of dopamine-antagonist to the subject such as risperidone. This invention is also directed to methods for treating aromatic L-amino acid decarboxylase (AADC) deficiency, wherein the method optionally comprises providing a pharmaceutical formulation comprising an rAAV2-hAADC vector, and empty capsids.

IPC Classes  ?

  • A61K 48/00 - Medicinal preparations containing genetic material which is inserted into cells of the living body to treat genetic diseases; Gene therapy
  • A61K 9/51 - Nanocapsules
  • A61K 31/4515 - Non-condensed piperidines, e.g. piperocaine having a butyrophenone group in position 1, e.g. haloperidol
  • A61K 31/5513 - 1,4-Benzodiazepines, e.g. diazepam
  • A61P 25/00 - Drugs for disorders of the nervous system
  • C12N 9/88 - Lyases (4.)
  • C12N 15/113 - Non-coding nucleic acids modulating the expression of genes, e.g. antisense oligonucleotides
  • C12N 15/62 - DNA sequences coding for fusion proteins
  • C12N 15/85 - Vectors or expression systems specially adapted for eukaryotic hosts for animal cells
  • C12N 15/86 - Viral vectors
  • C12N 15/864 - Parvoviral vectors

29.

INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME

      
Application Number 18151963
Status Pending
Filing Date 2023-01-09
First Publication Date 2024-03-28
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Lin, Shih-Yen
  • Chang, Che-Jia

Abstract

A method includes performing a first deposition process to form a first graphene layer over a substrate, the first deposition process being performed under a first temperature and a first pressure; performing a second deposition process to form a second graphene layer over the first graphene layer, the second deposition process being performed under a second temperature and a second pressure, in which the first temperature is higher than the second temperature, and the first pressure is lower than the second pressure; forming a gate structure over the second graphene layer; and forming source/drain contacts on opposite sides of the gate structure and electrically connected to the first and second graphene layers.

IPC Classes  ?

  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/8234 - MIS technology
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/66 - Types of semiconductor device

30.

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

      
Application Number 18151304
Status Pending
Filing Date 2023-01-06
First Publication Date 2024-03-21
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Lin, Shih-Yen
  • Tsai, Po-Cheng

Abstract

A method includes forming a gate dielectric layer over a gate electrode layer; forming a 2-D material layer over the gate dielectric layer; forming source/drain contacts over source/drain regions of the 2-D material layer, in which each of the source/drain contacts includes an antimonene layer and a metal layer over the antimonene layer; and after forming the source/drain contacts, removing a first portion of the 2-D material layer exposed by the source/drain contacts, while leaving a second portion of the 2-D material layer remaining over the gate dielectric layer as a channel region.

IPC Classes  ?

  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/8234 - MIS technology
  • H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L 29/22 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds

31.

SEMICONDUCTOR DEVICE HAVING 2D CHANNEL LAYER

      
Application Number 18515148
Status Pending
Filing Date 2023-11-20
First Publication Date 2024-03-14
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Wang, Yun-Yuan
  • Hsiao, Chih-Hsiang
  • Ni, I-Chih
  • Wu, Chih-I

Abstract

A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

IPC Classes  ?

  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/40 - Electrodes
  • H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions

32.

METHOD OF DETECTING SLEEP DISORDER BASED ON EEG SIGNAL AND DEVICE OF THE SAME

      
Application Number 18465927
Status Pending
Filing Date 2023-09-12
First Publication Date 2024-03-14
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Lin, Phone
  • Lin, Xin-Xue

Abstract

The present invention discloses a method of detecting sleep disorder based on an EEG signal and device of the same. The method and device only need an EEG signal for analysis to determine sleep disorder and abnormal score. Therefore, the method and device may reduce cost of collecting physical information and avoid from uncomfortable feeling of user who wears several sensors.

IPC Classes  ?

  • A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
  • A61B 5/372 - Analysis of electroencephalograms

33.

SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

      
Application Number 18507957
Status Pending
Filing Date 2023-11-13
First Publication Date 2024-03-14
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chen, Miin-Jang
  • Yi, Sheng-Han
  • Lu, Chen-Hsuan

Abstract

A method includes forming source/drain regions in a semiconductor substrate; depositing a zirconium-containing oxide layer over a channel region in the semiconductor substrate and between the source/drain region; forming a titanium oxide layer in contact with the zirconium-containing oxide layer; forming a top electrode over the zirconium-containing oxide layer, wherein no annealing is performed after depositing the zirconium-containing oxide layer and prior to forming the top electrode.

IPC Classes  ?

  • H01L 29/51 - Insulating materials associated therewith
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

34.

METHOD AND KIT FOR MONITORING NON-SMALL CELL LUNG CANCER

      
Application Number 18279824
Status Pending
Filing Date 2022-03-01
First Publication Date 2024-02-29
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Tsai, Hsing-Chen
  • Yu, Chong-Jen
  • Lu, Hsuan-Hsuan
  • Lin, Shu-Yung
  • Huang, Yi-Jhen
  • Dong, Chen-Yuan

Abstract

Provided is a method for diagnosing and monitoring progression of cancer or effectiveness of a therapeutic treatment. The method includes detecting a methylation level of at least one gene in a biological sample containing circulating free DNA. Also provided are primer pairs and probes for diagnosis or prognosis of cancer in a subject in need thereof.

IPC Classes  ?

  • C12Q 1/6886 - Nucleic acid products used in the analysis of nucleic acids, e.g. primers or probes for diseases caused by alterations of genetic material for cancer

35.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 17890080
Status Pending
Filing Date 2022-08-17
First Publication Date 2024-02-22
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Tu, Chien-Te
  • Liu, Chee-Wee

Abstract

A method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of sacrificial layers and a plurality of channel layers alternately arranged over the semiconductor substrate, and each of the sacrificial layers is a multi-layer film comprising a bottom epitaxial layer, a middle epitaxial layer over the bottom epitaxial layer, and a top epitaxial layer over the middle epitaxial layer, wherein the middle epitaxial layer has a lower germanium concentration than the bottom and top epitaxial layers; laterally recessing the sacrificial layers to form sidewall recesses alternating with the channel layers; forming inner spacers in the sidewall recesses; forming source/drain epitaxial structures on opposite sides of the channel layers.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/786 - Thin-film transistors
  • H01L 21/8234 - MIS technology

36.

PROBIOTIC COMPOSITIONS AND USES THEREOF

      
Application Number 18502098
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-02-22
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Chen, Ming-Ju
  • Huang, Hsiao-Wen

Abstract

An isolated bacterial strain of Lactiplantibacillus plantarum subsp. plantarum MFM 30-3 deposited under the DSMZ Accession No. DSM 34213 is provided; a probiotic composition including an Lactiplantibacillus plantarum subsp. plantarum MFM 30-3 and optionally, one or more additional probiotic organisms that enhance the probiotic activity of the Lactiplantibacillus plantarum subsp. plantarum MFM 30-3 is also provided; and a method for preventing or treating chronic kidney disease in a subject in need thereof including: administering to the subject a pharmaceutically effective amount of the probiotic composition including an isolated bacterial strain of Lactiplantibacillus plantarum subsp. plantarum MFM 30-3, and optionally, one or more additional probiotic organisms that enhance the probiotic activity of the Lactiplantibacillus plantarum subsp. plantarum MFM 30-3 is further provided.

IPC Classes  ?

  • A61K 35/747 - Lactobacilli, e.g. L. acidophilus or L. brevis
  • A23L 33/135 - Bacteria or derivatives thereof, e.g. probiotics
  • A61P 13/12 - Drugs for disorders of the urinary system of the kidneys
  • C12N 1/20 - Bacteria; Culture media therefor

37.

Computing-in-memory circuitry

      
Application Number 17883630
Grant Number 12009054
Status In Force
Filing Date 2022-08-09
First Publication Date 2024-02-15
Grant Date 2024-06-11
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Hsu, Ying-Tuan
  • Liu, Tsung-Te
  • Chiueh, Tzi-Dar

Abstract

A computing-in-memory circuitry includes multiple digital-to-analog converters, multiple computing arrays, and multiple charge processing networks. The digital-to-analog converters convert external data into input data and the digital-to-analog converters are connected in series with a corresponding plurality of output capacitor pairs. The computing arrays receive the input data from both ends and execute a computation to output a first computing value. The charge processing networks receive and accumulate the first computing values over a predetermined time interval through switching pairs in series with the output capacitor pairs. The charge processing networks evenly distribute charges of the first computing value to selected output capacitor pairs and compare voltage differences between two ends of the output capacitor pairs to output a second computing value.

IPC Classes  ?

  • G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
  • G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
  • G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

38.

GROUP-BASED RADIO RESOURCE ALLOCATION BETWEEN A TN AND AN NTN NETWORKS

      
Application Number 18356106
Status Pending
Filing Date 2023-07-20
First Publication Date 2024-02-08
Owner
  • MEDIATEK INC. (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Lee, Hao-Wei
  • Fu, I-Kang
  • Chen, Chun-Chia
  • Liao, Chen-I
  • Wei, Hung-Yu

Abstract

A method for performing radio resource allocation in a TN-NTN mixed system is provided. The system includes a satellite that covers an NTN cell, and a plurality of TN base stations (TN BSs) within a coverage of the satellite. The NTN cell serves a plurality of NTN user equipments (NTN UEs). The method includes dividing the plurality of NTN UEs into X NTN UE groups; partitioning a radio resource into M parts, where M≥X; dividing the plurality of TN BSs into M TN BS groups; deciding radio resource allocation regarding the plurality of NTN UEs, by allocating an i-th part of the radio resource to an i-th NTN UE group, where i=1, 2, . . . , X; and deciding radio resource allocation regarding the plurality of TN BSs, by allocating a sum of a j-th to an M-th parts of the radio resource to a j-th TN BS group, where j=1, 2, . . . , M.

IPC Classes  ?

  • H04W 72/121 - Wireless traffic scheduling for groups of terminals or users
  • H04B 7/185 - Space-based or airborne stations

39.

METHOD OF RADIO RESOURCE ALLOCATION FOR A TN-NTN NETWORK

      
Application Number 18361045
Status Pending
Filing Date 2023-07-28
First Publication Date 2024-02-08
Owner
  • MEDIATEK INC. (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Lee, Hao-Wei
  • Fu, I-Kang
  • Chen, Chun-Chia
  • Liao, Chen-I
  • Wei, Hung-Yu

Abstract

This disclosure provides a method, an apparatus, and a non-transitory computer-readable medium for radio resource allocation for a terrestrial network (TN) cell. In the method, the TN cell is determined to be outside a coverage of a first non-terrestrial network (NTN) cell. In response to the TN cell being outside the coverage of the first NTN cell, a radio resource is allocated to the TN cell based on a radio resource of the first NTN cell.

IPC Classes  ?

  • H04W 72/542 - Allocation or scheduling criteria for wireless resources based on quality criteria using measured or perceived quality
  • H04B 7/185 - Space-based or airborne stations

40.

METHOD AND APPARATUS FOR NON-INVASIVE IMAGE-OBSERVING DENSITY OF INTRA-EPIDERMAL NERVE FIBER OF HUMAN SKIN

      
Application Number 17815571
Status Pending
Filing Date 2022-07-28
First Publication Date 2024-02-01
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Sun, Chi-Kuang
  • Wu, Pei-Jhe
  • Tseng, Hsiao-Chieh

Abstract

The present invention relates to a method and apparatus for non-invasive image-observing the density of an intra-epidermal nerve fiber of human skin, in which the method includes: providing a nonlinear optical microscopy device for capturing an intra-epidermal nerve fiber structural image of an acquisition area of a to-be-tested human skin to observe continuous signals of intra-epidermal nerve fiber images, wherein the nonlinear optical microscopy device includes: a laser light source for emitting laser light with a pulsed laser, and an image processing member for processing image signals; focusing the laser light on the intra-epidermal nerve fiber to obtain nerve signals of the intra-epidermal nerve fiber that have a length of at least three points of the intra-epidermal nerve fiber, and constitute a plurality of nerve fibers; and calculating the total number of nerve fiber signals of the to-be-tested human skin, and dividing it by the total area of captured images to obtain the density of the to-be-tested human body; and evaluating and determining whether the human suffers from related neuropathy. such as peripheral neuropathy.

IPC Classes  ?

  • A61B 18/20 - Surgical instruments, devices or methods for transferring non-mechanical forms of energy to or from the body by applying electromagnetic radiation, e.g. microwaves using laser
  • A61N 5/06 - Radiation therapy using light

41.

DRIVE SYSTEM THERMAL TEMPERATURE RISE TEST AND COMPENSATION SYSTEM

      
Application Number 17933361
Status Pending
Filing Date 2022-09-19
First Publication Date 2024-01-25
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Jywe, Wen-Yuh
  • Hsieh, Tung-Hsien
  • Hsu, Chia-Ming
  • Chang, Yu-Wei
  • Huang, Sen-Yi
  • Chiu, Ching-Ying
  • Lu, Pin-Wei
  • Zeng, Jheng-Jhong

Abstract

A drive system thermal temperature rise test and compensation system. The system has an optical non-contact type sensing head mounted on a main shaft of a machine tool, and a sensing center is formed in the center of the sensing head. A platform driven by a transmission device of the machine tool is provided with plural ball lens devices, and a temperature sensor for transmitting temperature data externally is further provided on the transmission device. After the machine tool sequentially records an original point coordinate for each ball lens center by using the sensing head, the sensing head is cyclically and sequentially moved to the original point coordinate of each ball lens, so as to measure a displacement error between the sensing center and the ball lens center resulted from thermal shifts of the transmission device, as well as capable of measuring multiaxial errors and using various axial temperatures for compensation.

IPC Classes  ?

  • G01K 3/10 - Thermometers giving results other than momentary value of temperature giving differentiated values in respect of time, e.g. reacting only to a quick change of temperature
  • G01B 11/00 - Measuring arrangements characterised by the use of optical techniques

42.

Electrochemical Equipment and System thereof for Reduction of Carbon Dioxide

      
Application Number 18137120
Status Pending
Filing Date 2023-04-20
First Publication Date 2024-01-25
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Chen, Hao Ming
  • Chen, Tai-Lung

Abstract

An electrochemical equipment and system thereof for reduction of carbon dioxide is provided with cathode compartment, catholyte compartment, anode compartment, anolyte chamber, and isolation unit.

IPC Classes  ?

  • C25B 3/26 - Reduction of carbon dioxide
  • C25B 1/02 - Hydrogen or oxygen
  • C25B 1/23 - Carbon monoxide or syngas
  • C25B 3/03 - Acyclic or carbocyclic hydrocarbons
  • C25B 9/19 - Cells comprising dimensionally-stable non-movable electrodes; Assemblies of constructional parts thereof with diaphragms
  • C25B 1/26 - Chlorine; Compounds thereof
  • C25B 9/70 - Assemblies comprising two or more cells

43.

2-D MATERIAL SEMICONDUCTOR DEVICE

      
Application Number 18480787
Status Pending
Filing Date 2023-10-04
First Publication Date 2024-01-25
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Lin, Shih-Yen
  • Tsai, Po-Cheng
  • Zhang, Yu-Wei

Abstract

A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/8234 - MIS technology
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

44.

SEMICONDUCTOR DEVICE

      
Application Number 18474894
Status Pending
Filing Date 2023-09-26
First Publication Date 2024-01-18
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Tu, Chien-Te
  • Lin, Hsin-Cheng
  • Liu, Chee-Wee

Abstract

A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

IPC Classes  ?

  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/66 - Types of semiconductor device
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/761 - PN junctions

45.

ELECTRONIC DEVICE

      
Application Number 18475959
Status Pending
Filing Date 2023-09-27
First Publication Date 2024-01-18
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chen, Shih-Yuan
  • Li, Jiun-Yun
  • Xu, Rui-Fu
  • Chen, Chiung-Yu
  • Yeh, Ting-I
  • Wu, Yu-Jui
  • Chang, Yao-Chun

Abstract

An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and overlaps with the transistor. The ring resonator includes a conductive loop and an impedance matching element. The conductive loop includes a loop portion having two first parts and a second part and two feeding lines. Each of the first parts of the loop portion is between the second part of the loop portion and one of the feeding lines, and a tunnel barrier of the transistor is closer to the second part than to the feeding lines. The impedance matching element is closer to the feeding lines than to the second part.

IPC Classes  ?

  • H01L 23/64 - Impedance arrangements
  • H01L 29/66 - Types of semiconductor device
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

46.

METHOD FOR IDENTIFYING ANTI-CANCER AGENTS USING AN IN VITRO CELL CULTURE SYSTEM THAT MAINTAINS CANCER CELL STEMNESS

      
Application Number 18452952
Status Pending
Filing Date 2023-08-21
First Publication Date 2024-01-18
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Yang, Pan-Chyr
  • Chen, Huei-Wen
  • Chen, Wan-Jiun

Abstract

An in vitro co-culture system comprising cancer-associated fibroblasts (CAFs) and cancer cells for producing and maintaining cancer stem cells and uses thereof for identifying agents capable of reducing cancer cell stemness. Also disclosed herein are a paracrine network through which CAFs facilitate production and/or maintenance of cancer stem cells and the use of components of such a paracrine network for prognosis purposes and for identifying cancer patients who are likely to respond to certain treatment.

IPC Classes  ?

  • C12N 5/095 - Stem cells; Progenitor cells
  • C12N 5/09 - Tumour cells
  • G01N 33/50 - Chemical analysis of biological material, e.g. blood, urine; Testing involving biospecific ligand binding methods; Immunological testing
  • G01N 33/574 - Immunoassay; Biospecific binding assay; Materials therefor for cancer

47.

ARRAYED RADIO-FREQUENCY (RF) SYSTEM

      
Application Number 17932029
Status Pending
Filing Date 2022-09-14
First Publication Date 2024-01-18
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chou, Hsi-Tseng
  • Yen, Chih-Ta
  • An, Qian-Xin
  • Chen, Wei-Feng
  • Shih, Cheng-Liang

Abstract

An arrayed RF system includes an expandable mother circuit carrier and sub-modules implemented with RF packaged radiation structures. The sub-modules are embedded onto the mother circuit carrier through plug-in interfaces to form a replaceable and expandable co-structural structure. The mother circuit carrier receives and up-converts an input intermediate-frequency signal, thereby generating first high-frequency signals. The sub-modules are horizontally embedded on the mother circuit carrier, arranged into a one-dimensional or two-dimensional array, and electrically connected to the mother circuit carrier. The RF packaged radiation structures respectively receive first high-frequency signals, thereby emitting first RF signals. The RF packaged radiation structures receive second RF signals, thereby generating second high-frequency signals. The mother circuit carrier down-converts the second high-frequency signals, thereby generating an output intermediate-frequency signal.

IPC Classes  ?

  • H05K 1/02 - Printed circuits - Details
  • H01Q 1/12 - Supports; Mounting means
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H04B 1/40 - Circuits

48.

INTEGRATED ANTENNA DEVICE

      
Application Number 17965286
Status Pending
Filing Date 2022-10-13
First Publication Date 2024-01-18
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chou, Hsi-Tseng
  • Yen, Chih-Ta
  • An, Qian-Xin
  • Chen, Wei-Feng
  • Shih, Cheng-Liang

Abstract

An integrated antenna device comprises a curved-surface transmitting array and an array antenna. The curved-surface transmitting army has a plurality of focuses to homogenize its radiation gains. The array antenna is arranged between the curved-surface transmitting array and the plurality of focuses. According to the control of an active RF module of the array antenna, the array antenna emits the first-order beam and performs beam scanning. The curved-surface transmitting array is used to focus the first-order beam to produce a second-order beam with high gain. The generation of the beamforming feed excitation weight of the active RF module makes the integrated antenna device have a beam scanning mechanism. The array antenna can be formed by feeder antennas A DSP dynamic groups the feeder antennas to form subarrays, the subarrays can generate different first-order beams for multi-point communications. The first-order beams can be scanned in an interleaved fashion.

IPC Classes  ?

  • H01Q 21/20 - Arrays of individually energised antenna units similarly polarised and spaced apart the units being spaced along, or adjacent to, a curvilinear path
  • H01Q 3/34 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase by electrical means

49.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18352876
Status Pending
Filing Date 2023-07-14
First Publication Date 2024-01-18
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Wan, Hsien-Wen
  • Cheng, Yi-Ting
  • Hong, Ming-Hwei
  • Kwo, Juei-Nai
  • Yang, Bo-Yu
  • Hong, Yu-Jie

Abstract

A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.

IPC Classes  ?

  • H01L 29/51 - Insulating materials associated therewith
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/786 - Thin-film transistors

50.

CALIBRATION SYSTEM

      
Application Number 18217672
Status Pending
Filing Date 2023-07-03
First Publication Date 2024-01-11
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chien, Chen-Ho
  • Hsieh, Li-Hui
  • Jaw, Jen-Jer

Abstract

A calibration system is configured to detect a capacity difference of a tipping bucket rain gauge and determine an operational condition of the tipping bucket rain gauge. The calibration system includes a field calibration device, a detection communication box, and an application. The application is executed by an electronic device, which, upon receiving metering information and environmental information transmitted by the detection communication box, can calculate the capacity difference of the tipping bucket rain gauge. The calibration system allows an operator to directly perform testing of the capacity difference and the operational condition of the tipping bucket rain gauge, so as to provide users with follow-up measures or suggestions.

IPC Classes  ?

  • G01F 25/20 - Testing or calibration of apparatus for measuring volume, volume flow or liquid level or for metering by volume of apparatus for measuring liquid level
  • G01W 1/14 - Rainfall or precipitation gauges

51.

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

      
Application Number 18471859
Status Pending
Filing Date 2023-09-21
First Publication Date 2024-01-11
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Huang, Jian-Zhi
  • Hsu, Yun-Hsuan
  • Ni, I-Chih
  • Wu, Chih-I

Abstract

A semiconductor structure includes a semiconductor substrate, a gate structure, a source/drain structure, a contact, a dielectric layer, and a metal line. The gate structure is on the semiconductor substrate. The source/drain structure is adjacent to the gate structure. The contact lands on the source/drain structure. The dielectric layer spas the contact and the gate structure. The metal line extends through the dielectric layer to the contact. The metal line includes a liner over the contact, a magnetic layer over the liner, a graphene layer over the magnetic layer, and a filling metal over the graphene layer. The magnetic layer has a greater permeability coefficient than the filling metal.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 21/321 - After-treatment

52.

SYSTEM AND METHOD FOR CARDIOVASCULAR RISK PREDICTION AND COMPUTER READABLE MEDIUM THEREOF

      
Application Number 17804839
Status Pending
Filing Date 2022-05-31
First Publication Date 2024-01-04
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Wang, Tzung-Dau
  • Lee, Wen-Jeng
  • Huang, Yu-Cheng
  • Tseng, Chiu-Wang
  • Lee, Cheng-Kuang
  • Wang, Wei-Chung
  • Chou, Cheng-Ying

Abstract

Provided are a system and a method for cardiovascular risk prediction, where artificial intelligence is utilized to perform segmentation on non-contrast or contrast medical images to identify precise regions of the heart, pericardium, and aorta of a subject, such that the adipose tissue volume and calcium score can be derived from the medical images to assist in cardiovascular risk prediction. Also provided is a computer readable medium for storing a computer executable code to implement the method.

IPC Classes  ?

53.

INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 17848806
Status Pending
Filing Date 2022-06-24
First Publication Date 2023-12-28
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
  • National Taiwan Normal University (Taiwan, Province of China)
Inventor
  • Hsiang, Kuo-Yu
  • Liao, Chun-Yu
  • Liu, Jen-Ho
  • Lee, Min-Hung

Abstract

An integrated circuit device includes a substrate and a memory device. The memory device is over the substrate. The memory device includes a bottom electrode, a dielectric layer, an antiferroelectric layer, and a top electrode. The dielectric layer is over the bottom electrode. The antiferroelectric layer is over the dielectric layer. The top electrode is over the antiferroelectric layer.

IPC Classes  ?

  • H01L 27/11507 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with ferroelectric memory capacitors characterised by the memory core region

54.

METHOD FOR PREVENTING OR TREATING UROLOGICAL CHRONIC PELVIC PAIN SYNDROME

      
Application Number 17835634
Status Pending
Filing Date 2022-06-08
First Publication Date 2023-12-14
Owner
  • National Health Research Institutes (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
  • National Chung Hsing University (Taiwan, Province of China)
  • National Cheng Kung University (Taiwan, Province of China)
Inventor
  • Lien, Wei-Chih
  • Lin, Feng-Huei
  • Wang, Hui-Min
  • Ching, Tak Shing
  • Zhou, Xin-Ran
  • Liang, Ya-Jyun
  • Wang, Chia-Yih
  • Lu, Fu-I
  • Chang, Huei-Cih

Abstract

Provided is a method for preventing or treating urological chronic pelvic pain syndrome (UCPPS) in a subject that includes administering an effective amount of cerium oxide nanoparticles (CeNPs) to the subject. Also provided is a method for preventing or treating an UCPPS in a subject that includes administering to the subject a pharmaceutical composition comprising an effective amount of the CeNPs and a pharmaceutically acceptable carrier thereof.

IPC Classes  ?

55.

HOT CARRIER SOLAR CELL AND TANDEM SOLAR CELL

      
Application Number 17961465
Status Pending
Filing Date 2022-10-06
First Publication Date 2023-12-14
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Lin, Ching-Fuh
  • Chang, Chung-Han

Abstract

A hot carrier solar cell capable of absorbing sunlight with wavelengths greater than 1100 nm includes a light-absorbing layer in contact with a semiconductor layer, and a first and a second electrode in contact with the light-absorbing layer and the semiconductor layer, respectively. The hot carrier solar cell can be produced in a lower cost using a simple process. In addition, a tandem solar cell having the above-mentioned hot carrier solar cell is also disclosed to improve the efficiency of the tandem solar cell.

IPC Classes  ?

  • H01L 31/055 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means where light is absorbed and re-emitted at a different wavelength by the optical element directly associated or integrated with the PV cell, e.g. by using luminescent material, fluorescent concentrators or up-conversion arrangements
  • H01L 31/0224 - Electrodes

56.

ADJUSTABLE VOLTAGE REGULATOR CIRCUITRY

      
Application Number 17838289
Status Pending
Filing Date 2022-06-13
First Publication Date 2023-12-14
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Wu, Bing-Chen
  • Liu, Tsung-Te

Abstract

An adjustable voltage regulator circuit, including a voltage conversion circuit, a voltage conversion controller, and a clock generator, is provided. The voltage conversion circuit receives an input voltage to generate an output voltage. The voltage conversion controller detects the output voltage, compares the output voltage with a reference voltage value, and outputs an enable signal based on a comparison result to control the voltage conversion circuit to adjust the output voltage. The clock generator generates a first clock signal and a second clock signal to respectively drive the voltage conversion circuit and the voltage conversion controller. The voltage conversion controller adjusts the enable signal to gradually adjust the output voltage to a predetermined voltage range.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

57.

BOARD STRUCTURE HAVING ARTICULATED JOINTS AND SPLICE OBJECT HAVING THE SAME

      
Application Number 18209023
Status Pending
Filing Date 2023-06-13
First Publication Date 2023-12-14
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Fang, Chiao
  • Chan, Vivian Hsin-Yueh
  • Cheng, Lung-Pan

Abstract

A board structure having articulated joints and a splice object having articulated joints are provided. The board structure includes a first board and a second board. The first board has a first holding slot and a first articulated arm, and the second board has a second holding slot and a second articulated arm. The first articulated arm is L-shaped or T-shaped and is accommodated in the second holding slot. The second articulated arm is L-shaped or T-shaped and is accommodated in the first holding slot. An articulated seam is formed between the first board and the second board, and the first board and the second board are positioned at various angles relative to each other along the articulated seam. The splice object includes multiple ones of the first boards and second boards.

IPC Classes  ?

  • F16C 11/04 - Pivotal connections
  • F16M 11/38 - Undercarriages with or without wheels changeable in height or length of legs, also for transport only by folding

58.

SEMICONDUCTOR DEVICE WITH OXIDE-BASED SEMICONDUCTOR CHANNEL

      
Application Number 17829773
Status Pending
Filing Date 2022-06-01
First Publication Date 2023-12-07
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chiu, Jih-Chao
  • Li, Song-Ling
  • Liu, Chee-Wee

Abstract

A method includes forming a fin over a substrate, the fin comprising alternately stacking first oxide-based semiconductor layers and second oxide-based semiconductor layers, removing the second oxide-based semiconductor layers to form a plurality of spaces each between corresponding ones of the first oxide-based semiconductor layers, and depositing in sequence a gate dielectric layer and a gate metal into the plurality of spaces each between corresponding ones of the second oxide-based semiconductor layers.

IPC Classes  ?

  • H01L 29/786 - Thin-film transistors
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/465 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 29/66 - Types of semiconductor device

59.

SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF

      
Application Number 17834596
Status Pending
Filing Date 2022-06-07
First Publication Date 2023-12-07
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chung, Chia-Che
  • Tsen, Chia-Jung
  • Liu, Chee-Wee

Abstract

A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/47 - Organic layers, e.g. photoresist

60.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 17830266
Status Pending
Filing Date 2022-06-01
First Publication Date 2023-12-07
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Tu, Chien-Te
  • Liu, Chee-Wee

Abstract

A method includes forming a semiconductor structure on a substrate; performing a first etching process on the semiconductor structure to form a fin structure upwardly extending above the substrate; performing a second etching process to trim the fin structure to have a reverse-trapezoidal cross-sectional profile; forming source/drain regions on opposite regions of the fin structure; forming a gate structure between the source/drain regions.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/786 - Thin-film transistors
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3065 - Plasma etching; Reactive-ion etching

61.

MEMORY DEVICE AND FORMATION METHOD THEREOF

      
Application Number 17831187
Status Pending
Filing Date 2022-06-02
First Publication Date 2023-12-07
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Tsou, Ya-Jui
  • Chiu, Jih-Chao
  • Shih, Huan-Chi
  • Liu, Chee-Wee
  • Lin, Shao-Yu
  • Wang, Chih-Lin

Abstract

A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.

IPC Classes  ?

  • H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
  • H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
  • H01L 43/08 - Magnetic-field-controlled resistors
  • H01L 43/10 - Selection of materials
  • H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

62.

GATED METAL-INSULATOR-SEMICONDUCTOR (MIS) TUNNEL DIODE HAVING NEGATIVE TRANSCONDUCTANCE

      
Application Number 18361758
Status Pending
Filing Date 2023-07-28
First Publication Date 2023-11-30
Owner
  • Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Hwu, Jenn-Gwo
  • Liao, Chien-Shun

Abstract

Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

IPC Classes  ?

  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H01L 29/51 - Insulating materials associated therewith
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

63.

METHOD FOR TREATING AND/OR PREVENTING ATOPY AND ALLERGIC DISEASES BY USING BACTERIA OR COMPOSITIONS HAVING 7 ALPHA-DEHYDROXYLASE ACTIVITY, AND/OR BILE ACID RECEPTORS FXR AND/OR TGR5 AGONISTS

      
Application Number 18135394
Status Pending
Filing Date 2023-04-17
First Publication Date 2023-11-30
Owner
  • NATIONAL TAIWAN UNIVERSITY HOSPITAL (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor Huang, Miao-Tzu

Abstract

The present disclosure provides a method for treating and/or preventing atopy and allergic diseases by using bacteria or compositions having 7 alpha-dehydroxylase activity, and the bile acid receptors FxR and/or TGR5 agonists. Bacteria or compositions having 7 alpha-dehydroxylase activity, and the bile acid receptors FxR and/or TGR5 agonists of the present disclosure can induce immune-regulatory leukocytes, and alleviate the severity of allergic airway diseases.

IPC Classes  ?

  • A61K 35/742 - Spore-forming bacteria, e.g. Bacillus coagulans, Bacillus subtilis, clostridium or Lactobacillus sporogenes
  • A61K 38/17 - Peptides having more than 20 amino acids; Gastrins; Somatostatins; Melanotropins; Derivatives thereof from humans
  • A61P 37/08 - Antiallergic agents
  • A61P 11/00 - Drugs for disorders of the respiratory system

64.

GPU-accelerated data processing method for rapid noise-suppressed contrast enhancement

      
Application Number 17827816
Status Pending
Filing Date 2022-05-30
First Publication Date 2023-11-30
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Sun, Chi-Kuang
  • Borah, Bhaskar Jyoti

Abstract

The present disclosure relates to a data processing method, and more specifically, to a digital image processing method to enable a rapid noise-suppressed contrast enhancement in an optical linear or nonlinear microscopy imaging application. The disclosed method digitally mimics a hardware-based feedback-driven adaptive or controlled illumination technique by means of digitally resembling selective laser-on and laser-off states so as to selectively optimize the signal strength and hence the visibility of the weak-intensity morphologies while mostly preventing saturation of the brightest structures.

IPC Classes  ?

  • G06T 5/00 - Image enhancement or restoration
  • G06T 5/20 - Image enhancement or restoration by the use of local operators

65.

GATE-ALL-AROUND DEVICE

      
Application Number 18362778
Status Pending
Filing Date 2023-07-31
First Publication Date 2023-11-23
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Tsai, Chung-En
  • Chung, Chia-Che
  • Liu, Chee-Wee
  • Lu, Fang-Liang
  • Huang, Yu-Shiang
  • Yeh, Hung-Yu
  • Tu, Chien-Te
  • Liu, Yi-Chun

Abstract

A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/786 - Thin-film transistors

66.

SEAT APPARATUS HAVING SIMULATED FORCE FEEDBACK AND METHOD FOR SIMULATING FORCE SENSATION OF DRIVING

      
Application Number 18314148
Status Pending
Filing Date 2023-05-09
First Publication Date 2023-11-23
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chen, Shiang-Fong
  • Lin, Bo-Ting
  • Pan, Chi
  • Yu, Tzu-Yuan

Abstract

A seat apparatus having a simulated force feedback and a method for simulating a force sensation of driving are provided. The seat apparatus includes a seating unit, a rotary platform, and a realistic seat pallet. The seating unit includes a seat pan. The rotary platform includes a chassis and a rotary motive module. The seat pan is disposed on the chassis along a rotation axis in an inclinable manner. The rotary motive module can control the seat pan to have a forward or rearward inclined angle. The realistic seat pallet is disposed on the seat pan, and includes a movable contact cushion and a pallet motive module. Through the pallet motive module, the movable contact cushion is slidable relative to the seat pan. The pallet motive module can control the movable contact cushion to have left and right displacements, front and rear displacements, angular displacements, or yaw rotations.

IPC Classes  ?

  • A47C 7/14 - Seat parts elastically mounted
  • A47C 7/56 - Parts or details of tipping-up chairs, e.g. of theatre chairs
  • A47C 1/023 - Reclining or easy chairs having independently-adjustable supporting parts the parts being horizontally-adjustable seats
  • G09B 9/04 - Simulators for teaching or training purposes for teaching control of vehicles or other craft for teaching control of land vehicles
  • A63G 31/16 - Amusement arrangements creating illusions of travel
  • A63F 13/803 - Driving vehicles or craft, e.g. cars, airplanes, ships, robots or tanks

67.

SEMICONDUCTOR DEVICE HAVING DOPED WORK FUNCTION METAL LAYER

      
Application Number 18360416
Status Pending
Filing Date 2023-07-27
First Publication Date 2023-11-16
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Huang, Chih-Hsiung
  • Tsai, Chung-En
  • Liu, Chee-Wee
  • Kuok, Kun-Wa
  • Hsiao, Yi-Hsiu

Abstract

A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

IPC Classes  ?

  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 29/40 - Electrodes
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/66 - Types of semiconductor device

68.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18226166
Status Pending
Filing Date 2023-07-25
First Publication Date 2023-11-16
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Lu, Fang-Liang
  • Wong, I-Hsieh
  • Lin, Shih-Ya
  • Liu, Cheewee
  • Pan, Samuel C.

Abstract

A semiconductor device includes a first layer that includes a first semiconductor material disposed on a semiconductor substrate, and a second layer of a second semiconductor material disposed on the first layer. The semiconductor substrate includes Si. The first semiconductor material and the second semiconductor material are different. The second semiconductor material is formed of an alloy including a first element and Sn. A surface region of an end portion of the second layer at both ends of the second layer has a higher concentration of Sn than an internal region of the end portion of the second layer. The surface region surrounds the internal region.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

69.

NANOWIRE STACK GAA DEVICE WITH SELECTABLE NUMBERS OF CHANNEL STRIPS

      
Application Number 18359745
Status Pending
Filing Date 2023-07-26
First Publication Date 2023-11-16
Owner
  • Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Tsou, Ya-Jui
  • Luo, Zong-You
  • Huang, Wen Hung
  • Yan, Jhih-Yang
  • Liu, Chee-Wee

Abstract

The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.

IPC Classes  ?

  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

70.

FERROELECTRIC MFM INDUCTOR AND RELATED CIRCUITS

      
Application Number 18343687
Status Pending
Filing Date 2023-06-28
First Publication Date 2023-11-09
Owner
  • Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Chen, Miin-Jang
  • Cheng, Po-Hsien
  • Yin, Yu-Tung

Abstract

Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H03H 7/06 - Frequency selective two-port networks including resistors
  • H03H 7/01 - Frequency selective two-port networks
  • H01L 29/66 - Types of semiconductor device

71.

MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18352872
Status Pending
Filing Date 2023-07-14
First Publication Date 2023-11-09
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Luo, Zong-You
  • Tsou, Ya-Jui
  • Liu, Chee-Wee
  • Lin, Shao-Yu
  • Chung, Liang-Chor
  • Wang, Chih-Lin

Abstract

A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

IPC Classes  ?

  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/01 - Manufacture or treatment
  • H10N 50/10 - Magnetoresistive devices
  • H10N 50/80 - Constructional details
  • H10N 50/85 - Magnetic active materials

72.

METHOD FOR MANUFACTURING MEMORY DEVICE

      
Application Number 18353569
Status Pending
Filing Date 2023-07-17
First Publication Date 2023-11-09
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Tsou, Ya-Jui
  • Luo, Zong-You
  • Liu, Chee-Wee
  • Lin, Shao-Yu
  • Chung, Liang-Chor
  • Wang, Chih-Lin

Abstract

A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

IPC Classes  ?

  • H10N 50/80 - Constructional details
  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/01 - Manufacture or treatment

73.

MEMORY DEVICE AND METHOD FOR FORMING THE SAME

      
Application Number 17739871
Status Pending
Filing Date 2022-05-09
First Publication Date 2023-11-09
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
  • National Taiwan Normal University (Taiwan, Province of China)
Inventor
  • Chen, Kuan-Ting
  • Liao, Chun-Yu
  • Hsiang, Kuo-Yu
  • Chung, Yun-Fang
  • Lee, Min-Hung
  • Chang, Shu-Tong

Abstract

A method includes forming a semiconductor layer over a substrate; depositing a first ferroelectric layer over a channel region of the semiconductor layer; depositing a first dielectric layer over the first ferroelectric layer; depositing a second ferroelectric layer over the first dielectric layer; depositing a gate metal layer over the second ferroelectric layer; patterning the gate metal layer, the second ferroelectric layer, the first dielectric layer, and the first ferroelectric layer to form a gate structure; and forming source/drain regions in the semiconductor layer and on opposite sides of the gate structure.

IPC Classes  ?

  • H01L 27/11597 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS] characterised by three-dimensional arrangements, e.g. cells on different height levels
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/786 - Thin-film transistors
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

74.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 17727737
Status Pending
Filing Date 2022-04-23
First Publication Date 2023-10-26
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Hwu, Jenn-Gwo
  • Chen, Jen-Hao
  • Chen, Kung-Chu

Abstract

A semiconductor device includes a substrate, a sensing device, and a transistor. The sensing device includes a dielectric layer, a sensing pad, a first sensing electrode, and a second sensing electrode. The dielectric layer is over the substrate. The sensing pad is over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode are over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode surround the sensing pad, and a distance between the first sensing electrode and the second sensing electrode is greater than a distance between the sensing pad and the first sensing electrode. The transistor is over the substrate. A gate of the transistor is connected to the sensing pad.

IPC Classes  ?

  • H01L 29/68 - Types of semiconductor device controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
  • H01L 29/66 - Types of semiconductor device

75.

WRITE ASSIST CIRCUIT FOR MEMORY DEVICE

      
Application Number 17720154
Status Pending
Filing Date 2022-04-13
First Publication Date 2023-10-19
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chung, Chia-Che
  • Lin, Hsin-Cheng
  • Liu, Chee-Wee

Abstract

A device is provided. The device includes a memory cell and a first write assist circuit. The memory cell operates with a first supply voltage and a second supply voltage different from the first supply voltage. The first write assist circuit includes a first write assist switch and a second write assist switch that are coupled to the memory cell through a first data line. In a write operation of a data, having a first logic value, to the memory cell, the first write assist switch transmits the first supply voltage to the first data line in response to a first control signal, received at a control terminal of the first write assist switch and having a voltage level of the second supply voltage, when the second write assist switch is configured to be turned off.

IPC Classes  ?

76.

ANTIMICROBIAL COMPOSITIONS, PHARMACEUTICAL COMPOSITIONS AND USE THEREOF

      
Application Number 18297439
Status Pending
Filing Date 2023-04-07
First Publication Date 2023-10-19
Owner
  • National Taiwan University (Taiwan, Province of China)
  • National Yang Ming Chiao Tung University (Taiwan, Province of China)
Inventor
  • Chiu, Hao-Chieh
  • Shiau, Chung-Wai

Abstract

Disclosed herein are an antimicrobial composition and related methods. With the synergistic effect of amide compounds and fatty acids in the composition, not only the antibacterial effect against drug-resistant bacteria can be achieved with a smaller amount of amide compounds, but the persister cells and biofilms of microorganisms can be effectively and quickly eradicated.

IPC Classes  ?

  • A61K 31/36 - Compounds containing methylenedioxyphenyl groups, e.g. sesamin
  • A61K 31/17 - Amides, e.g. hydroxamic acids having the group N—C(O)—N or N—C(S)—N, e.g. urea, thiourea, carmustine
  • A61K 31/4412 - Non-condensed pyridines; Hydrogenated derivatives thereof having oxo groups directly attached to the heterocyclic ring
  • A61K 31/201 - Carboxylic acids, e.g. valproic acid having a carboxyl group bound to an acyclic chain of seven or more carbon atoms, e.g. stearic, palmitic or arachidic acid having one or two double bonds, e.g. oleic or linoleic acid
  • A61K 31/202 - Carboxylic acids, e.g. valproic acid having a carboxyl group bound to an acyclic chain of seven or more carbon atoms, e.g. stearic, palmitic or arachidic acid having three or more double bonds, e.g. linolenic acid
  • A61P 31/04 - Antibacterial agents

77.

INTEGRATED NUCLEIC ACID LOOP-MEDIATED ISOTHERMAL AMPLIFICATION AND MOBILE DEVICE SYSTEM

      
Application Number 18046575
Status Pending
Filing Date 2022-10-14
First Publication Date 2023-10-05
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Chen, Chien-Fu
  • Wu, Shou-Cheng
  • Chen, Shi-Jia
  • Chien, Yuh-Shiuan
  • Sheng, Wang-Huei

Abstract

An integrated nucleic acid loop-mediated isothermal amplification and mobile device system is provided and includes a main body and a power supply, where the 5 main body at least has a delivery unit, a heating unit and a control unit, the control unit is electrically connected to the delivery unit and the heating unit, and the power supply is electrically connected to the main body. A method for operating the integrated nucleic acid loop-mediated isothermal amplification and mobile device system is also provided.

IPC Classes  ?

  • C12Q 1/6844 - Nucleic acid amplification reactions
  • B01L 7/00 - Heating or cooling apparatus; Heat insulating devices

78.

ORGANIC ELECTROLUMINESCENT DEVICES WITH IMPROVED OPTICAL OUT-COUPLING EFFICIENCIES

      
Application Number 18021856
Status Pending
Filing Date 2020-09-21
First Publication Date 2023-10-05
Owner
  • Applied Materials, Inc. (USA)
  • National Taiwan Universtiy (Taiwan, Province of China)
Inventor
  • Chen, Chung-Chia
  • Lin, Wan-Yu
  • Bang, Hyunsung
  • Xu, Lisong
  • Yu, Gang
  • Kwak, Byung-Sung
  • Visser, Robert Jan
  • Wu, Chung-Chih
  • Lin, Hoang Yan
  • Su, Guo-Dong
  • Lee, Wei-Kai
  • Chen, Yi-Jiun
  • Hsu, Ting-Sheng
  • Liao, Po-Hsiang
  • Lin, Wei-Cheng

Abstract

Embodiments of the present disclosure generally relate to electroluminescent devices, such as organic light-emitting diodes, and displays including electroluminescent devices. In an embodiment is provided an electroluminescent device that includes a pixel defining layer, an organic emitting unit disposed over at least a portion of the pixel defining layer, and a filler layer disposed over at least a portion of the organic emitting unit, wherein a refractive index of the pixel defining layer is lower than a refractive index of the filler layer, and wherein the refractive index of the pixel defining layer is lower than a refractive index of one or more layers of the organic emitting unit. In another embodiment is provided a display device that includes a substrate, a thin film transistor formed on the substrate, an interconnection electrically coupled to the thin film transistor, and an electroluminescent device electrically coupled to the interconnection.

IPC Classes  ?

  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/80 - Constructional details
  • H10K 59/131 - Interconnections, e.g. wiring lines or terminals

79.

METHOD OF PREPARING TRITERPENOID COMPOUND

      
Application Number 18194171
Status Pending
Filing Date 2023-03-31
First Publication Date 2023-10-05
Owner National Taiwan University (Taiwan, Province of China)
Inventor Liang, Pi-Hui

Abstract

A method of preparing a triterpenoid compound of formula (I): A method of preparing a triterpenoid compound of formula (I): A method of preparing a triterpenoid compound of formula (I): including a step of converting a compound of formula (II) into the compound of formula (I), A method of preparing a triterpenoid compound of formula (I): including a step of converting a compound of formula (II) into the compound of formula (I), A method of preparing a triterpenoid compound of formula (I): including a step of converting a compound of formula (II) into the compound of formula (I), wherein R1 and R2 independently represent hydrogen or a protecting group selected from the group consisting of C1-C8 alkyl, allyl, C2-C8 alkenyl, C2-C8 alkynyl, (C6-C12)aryl(C1-C8)alkyl, tri(C1-C8)alkylsilyl, di(C1-C8)alkyl(C6-C12)arylsilyl, di(C6-C12)aryl(C1-C8)alkylsilyl ,tri(C6-C12)arylsilyl, —C(O)R7, and —C(O)OR8, and each of which is substituted with from 0 to 4 substituents independently selected from the group consisting of hydroxy, cyano, halo, halo(C1-C6)alkyl, halo(C1-C6)alkyloxy, (C1-C6)alkylthio, C1-C6 alkyl, C2-C6 alkenyl, C2-C6 alkynyl, C3-C7 cycloalkyl and C1-C6 alkoxy, wherein R7 and R8 are independently C1-C8 alkyl or C6-C12 aryl.

IPC Classes  ?

  • C07C 51/16 - Preparation of carboxylic acids or their salts, halides, or anhydrides by oxidation

80.

CONJUGATE FOR TARGETING THERAPY

      
Application Number 17658082
Status Pending
Filing Date 2022-04-05
First Publication Date 2023-10-05
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Liang, Pi-Hui
  • Chang, Chun-Kai
  • Chiu, Pei-Fang

Abstract

The present disclosure provides a novel conjugate or a pharmaceutically acceptable salt thereof, wherein the conjugate has an active pharmaceutical moiety or a prodrug thereof, a targeting module and a linker therebetween. The conjugate or a pharmaceutically acceptable salt thereof is useful for treating a disease, recurrence or progression in a subject or increasing the likelihood of survival over a relevant period in a subject diagnosed with a disease.

IPC Classes  ?

  • A61K 47/54 - Medicinal preparations characterised by the non-active ingredients used, e.g. carriers or inert additives; Targeting or modifying agents chemically bound to the active ingredient the non-active ingredient being chemically bound to the active ingredient, e.g. polymer-drug conjugates the non-active ingredient being a modifying agent the modifying agent being an organic compound
  • A61P 35/00 - Antineoplastic agents

81.

SEMICONDUCTOR DEVICE WITH GATE DIELECTRIC FORMED USING SELECTIVE DEPOSITION

      
Application Number 18324636
Status Pending
Filing Date 2023-05-26
First Publication Date 2023-10-05
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
  • NATIONAL TAIWAN NORMAL UNIVERSITY (Taiwan, Province of China)
Inventor
  • Lee, Tung-Ying
  • Chen, Tse-An
  • Wang, Tzu-Chung
  • Chen, Miin-Jang
  • Yin, Yu-Tung
  • Yang, Meng-Chien

Abstract

A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/786 - Thin-film transistors
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

82.

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

      
Application Number 17698696
Status Pending
Filing Date 2022-03-18
First Publication Date 2023-10-05
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Jhan, Shun-Siang
  • Chou, Ang-Sheng
  • Ni, I-Chih
  • Wu, Chih-I

Abstract

A method includes forming a 2-D semiconductor material layer over a substrate; forming source/drain contacts over source/drain regions of the 2-D semiconductor material layer; and forming a gate structure over a channel region of the 2-D semiconductor material layer. Forming the source/drain contacts includes performing a first deposition process to deposit a first metal layer over the 2-D semiconductor material layer; and after the first deposition process is completed, performing a second deposition process to deposit a second metal layer over the first metal layer, in which the second metal layer has a higher melting point than the first metal layer.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 29/786 - Thin-film transistors
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 21/8234 - MIS technology
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

83.

PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME

      
Application Number 17710815
Status Pending
Filing Date 2022-03-31
First Publication Date 2023-10-05
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chang, Tzu-Hsuan
  • Chen, Chien-Liang
  • Lin, Rong-Teng

Abstract

A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a two-dimensional (2D) material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.

IPC Classes  ?

  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

84.

METHOD OF MANUFACTURING SILICON NANO-POWDERS AND MANUFACTURING EQUIPMENT IMPLEMENTING SUCH METHOD

      
Application Number 18181997
Status Pending
Filing Date 2023-03-10
First Publication Date 2023-09-28
Owner NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor Lan, Chung-Wen

Abstract

A method of manufacturing silicon nano-powders and a manufacturing equipment implementing such method. The method according to the invention utilizes a plurality of aluminum powders to react with a silicon tetrahalide into a plurality of silicon nano-powders and an aluminum trihalide to obtain the silicon nano-powders.

IPC Classes  ?

  • C01B 21/068 - Binary compounds of nitrogen with metals, with silicon, or with boron with silicon
  • B82Y 30/00 - Nanotechnology for materials or surface science, e.g. nanocomposites
  • C01B 21/072 - Binary compounds of nitrogen with metals, with silicon, or with boron with aluminium
  • B82Y 40/00 - Manufacture or treatment of nanostructures

85.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

      
Application Number 17871451
Status Pending
Filing Date 2022-07-22
First Publication Date 2023-09-28
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Kang, Wei-Cheng
  • Chang, Tzu-Hsuan
  • Weng, Wei-Yang
  • Cheng, Yu-Tzu
  • Hsu, Huang-Chun
  • Liao, Yu-Jung

Abstract

A semiconductor device having a standard cell comprises a first bottom transistor, a first top transistor, a second bottom transistor, a second top transistor, and a first bottom-transistor-level metal line. The first bottom transistor is in a first row. The first top transistor is disposed above the first bottom transistor in the first row. The first bottom transistor and the first top transistor share a first gate structure. The second bottom transistor is in a second row next to the first row. The second top transistor is disposed above the second bottom transistor in the second row. The second bottom transistor and the second top transistor share a second gate structure. The first bottom-transistor-level metal line extends laterally from a first source/drain region of the first bottom transistor to a source/drain region of the second bottom transistor.

IPC Classes  ?

86.

METHOD OF GENERATING RANDOMNESS BY PUBLIC PARTICIPATION

      
Application Number 18099024
Status Pending
Filing Date 2023-01-19
First Publication Date 2023-09-21
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Lee, Hsun
  • Hsu, Yuming
  • Wang, Jing-Jie
  • Yang, Hao Cheng
  • Chen, Yu-Heng
  • Hu, Yih-Chun
  • Hsiao, Hsu-Chun

Abstract

A method of generating randomness by public participation may comprise: communicating with the commodity devices to execute a protocol comprising a setup phase, a contribution phase and a result-generation phase, wherein: in the setup phase, parameters are initialized, a verifiable delay function is setup, and the parameters are published; the contribution phase is divided into at least one first stage, published parameters are provided, random values are received, and a Merkle tree root and Merkle tree audit paths are published in each of the first stage; and the result-generation phase is divided into at least one second stage of the same number as that of the first stage, each second stage is dedicated to one of the first stage ahead of the second stage for a period, and in each second stage, computation is performed to generate a result of randomness which is published.

IPC Classes  ?

  • H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems

87.

PTGR2 inhibitors and their use

      
Application Number 17688369
Grant Number 11851435
Status In Force
Filing Date 2022-03-07
First Publication Date 2023-09-07
Grant Date 2023-12-26
Owner
  • National Health Research Institutes (Taiwan, Province of China)
  • National Taiwan University (Taiwan, Province of China)
Inventor
  • Tsou, Lun Kelvin
  • Hung, Ming-Shiu
  • Chen, Chieh Wen
  • Hsieh, Meng-Lun
  • Chang, Yi-Cheng
  • Chuang, Lee Ming

Abstract

Disclosed are compounds of formula (I) as follows: 1, W, and Het is defined herein. Also provides are a method of inhibiting prostaglandin reductase 2 (“PTGR2”) using such a compound and a pharmaceutical composition containing same.

IPC Classes  ?

  • C07D 487/04 - Ortho-condensed systems
  • C07D 239/56 - One oxygen atom and one sulfur atom
  • C07D 417/12 - Heterocyclic compounds containing two or more hetero rings, at least one ring having nitrogen and sulfur atoms as the only ring hetero atoms, not provided for by group containing two hetero rings linked by a chain containing hetero atoms as chain links

88.

Antibacterial chemical compound, its manufacturing method and its use thereof

      
Application Number 17686949
Grant Number 11925650
Status In Force
Filing Date 2022-03-04
First Publication Date 2023-09-07
Grant Date 2024-03-12
Owner
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
  • NATIONAL YANG MING CHIAO TUNG UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chiu, Hao-Chieh
  • Shiau, Chung-Wai

Abstract

The present invention provides an antibacterial chemical compound, its manufacturing method and its use thereof which acts as antibacterial agents being useful for treating a disease or condition characterized by infectious disease, such as gastroenteritis and invasive non-typhoidal Salmonellosis, and also providing a new therapeutic option for patients infected by the bacteria with the resistance to antibiotics.

IPC Classes  ?

  • A61K 31/5513 - 1,4-Benzodiazepines, e.g. diazepam
  • A61K 31/165 - Amides, e.g. hydroxamic acids having aromatic rings, e.g. colchicine, atenolol, progabide
  • A61K 31/431 - Compounds containing 4-thia-1-azabicyclo [3.2.0] heptane ring systems, i.e. compounds containing a ring system of the formula , e.g. penicillins, penems containing further heterocyclic ring systems, e.g. ticarcillin, azlocillin, oxacillin
  • A61K 31/496 - Non-condensed piperazines containing further heterocyclic rings, e.g. rifampin, thiothixene
  • A61K 31/5383 - 1,4-Oxazines, e.g. morpholine ortho- or peri-condensed with heterocyclic ring systems
  • A61K 31/65 - Tetracyclines
  • A61K 31/7036 - Compounds having saccharide radicals attached to non-saccharide compounds by glycosidic linkages attached to a carbocyclic compound, e.g. phloridzin having at least one amino group directly attached to the carbocyclic ring, e.g. streptomycin, gentamycin, amikacin, validamycin, fortimicins
  • A61P 31/04 - Antibacterial agents
  • C07D 495/04 - Ortho-condensed systems

89.

MEMORY DEVICE AND METHOD FOR FORMING THE SAME

      
Application Number 17681545
Status Pending
Filing Date 2022-02-25
First Publication Date 2023-08-31
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Li, Chia-Shuo
  • Wu, Yu-Tien
  • Chen, Bo-You
  • Ni, I-Chih
  • Wu, Chih-I

Abstract

A method includes forming a transistor over a substrate; and forming a resistive element over the transistor, in which forming the resistive element includes forming a bottom electrode electrically connected to a source/drain region of the transistor; forming a resistive switching layer over the bottom electrode, in which the resistive switching layer is made of metal halide; and forming a top electrode over the resistive switching layer.

IPC Classes  ?

  • H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
  • H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier

90.

INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 17678094
Status Pending
Filing Date 2022-02-23
First Publication Date 2023-08-24
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chiu, Jih-Chao
  • Liu, Chee-Wee

Abstract

A method for fabricating an integrated circuit device is provided. The method includes forming a field effect transistor (FET) on a semiconductor substrate; depositing a first dielectric layer over the FET; depositing a first metal-containing dielectric layer over the first dielectric layer; and forming a first thin film transistor (TFT) over the first metal-containing dielectric layer.

IPC Classes  ?

  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/786 - Thin-film transistors
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 29/66 - Types of semiconductor device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

91.

Stacked semiconductor device with nanostructure channels and manufacturing method thereof

      
Application Number 17673890
Grant Number 11955384
Status In Force
Filing Date 2022-02-17
First Publication Date 2023-08-17
Grant Date 2024-04-09
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Tu, Chien-Te
  • Lin, Hsin-Cheng
  • Liu, Chee-Wee

Abstract

A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.

IPC Classes  ?

  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 21/761 - PN junctions
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

92.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

      
Application Number 18135650
Status Pending
Filing Date 2023-04-17
First Publication Date 2023-08-10
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Lan, Huang-Siang
  • Liu, Cheewee
  • Liu, Chi-Wen
  • Huang, Shih-Hsien
  • Wong, I-Hsieh
  • Yeh, Hung-Yu
  • Tsai, Chung-En

Abstract

A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/66 - Types of semiconductor device

93.

System and Method for Continuous Cell Production

      
Application Number 18107502
Status Pending
Filing Date 2023-02-09
First Publication Date 2023-08-10
Owner National Taiwan University (Taiwan, Province of China)
Inventor
  • Young, Tai-Horng
  • Yen, Chia-Hsiang
  • Wu, Ying-Syuan
  • Shih, Chiao-Chi

Abstract

The application provides a system for continuous cell production, comprising: a culture container; and a polymer blended layer arranged on the inner surface of the culture container; wherein, the polymer blended layer is a pH-responsive polymer blended with nylon. Additionally, a method for continuous cell production using the system of the present application is provided.

IPC Classes  ?

  • C12M 1/12 - Apparatus for enzymology or microbiology with sterilisation, filtration, or dialysis means
  • C12N 5/077 - Mesenchymal cells, e.g. bone cells, cartilage cells, marrow stromal cells, fat cells or muscle cells
  • C12N 5/0775 - Mesenchymal stem cells; Adipose-tissue derived stem cells
  • C12N 5/071 - Vertebrate cells or tissues, e.g. human cells or tissues

94.

MEMORY STRUCTURE AND FORMATION METHOD THEREOF

      
Application Number 17668514
Status Pending
Filing Date 2022-02-10
First Publication Date 2023-08-10
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Chen, Wei-Jen
  • Tsou, Ya-Jui
  • Liu, Chee-Wee
  • Lin, Shao-Yu
  • Wang, Chih-Lin

Abstract

A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.

IPC Classes  ?

  • H01L 43/04 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details of Hall-effect devices
  • H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
  • H01L 43/06 - Hall-effect devices
  • H01L 43/14 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof for Hall-effect devices

95.

Metal-insulator-semiconductor tunnel diode memory

      
Application Number 17582674
Grant Number 11855099
Status In Force
Filing Date 2022-01-24
First Publication Date 2023-07-27
Grant Date 2023-12-26
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Hwu, Jenn-Gwo
  • Hsu, Ting-Hao

Abstract

A method includes forming a first dielectric layer over the substrate and covering first, second, third, fourth, fifth and sixth protrusion regions; forming first, second, and third gate conductors over the first, fourth, and fifth protrusion regions, respectively; performing a first implantation process to form a second source region and a second drain region in the fourth protrusion region; performing a second implantation process to form a first source region and a first drain region in the first protrusion region, and to form a third source region and a third drain region in the fifth protrusion region; forming a metal layer over the third protrusion region; patterning the metal layer to form an inner circular electrode and an outer ring electrode encircling the inner circular electrode; forming a word line; and forming a bit line.

IPC Classes  ?

  • H01L 29/88 - Tunnel-effect diodes
  • H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
  • G11C 11/38 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements using tunnel diodes
  • H01L 27/102 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
  • H01L 29/66 - Types of semiconductor device
  • H10B 99/00 - Subject matter not provided for in other groups of this subclass

96.

HUMANIZED ACE2-FC FUSION PROTEIN FOR TREATMENT AND PREVENTION OF SARS-COV-2 INFECTION

      
Application Number 18001947
Status Pending
Filing Date 2021-06-15
First Publication Date 2023-07-27
Owner
  • ACADEMIA SINICA (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Yang, Pan-Chyr
  • Chang, Sui-Yuan
  • Huang, Kuo-Yen

Abstract

Disclosed herein are ACE2-Fc fusion polypeptides that contain at least one binding site for a spike protein of a coronavirus and methods of using such for therapeutic and/or diagnostic purposes. Also provided herein are methods for producing such fusion polypeptides.

IPC Classes  ?

  • C07K 14/705 - Receptors; Cell surface antigens; Cell surface determinants
  • A61K 47/64 - Drug-peptide, drug-protein or drug-polyamino acid conjugates, i.e. the modifying agent being a peptide, protein or polyamino acid which is covalently bonded or complexed to a therapeutically active agent
  • A61P 31/14 - Antivirals for RNA viruses
  • C07K 14/55 - IL-2
  • A61K 38/20 - Interleukins
  • A61K 38/17 - Peptides having more than 20 amino acids; Gastrins; Somatostatins; Melanotropins; Derivatives thereof from humans
  • A61K 45/06 - Mixtures of active ingredients without chemical characterisation, e.g. antiphlogistics and cardiaca

97.

SYSTEM FOR QUANTITATIVE DIFFERENTIAL PHASE CONTRAST MICROSCOPY WITH ISOTROPIC TRANSFER FUNCTION

      
Application Number 18121979
Status Pending
Filing Date 2023-03-15
First Publication Date 2023-07-27
Owner
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
  • YONGLIN HEALTHCARE FOUNDATION (Taiwan, Province of China)
Inventor
  • Luo, Yuan
  • Chuang, Yu-Hsuan
  • Lin, Yu-Zi

Abstract

A system for quantitative differential phase contrast microscopy with isotropic transfer function utilizes a modulation mechanism to create a detection light field having a radial or other axial orientation of optical intensity gradient or other distribution. A condenser generates an off-axis light field to project onto an object under examination, thereby generating an object light field, which is then guided to an image capturing device through an objective lens for capturing images. A differential phase contrast algorithm is applied to the images for obtaining a phase, thereby a depth information corresponding to the phase can be obtained to reconstruct the surface profile of the object.

IPC Classes  ?

  • G02B 21/14 - Condensers affording illumination for phase-contrast observation
  • G02B 21/00 - Microscopes

98.

NEEDLE FREE DELIVERY SYSTEM AND OPERATION METHOD THEREOF

      
Application Number 17661564
Status Pending
Filing Date 2022-05-01
First Publication Date 2023-07-27
Owner
  • National Taiwan University of Science and Technology (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
  • National Defense Medical Center (Taiwan, Province of China)
Inventor
  • Liao, Ai-Ho
  • Wang, Chih-Hung
  • Liu, Hao-Li

Abstract

The present disclosure provides a needle free delivery system, which includes a handheld device and a signal switching device. The signal switching device is electrically connected to the handheld device, and the handheld device includes an ultrasonic probe. The signal switching device provides a burst wave capable of generating a resonant carrier wave through piezoelectric material to the handheld device, so that an ultrasonic wave of the handheld device can perform a needleless delivery on a carrier.

IPC Classes  ?

  • A61B 8/00 - Diagnosis using ultrasonic, sonic or infrasonic waves
  • H04R 17/10 - Resonant transducers, i.e. adapted to produce maximum output at a predetermined frequency

99.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 17736819
Status Pending
Filing Date 2022-05-04
First Publication Date 2023-07-27
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Wang, Chun-Yuan
  • Chen, Miin-Jang

Abstract

A method for fabricating a semiconductor device is provided. The method includes depositing a gate dielectric layer over a semiconductor substrate; depositing a work function layer over the gate dielectric layer by an atomic layer deposition (ALD) process, wherein the work function layer comprises a metal element and a nonmetal element, and the ALD process comprises a plurality of cycles. Each of the cycles comprises: introducing a precursor gas comprising the metal element to a chamber to form a precursor surface layer on the semiconductor substrate in the chamber; purging a remaining portion of the precursor gas away from the chamber; performing a reactive-gas plasma treatment using a reactive-gas plasma comprising the nonmetal element to convert the precursor surface layer into a monolayer of the work function layer; purging a remaining portion of the reactive-gas plasma away from the chamber, and performing an inert-gas plasma treatment in the chamber.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/49 - Metal-insulator semiconductor electrodes

100.

INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 17580536
Status Pending
Filing Date 2022-01-20
First Publication Date 2023-07-20
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • NATIONAL TAIWAN UNIVERSITY (Taiwan, Province of China)
Inventor
  • Hwu, Jenn-Gwo
  • Lin, Jian-Yu

Abstract

An integrated circuit device includes a semiconductor structure, a tunneling layer, a top electrode, a passivation layer, and a conductive feature. The semiconductor structure has a base portion and a protruding portion over a top surface of the base portion. The tunneling layer is over a top surface of the protruding portion of the semiconductor structure. The top electrode is over the tunneling layer. The passivation layer is over a sidewall of the protruding portion of the semiconductor structure. The conductive feature is directly below the protruding portion of the semiconductor structure.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/88 - Tunnel-effect diodes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
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