A method of managing data storage using a management device that includes determining respective status information for a plurality of storage devices, and calculating, based on the status information, a respective cost for each of the plurality of storage devices using a cost function that includes one or more parameters including at least one of: a program/erase (P/E) parameter, a block error state parameter, a block error level parameter, and a workload parameter. The method further includes selecting a destination storage device of the plurality of storage devices based on at least some of the calculated costs, and writing data to the destination storage device.
A system for reading stored data may include one or more Ethernet drives and a controller, both configured to communicatively connect to a host device. The controller may receive a first read command from the host device, determine a first drive among the one or more Ethernet drives using the first read command and a mapping table, translate the first read command into a second read command, and send the second read command to the first drive. Responsive to receiving the second read command, the first drive may send a first remote data transfer instruction to the host device independent of the controller. The first remote data transfer instruction may include stored data read from the first drive to cause the host device to write the stored data read from the first drive to one or more memory buffers in the host device indicated by the second read command.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
4.
INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE
An integrated circuit device according to an embodiment has a substrate, a first transistor, an insulating layer, a first contact, a second contact, and a first single crystal part. The first transistor has a first gate electrode, a first source region, and a first drain region provided on the substrate. The first contact faces the first gate electrode. The second contact faces a first region which is one among the first source region and the first drain region. The first single crystal part forms a protruding section, which is provided on the first region and protrudes from the outer surface of the first region, and is positioned between the first region and the second contact.
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
5.
SYSTEM AND METHOD FOR MANAGING GUI OF VIRTUAL NVME ENTITIES IN NVME OVER FABRIC APPLIANCE
A method includes enabling, by a processor, a user to create indication of configuration of a virtual subsystem. The processor enables the user to create, in the indication of configuration of the virtual subsystem, indication of a namespace associated with one of storage devices, indication of a controller, indication of a host, and indication of connectivity between a controller and a namespace or between a host and a namespace. The processor enables the user to select the indicated controller and the indicated namespace, select the indicated host and the indicated controller, and create, in the indication of configuration of virtual subsystem, indication of connectivity between the controller and the namespace and indication of connectivity between the host and the controller. The processor implements the configuration of the virtual subsystem in an appliance to cause the appliance to provide the host with storage access to the namespace via the controller.
Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.
A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.
A semiconductor storage device includes a controller including a data direct memory access (DDMA) controller. The controller receives a plurality of read commands segmented into data transfer descriptors associated with data tags from a host device and directs a plurality of the data transfer descriptors to the DDMA controller. The DDMA controller pre-fetches one or more descriptors from the host device associated with one or more of the plurality of data tags, a first data tag having an associated number of descriptors corresponding to contiguous blocks of memory. The DDMA controller determines if the associated number of descriptors satisfies a threshold, and, if it does not, moves the first data tag to a first list, when at a head of the first list moves the first data tag to a second list, and when at a head of the second list, transmits the data associated with the first data tag.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
The present invention provides a method for analyzing a silicon substrate that enables highly accurate analysis, by ICP-MS, of impurities such as trace metals in a silicon substrate on which a nitride film of large film thickness has been formed. The present invention is a method of analysis using a silicon substrate analysis device provided with a loading port, a substrate transport robot, an aligner, a drying chamber, a vapor phase decomposition chamber, an analysis scan port including an analysis stage and a substrate analysis nozzle, an analytical solution collecting means, and an analysis means for analysis with inductively coupled plasma, wherein the method of analysis is characterized by: sweeping over the surface of a silicon substrate on which a nitride film has been formed with a recovery solution of a mixed solution of hydrofluoric acid and hydrogen peroxide from the substrate analysis nozzle and recovering same, thereafter discharging the recovery solution onto the silicon substrate surface and drying by heating, discharging a strong acid solution or a strong alkaline solution and drying by heating, sweeping the silicon substrate surface with an analytical solution and recovering same, and analyzing the analytical solution by ICP-MS.
G01N 27/62 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electric discharges, e.g. emission of cathode
10.
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM
The information processing device according to an embodiment of the present invention is provided with a first memory, a first reception unit, a first determination unit, and a first transmission unit. The first memory holds first video data on the interior of an automobile at a first time. The first reception unit receives, from the automobile through wireless communication, second video data on the interior of the automobile at a second time which is after the first time. The first determination unit determines whether or not there is a change in the interior of the automobile between the first time and the second time, on the basis of the first video data and the second video data. The first transmission unit transmits, to the automobile through wireless communication, first data based on the determination result obtained by the first determination unit.
A semiconductor storage device (1) according to the present invention is provided with: a plurality of first electrode layers (SGS, WL1) which are stacked in a first direction (Z); a plurality of second electrode layers (WL2, SGD) which are stacked in the first direction; a first pillar body (PB1) which penetrates through the plurality of first electrode layers in the first direction; a second pillar body (PB2) which penetrates through the plurality of second electrode layers in the first direction; a joint part (JP) which connects the first pillar body and the second pillar body with each other; and an island-like spacer film (20) which surrounds the joint part. The plurality of first electrode layers and the plurality of second electrode layers are arranged in the first direction; and the joint part and the spacer film are positioned between the plurality of first electrode layers and the plurality of second electrode layers.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor chip includes a semiconductor die formed on a substrate, a first power mesh formed on the substrate, and a second power mesh formed on the substrate electrically isolated from the first power mesh. The semiconductor chip also includes a first circuit block formed on the substrate and electrically connected to the first power mesh, and a second circuit block formed on the substrate and electrically connected to the second power mesh. The first circuit block and the second circuit block are communicatively coupled to a first plurality of external circuit connections and a second plurality of external circuit connections, respectively. The semiconductor chip also includes one or more first signal pins and one or more second signal pins formed on the substrate, the first and second signal pins designed to receive external signals.
In one embodiment, a network of SSDs includes a switch with a plurality of powered ports configured to be communicatively coupled to a controller and a host client and a plurality of SSDs configured to be communicatively coupled to the plurality of powered ports. The switch is configured to deliver up to a predefined power level to each of the plurality of SSDs via the plurality of powered port. Each of the plurality of SSDs consumes power. The controller is configured to manage the predefined power level for each of the plurality of SSDs by identifying the power consumed by each of the plurality of SSDs and allocating a new power level to each of the plurality of SSDs based on the power consumed by each of the plurality of SSD. In one embodiment, the switch and the plurality of SSDs are configured to occupy a server rack space.
A device for storing key-value (KV) data includes non-volatile memory and a controller. The controller includes a decapsulator and a KV mapper to receive network data communicated over a network, for example using a layer 2 protocol. The decapsulator is configured to decapsulate a payload from the network data, the payload including a key-value pair and first information. The KV mapper is configured to receive the key-value pair and the first information decapsulated from the network data, and determine, based on the received key-value pair and first information, a first location of the non-volatile memory. The controller is further configured to store KV data corresponding to the key-value pair at the first location of the non-volatile memory based on the first information.
An information processing device according to one embodiment reserves a power supply station that charges a battery of an electric vehicle. The information processing device comprises: a receiving unit that receives a first piece of information indicating battery remaining-power, a second piece of information relating to a destination and a third piece of information relating to a route; a first search unit that searches for a recommended route to the destination, on the basis of the second and third pieces of information; a second search unit that searches for a power supply station; a first evaluation unit that evaluates whether the battery needs to be charged on the way to the destination, on the basis of the first piece of information and the recommended route; and a reservation unit that, if the evaluation is that the battery needs to be charged, reserves the power supply station without waiting for a command from a user.
In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the first region in the first operation mode.
A storage appliance includes a first SSD, a second SSD, and a controller. Hie controller is able to calculate a first utilization parameter of the first SSD and a second utilization parameter of the second SSD. If the first utilization parameter is less than a threshold and the second utilization parameter exceeds the threshold, the controller identifies a data range stored on the first SSD to be removed. The removal of the data range from the first SSD causes the first utilization parameter to exceed the threshold. The controller then migrates the data range from the first SSD to the second SSD.
A network storage appliance comprises solid state disks, a network interface adapter communicatively coupled to the solid state disks and a host client, a non-volatile semiconductor memory device communicatively coupled to the solid state disks and the network interface adapter, and a CPU communicatively coupled to the non-volatile semiconductor memory device and the network interface adapter. The non-volatile semiconductor memory device can receive data from the host client via the network interface adapter, store the data temporarily, and transfer the data to one of the solid state disks. The CPU can receive a write request from the host client via the network interface adapter, determine whether or not the non-volatile semiconductor memory device is available to store the data, initiate the network interface adapter to perform the transfer of the data, from the host client to the non-volatile semiconductor memory device if the non-volatile semiconductor memory device is available to store the data, and initiate the network interface adapter to broadcast a query to one or more external storages if the non-volatile semiconductor memory device is not available to store the data.
This semiconductor storage device includes: a first memory string that includes a first memory cell; a bit line; a sense amplifier that includes a latch circuit; a data register that is connected to the sense amplifier and that transmits and receives data to/from the sense amplifier; and a control circuit that can execute a reading operation from the first memory cell by suspending a writing operation during the writing operation in the first memory cell. In the reading operation from the first memory cell executed by suspending the writing operation in the first memory cell, the sense amplifier transmits data read from the first memory cell as read data to the data register when the writing in the first memory cell has ended, and transmits write data held by the latch circuit as read data to the data register when the writing in the first memory cell has not ended.
According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.
Provided is a semiconductor storage device which is able to be produced with less cost. A semiconductor storage device according to one embodiment of the present invention is provided with a first substrate, a first element layer that is provided on the upper surface of the first substrate, a second substrate, and a second element layer that is provided on the upper surface of the second substrate. The first substrate comprises a first via. The first element layer comprises a first pad which is electrically connected to the first via, while being provided on the upper surface of the first element layer; and the second substrate comprises a second via. The second element layer comprises a second pad which is electrically connected to the second via, while being provided on the upper surface of the second element layer. The upper surface of the second element layer is arranged so as to face the upper surface of the first element layer. The first pad and the second pad are arranged symmetrically with respect to the facing surfaces of the first element layer and the second element layers, while being electrically connected to each other.
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
22.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device according to this embodiment includes a laminate body and a columnar part. The laminate body includes: a first laminate part including a plurality of electrode layers laminated in a first direction with insulating bodies therebetween; a second laminate part including a plurality of electrode layers laminated in the first direction with insulating bodies therebetween, the second laminate part being disposed separated from the first laminate part in the first direction; and a linking part provided between the first laminate part and the second laminate part, the linking part including a high dielectric layer having higher relative permittivity than the insulating bodies. The columnar part includes: a first portion provided in the first laminate part, extending in the first direction of the laminate body; a second portion provided in the second laminate part, extending in the first direction; and an intermediate part provided in the linking part, connecting the first portion and the second portion.
The semiconductor device according to an embodiment includes a laminate, a first insulating layer, first and second step parts 2, and a second insulating layer 46. The laminate includes a first electrode layer 41 (WLDD) and a second electrode layer 41 (SGD). The first and second step parts 2 are provided to a first end-section region 101 and a second end-section region 102. The second insulating layer 46 extends in the X-direction. The second insulating layer divides the second electrode layer 41 (SGD) along the X-direction. The length L1 of the second insulating layer 46 along the X-direction is greater than the length L2 of the second electrode layer 41 (SGD) along the X-direction and less than the length L3 of the first electrode layer 41 (WLDD) along the X-direction.
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A memory device according to an embodiment includes: a first memory chip which includes a first circuit and first and second terminals; a second memory chip which includes a second circuit and a third terminal; and an interface chip which includes first and second voltage generation circuits. The second memory chip is provided above the first memory chip, and the interface chip is provided below the first memory chip. A first end section of the first terminal is connected to the first circuit, and a second end section of the first terminal is connected to the first voltage generation circuit. A third end section of the second terminal is connected to the third terminal, and a fourth end section of the second terminal is connected to the second voltage generation circuit. A fifth end section of the third terminal is connected to the second circuit, and a sixth end section of the third terminal is connected to the second voltage generation circuit via the second terminal. The third end section does not overlap the fourth end section and does overlap the sixth end section in a direction perpendicular to the surface of the first memory chip.
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
This storage device comprises a first memory cell and a second memory cell adjacent to the first memory cell, and a sequencer which, when reading data from the first memory cell, performs a first read operation on the second memory cell, performs a second read operation on the first memory cell, and performs a third read operation on the first memory cell while applying a voltage different from the voltage when performing the second read operation to the gate of the second memory cell, the sequencer generating, on the basis of the results of the first through third read operations, first data stored in the first memory cell and second data for correcting the first data.
A memory device according to an embodiment includes: a first memory chip which includes a first circuit and first and second terminals; a second memory chip which includes a second circuit and a third terminal; and an interface chip which includes first and second voltage generation circuits. The second memory chip is provided above the first memory chip, and the interface chip is provided below the first memory chip. A first end section of the first terminal is connected to the first circuit, and a second end section of the first terminal is connected to the first voltage generation circuit. A third end section of the second terminal is connected to the third terminal, and a fourth end section of the second terminal is connected to the second voltage generation circuit. A fifth end section of the third terminal is connected to the second circuit, and a sixth end section of the third terminal is connected to the second voltage generation circuit via the second terminal. The third end section does not overlap the fourth end section and does overlap the sixth end section in a direction perpendicular to the surface of the first memory chip.
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
Provided is a storage device comprising a memory cell array that stores data; a control circuit that controls the memory cell array according to commands; and a receiver which enters an active state on the basis of operations results of a first signal, a second signal or an address and a command, and which can receive a command or data.
According to one embodiment, a first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.
A semiconductor storage device of an embodiment is provided with a row decoder and a memory cell array equipped with a first block. The first block is provided with a first region CEL, a second region WLHU adjacent to the first region CEL in a first direction (Y-direction), and a third region CNCT for connecting the first region CEL and the second region WLHU. The memory cell array is further equipped with: a first insulating layer 730 burying a first trench DY between the first region CEL and the second region WLHU and making contact with the third region CNCT; a first contact plug CP12 provided in the first insulating layer 730 and electrically connected to the row decoder; and a first wiring layer IC1 for connecting a select gate line SGD and the first contact plug CP12.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
30.
SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME
The semiconductor device according to an embodiment includes a substrate, a laminated body, and a columnar part. The laminated body is provided on the substrate, and has a plurality of first electroconductive layers and a plurality of first insulation layers. The first electroconductive layers and the first insulation layers are provided in alternating fashion along a first direction. The columnar part includes a block layer, a charge accumulation layer, a tunnel layer, and a semiconductor layer extending in the first direction in the laminated body. In a second direction, which intersects the first direction, the block layer is provided on the plurality of first electroconductive layers and the plurality of first insulation layers, the charge accumulation layer is provided on the block layer, the tunnel layer is provided on the charge accumulation layer, and the semiconductor layer is provided on the tunnel layer. The columnar part includes a first part, and a second part provided on the substrate side relative to to the first part. The dimension in the second direction of the second part is smaller than the dimension in the second direction of the first part. A part provided on the second part of the block layer is thicker than a part provided on the first part of the block layer.
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor device according to one embodiment of the present invention is provided with: first through 32nd memory cells; first through 16th bit lines connected to the first through 16th memory cells; 17th through 32nd bit lines connected to the 17th through 32nd memory cells; a first word line connected to the gate of the first through 32nd memory cells; first through 16th sense amplifiers for determining, at a first timing, data read out by the first through 16th memory cells; and 17th through 32nd sense amplifiers for determining, at a second timing, data read out by the 17th through 32nd memory cells. The first timing differs from the second timing.
According to one embodiment, a semiconductor memory device includes: a memory configured to store data; an error correcting circuit configured to correct an error in data read from the memory, and to generate a first signal of a first state, which is transmitted to an external along with the data if the error in the data cannot be corrected; and a first pin configured to transmit the first signal to the external and receive a data mask signal from the external.
According to one embodiment, a memory- includes a bit line connected to a memory cell; and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell; a first transistor to control a current supplied to the memory cell based on a first control signal; and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first bank and a gate of the first transistor of the second bank are independently supplied with a voltage.
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
35.
MAGNETIC SHIELD TRAY, MAGNETIC SHIELD WRAPPER AND MAGNETIC MEMORY PRODUCT SHIELDED FROM EXTERNAL MAGNETIC FIELD
According to an embodiment, a magnetic shield tray includes a main body with a plate form including a magnetic material, and mount portions as holes disposed in the main body. The magnetic material is exposed on an inner surface of the holes.
This invention realizes a configuration that can quickly make data persistent when a computer such as a server is configured redundantly to provide high reliability. An electronic circuit board of an embodiment is provided with a non-volatile memory, a reading section, a switching section, and a communication section. The reading section reads data stored in the non-volatile memory. When power is supplied from a first power source, the switching section switches to a first state in which a host apparatus that reads data from and writes data to the non-volatile memory is connected to the non-volatile memory, and when power is supplied from a second power source, the switching section switches to a second state in which the host apparatus and the non-volatile memory are not connected and the reading section and the non-volatile memory are connected. When power is supplied from the second power source, the communication section sends the data that the reading section read from the non-volatile memory to an external apparatus.
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G06F 1/26 - Power supply means, e.g. regulation thereof
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
37.
MEMORY CONTROLLER, INFORMATION PROCESSING DEVICE, AND PROCESSING DEVICE
According to the present invention, a high-performance and highly-reliable data perpetuating method is realized. A memory controller of an embodiment includes a non-volatile cache memory and a controller. The non-volatile cache memory stores therein one portion of data stored in a non-volatile main memory connected to the memory controller. The controller controls writing into the non-volatile cache memory. The memory controller is connected to a processing device via an interconnector that guarantees a protocol indicating a procedure for preventing mismatch of data among a plurality of cache memories. After detecting that data stored in any region of the non-volatile main memory has been updated by the processing device, the controller transmits the updated data to the memory controller and writes the updated data into the non-volatile cache memory by using the protocol.
According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
39.
SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREFOR
The semiconductor storage device according to an embodiment is provided with: a semiconductor pillar that extends in a first direction; a first electrode that extends in a second direction intersecting the first direction; a second electrode provided between the semiconductor pillar and the first electrode; a first insulating film provided between the semiconductor pillar and the second electrode; and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin plate portion that is disposed at the first electrode side and a thick plate portion that is disposed at the semiconductor pillar side and that has a length in the first direction longer than that of the thin plate portion.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor memory device according to an embodiment is provided with: a plurality of semiconductor pillars that extend in a first direction and that are arranged along a second direction intersecting the first direction; two wires that are provided on both sides of the plurality of semiconductor pillars in a third direction intersecting the first direction and the second direction and that extend in the second direction; and an electrode film disposed between each of the semiconductor pillars and each of the wires. The two wires can be driven independently of each other.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
G11C 5/00 - STATIC STORES - Details of stores covered by group
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
A template 1 for imprinting according to one embodiment is provided with: a substrate 2 that has a main surface 2a; a protruding portion 3 that is provided on the main surface 2a and has an end surface on the side opposite to the main surface 2a, wherein a recess/protrusion pattern 3a that is pressed into a liquid transfer object is formed on said end surface; and a liquid-repellent layer 4 that is formed on at least a side surface of the protruding portion 3, avoiding the recess/protrusion pattern 3a, and repels the liquid transfer object.
An imprinting template production device 1 according to one embodiment is provided with: a support portion 3 that supports a template W equipped with a substrate 11, which has a main surface, and a protruding portion 12, which is provided on the main surface and has an end surface on the opposite side from the main surface and in which a recess/protrusion pattern is formed on said end surface, such that the protruding portion 12 faces downward; a vaporizing portion 5 that is provided on the support portion 3 below the template W and vaporizes a liquid-repellent material; and an adhesion prevention plate 7 that is provided on the support portion 3 below the template W, allows the vaporized liquid-repellent material to adhere to a side surface of the protruding portion 12 of the template W on the support portion 3, and prevents adhesion to the recess/protrusion pattern.
B29C 33/38 - SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING - Details thereof or accessories therefor characterised by the material or the manufacturing process
B29C 59/02 - Surface shaping, e.g. embossing; Apparatus therefor by mechanical means, e.g. pressing
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
An imprinting template production device 1 according to one embodiment is provided with: a stage 3 that supports a template W equipped with a substrate 11, which has a main surface, and a protruding part 12, which is provided on the main surface and has an end surface on the opposite side from the main surface and in which a recess/protrusion pattern is formed on said end surface; a supply head 4 that supplies a liquid liquid-repellent material to the template W on the stage 3; a movement mechanism (a Y-axis movement mechanism 6 or a pair of X-axis movement mechanisms 8A and 8B) that moves the stage 3 and the supply head 4 relative to each other in a direction parallel to the stage 3; and a control part 9 that controls the supply head 4 and the movement mechanism such that the supply head 4 applies the liquid liquid-repellent material to at least a side surface of the protruding part 12, avoiding the recess/protrusion pattern.
A memory device control method of an embodiment of the present invention is configured as follows: a first semiconductor memory receives a read command sent from a controller; a second semiconductor memory receives a write command sent from the controller; data is read from within the first semiconductor memory on the basis of the read command; the first semiconductor memory sends the data and a control signal indicating that the data has been outputted; and on the basis of the write command, the second semiconductor memory receives the data at a timing based on the control signal, and the received data is written in the second semiconductor memory.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a first end connected to the bit line, a second transistor with a first end connected to a second end of the first transistor, a third transistor with a first end connected to the bit line, a fourth transistor with a first end connected to a second end of the third transistor, and an amplifier connected to a second end of the second transistor and to a second end of the fourth transistor.
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
According to one embodiment, a memory system includes: a first memory cell area where a first memory cell is provided; a second memory cell area where a second memory cell is provided; an ECC circuit which corrects an error of data stored by the first memory cell; and a control circuit which replaces the first memory cell with the second memory cell if the number of times an error is successfully corrected in the first memory cell reaches a first value.
According to one embodiment, a memory device includes: a memory cell array including a first and a second array; a fuse circuit to hold first data; and a control circuit to control a replacement process on the first and second arrays based on the first data. When a first address in a first direction in the first array is supplied, the fuse circuit transfers the first data corresponding to the first address to the control circuit, and when a second address in a second direction in the first array is supplied after the first data is transferred, the control circuit accesses one of the first and second arrays based on a comparison result for the second address and the first data.
G11C 29/00 - Checking stores for correct operation; Testing stores during standby or offline operation
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
According to an embodiment of the present invention, a semiconductor storage device is provided with: first and second semiconductor pillars, which extend in the first direction, and are disposed in the second direction intersecting the first direction; first and second wiring lines, which are provided between the first semiconductor pillar and the second semiconductor pillar, and extend in the third direction intersecting both the first direction and the second direction; a first electrode that is provided between the first semiconductor pillar and the first wiring line; a second electrode that is provided between the second semiconductor pillar and the second wiring line; third and fourth wiring lines, which extend in the second direction, and pass both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar; a first contact, which is in contact with the first semiconductor pillar, and is connected to the third wiring line; and a second contact, which is in contact with the second semiconductor pillar, and is connected to the fourth wiring line.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A memory device of one embodiment includes memory elements which store data and parity; a first decoder which, when scrubbing of the data is performed while no external access is being made to the memory device, uses a syndrome generated from the data and the parity to correct an error of a maximum of N bits in a unit of the data; and a second decoder which, when reading of the data is performed, uses the syndrome to correct an error of a maximum of M bits in a unit of the data. The M bits represents the number of bits smaller than the N bits.
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G06F 12/16 - Protection against loss of memory contents
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
51.
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR PRODUCING SAME
A semiconductor memory device according to an embodiment of the present invention is provided with: a semiconductor pillar that extends in a first direction; a first electrode that extends in a second direction that crosses the first direction; a second electrode provided between the semiconductor pillar and the first electrode; a first insulating film provided between the first electrode and the second electrode, and on both first-direction sides of the first electrode; a second insulating film provided between the second electrode and the first insulating film, and on both first-direction sides of the second electrode; a third insulating film provided between the second electrode and the semiconductor pillar; and a conductive film provided in a region sandwiched between the first insulating film and the second insulating film.
A semiconductor storage device of an embodiment of the present invention is equipped with a pair of first electrodes, semiconductor pillars, inter-pillar insulation members, a first insulation film, a second electrode, and a second insulation film. The pair of first electrodes extend in a first direction away from one another. The semiconductor pillars and the inter-pillar insulation members are arranged alternately in the first direction between the pair of first electrodes. The semiconductor pillars and the inter-pillar insulation members extend in a second direction that intersects the first direction. The first insulation film is disposed in the periphery of the semiconductor pillars. The second electrode is disposed between each of the pair of first electrodes and the first insulation film. The second electrode is not disposed between the semiconductor pillars and the inter-pillar insulation member. The second insulation film is disposed between the second electrode and the first electrode.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
53.
SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME
According to an embodiment of the present invention, this semiconductor storage device is provided with: a semiconductor pillar extending in the first direction; a first electrode extending in the second direction intersecting the first direction; a second electrode that is provided between the semiconductor pillar and the first electrode; a first insulating film that is provided between the semiconductor pillar and the second electrode; a second insulating film, which is provided between the first electrode and the second electrode, and on both the first electrode sides in the first direction; and a conductive film, which is provided between the second electrode and the second insulating film, and is not in contact with the first insulating film.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor