A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
2.
Memory system and method of controlling memory system
According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
5.
TEMPLATE, TEMPLATE MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
According to one embodiment, a template for imprint patterning processes comprises a template substrate having a first surface and a pedestal on the first surface of the template substrate, the pedestal having a second surface spaced from the first surface in a first direction perpendicular to the first surface. A pattern is disposed on the second surface. The pedestal has a sidewall between the first surface and the second surface that is at an angle of less than 90° to the second surface.
B29C 33/42 - SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING - Details thereof or accessories therefor characterised by the shape of the moulding surface, e.g. ribs or grooves
B29C 35/08 - Heating or curing, e.g. crosslinking or vulcanising by wave energy or particle radiation
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
B29C 37/00 - Component parts, details, accessories or auxiliary operations, not covered by group or
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
B29C 43/02 - Compression moulding, i.e. applying external pressure to flow the moulding material; Apparatus therefor of articles of definite length, i.e. discrete articles
B29C 43/38 - Moulds for making articles of definite length, i.e. discrete articles with means to avoid flashes
A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
7.
SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
In one embodiment, a semiconductor manufacturing apparatus includes a substrate holder configured to hold a plurality of substrates such that the substrates are arranged in parallel to each other. The apparatus further includes a fluid injector including a plurality of openings that inject fluid to areas in which distances from surfaces of the substrates are within distances between centers of the substrates adjacent to each other, the fluid injector being configured to change injection directions of the fluid injected from the openings in planes that are parallel to the surfaces of the substrates by self-oscillation.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
8.
NON-VOLATILE STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
9.
Memory device which generates operation voltages in parallel with reception of an address
A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.
A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through its second and third transistors.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.
H03M 7/00 - Conversion of a code where information is represented by a given sequence or number of digits to a code where the same information is represented by a different sequence or number of digits
H03M 7/34 - Conversion to or from delta modulation, i.e. one-bit differential modulation adaptive
H03M 7/30 - Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
G06F 3/06 - Digital input from, or digital output to, record carriers
According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.
A solid state drive (SSD) with improved techniques for testing power loss protection (PLP) capacitors and a method for testing PLP capacitors of SSDs is disclosed. In one embodiment, the SSD includes a memory controller and one or more non-volatile memory devices and a volatile memory device coupled to the memory controller. The SSD also includes a PLP capacitor configured to supply a first voltage to the memory controller, the one or more non-volatile memory devices, and the volatile memory device in the event of a power loss or failure of the SSD. In one embodiment, the PLP capacitor is further configured to increase the first voltage to a second voltage prior to testing the PLP capacitor. In another embodiment, the memory controller is configured to reduce a volume of data stored in the volatile memory device prior to testing the PLP capacitor.
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.
According to one embodiment, a method of manufacturing a memory device includes forming a first layer stack and a second layer stack at an interval on a foundation, and forming a first insulator that includes a first portion on a side surface of the first layer stack, a second portion on a side surface of the second layer stack, and a third portion on the foundation between the first and second layer stacks. Part of the first portion of the first insulator and part of the second portion are thinned with an ion beam while leaving the third portion of the first insulator. A second insulator is formed between the first and second portions of the first insulator.
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
17.
Imprinting method and semiconductor device manufacturing method
According to one embodiment, an imprinting method comprises forming a carbon film on a substrate. The carbon film being oxygen in an amount of less than or equal to 15% by weight. A transfer material is dispensed over the carbon film. A patterned template is brought into contact with the transfer material. The transfer material is cured with light passing through the patterned template. The patterned template is then detached from the cured transfer material.
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
According to one embodiment, a magnetic device includes a stacked body including a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first magnetic layer and the second magnetic layer. The stacked body has a quadrangular planar shape, the stacked body has a first side dimension in a first direction parallel to a surface of a substrate and a thickness in a second direction perpendicular to the surface of the substrate, and a ratio of the first side dimension to the thickness is in a range of 0.10 to 4.0.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
A magnetic storage device includes a magnetic body including first and second magnetic regions and a magnetic connection region that connects the first and second magnetic regions, and in which a plurality of magnetic domains each storing information by a magnetization direction thereof is formed, a read element that is electrically connected to the magnetic connection region and by which a magnetization direction of one of the magnetic domains is read, and a write element by which a magnetic domain having a magnetization direction is formed in the magnetic body according to information to be stored. The magnetic domains formed in each of the first and second magnetic regions are shifted in a predetermined direction in response to current that flows through the corresponding one of the first and second magnetic regions.
G11C 19/08 - Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
According to one embodiment, a semiconductor device includes: a semiconductor substrate; a first via provided on the semiconductor substrate; a metal wiring provided on the first via; and a second via provided on the metal wiring. One of the side surfaces facing each other in the first direction of the metal wiring and one of the side surfaces facing each other in the first direction of the second via are aligned in the first direction.
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layers; After-treatment of these layers
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/528 - Layout of the interconnection structure
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
21.
Memory system for writing fractional data into nonvolatile memory
According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory and a controller circuit. The controller circuit configured to control the volatile memory and the nonvolatile memory and to perform a write process and a non-volatilization process. The controller circuit is further configured to, during the write process, store write data in the volatile memory, and during the non-volatilization process, upon determining that data size stored in the write buffer being less than unit of writing of the nonvolatile memory, suspend completion of the non-volatilization process and not return a notification of completion of the non-volatilization process.
A magnetic storage device includes a memory cell with a magnetoresistive effect element and a switching element connected in series. The magnetoresistive effect element is configured to change from a first resistance state to a second resistance state that is lower in resistance than the first resistance state in response to a first write operation flowing current in a first direction through the memory cell and to change from the second resistance state to the first resistance state in response to a second write operation flowing current in a second direction through the memory cell. The switching element has a first voltage drop associated with current flows in the first direction and has a second voltage drop associated with current flows the second direction that is lower than the first voltage drop.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
G11C 11/02 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11551 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
24.
Semiconductor memory device in which memory cells are three-dimensionally arrange
A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
G11C 16/26 - Sensing or reading circuits; Data output circuits
According to one embodiment, a semiconductor device includes a wiring board, a controller chip that is provided on the wiring board and is sealed with a first resin composition, a nonvolatile memory chip that is provided on the first resin composition and is sealed with a second resin composition, a second bonding wire that connects a pad for electric power supply wiring of the controller chip to the wiring board and is sealed with the first resin composition, and a first bonding wire that connects a pad for signal wiring of the controller chip to the wiring board, is sealed with the first resin composition, and has a higher Pd content than that of the second bonding wire.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
According to one embodiment, a semiconductor storage device includes a stacked body, a first columnar body, and a second columnar body. In the stacked body, a plurality of conductive layers and a plurality of insulating layers are alternately stacked along a first direction. The first columnar body extends through the stacked body. The second columnar body extends through the stacked body, and is aligned with the first columnar body along the first direction. The second columnar body includes a second channel film. The first columnar body includes a first channel film, a core surrounded by the first channel film, and a conductive layer. The conductive layer is in contact with the second channel film of the second columnar body and the first channel film of the first columnar body.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
27.
Magnetic memory device with a nonmagnet between two ferromagnets of a magnetoresistive effect element
According to one embodiment, a magnetic memory device includes a first interconnect and a magnetoresistive effect element. The first interconnect includes a first nonmagnet including a light metal and a second nonmagnet including a heavy metal on the first nonmagnet. The magnetoresistive effect element includes a third nonmagnet on the second nonmagnet, a first ferromagnet on the third nonmagnet, a second ferromagnet, and a fourth nonmagnet between the first ferromagnet and the second ferromagnet. The third nonmagnet has a film thickness of 2 nanometers or less.
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
According to one embodiment, a magnetic device includes: a first magnetic material provided above a substrate; a second magnetic material provided between the substrate and the first magnetic material; a nonmagnetic material provided between the first magnetic material and the second magnetic material; a first layer provided between the substrate and the second magnetic material and including an amorphous layer; and a second layer provided between the amorphous layer and the second magnetic material and including a crystal layer.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
According to one embodiment, a memory device includes a resistance change memory element including a first electrode, a second electrode, and an intermediate layer provided between the first electrode and the second electrode, containing germanium (Ge), tellurium (Te) and at least one element selected from lithium (Li) and sodium (Na), and at least a part of which being capable of exhibiting a crystalline state.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
31.
Magnetic memory device and manufacturing method of the same
According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a fixed magnetization direction, a nonmagnetic layer provided on the first magnetic layer, and a second magnetic layer provided on the nonmagnetic layer and having a variable magnetization direction, a first insulating layer provided along a side surface of the stacked structure and having an upper end located at a position lower than an upper end of the side surface of the stacked structure, and a second insulating layer covering the first insulating layer and having an upper end located at a position higher than the upper end of the first insulating layer.
H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
32.
Nonvolatile memory device including memory element in equal cross-sectional area of word lines and bit lines
According to one embodiment, a nonvolatile memory device includes first and second word lines, first and second bit lines, memory cells each including a resistance change memory element, a global word line including a first global word line portion including a first end portion, a global bit line including a first global bit line portion including a second end portion. The first and second word lines and the first global bit line portion have a first line width and a first line thickness, the first and second bit lines and the first global word line portion have a second line width and a second line thickness.
A memory system includes a semiconductor storage device and a memory controller. The memory controller includes a command buffer and a descriptor buffer. The memory controller stores a first command received from outside in the command buffer, fetches a first descriptor from the host device, based on the stored first command, stores the fetched first descriptor in the descriptor buffer, stores a second command received from the outside in the command buffer, discards an unused part of the first descriptor from the descriptor buffer, fetches a second descriptor from the host device, based on the stored second command, and stores the fetched second descriptor at an address where the discarded part of the first descriptor was stored.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
The semiconductor memory device of the embodiment includes a stacked body including interlayer insulating layers and gate electrode layers alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a first insulating layer provided between the semiconductor layer and the gate electrode layers; conductive layers provided between the first insulating layer and the gate electrode layers; and second insulating layers provided between the conductive layers and the gate electrode layers and the second insulating layers containing ferroelectrics. Two of the conductive layers adjacent to each other in the first direction are separated by one of the interlayer insulating layers interposed between the two of the conductive layers, and a first thickness of one of the gate electrode layers in the first direction is smaller than a second thickness of one of the conductive layers in the first direction.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/11 - Static random access memory structures
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
H01L 27/11585 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with the gate electrodes comprising a layer used for its ferroelectric memory properties, e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS]
According to one embodiment, a semiconductor device includes a storage device in which a substrate is embedded and sealed in a mold, and an antenna label attached to the storage device. The antenna label is configured to provide a wireless communication function.
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
H01Q 1/36 - Structural form of radiating elements, e.g. cone, spiral, umbrella
H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
According to one embodiment, a storage device includes a first conductive layer, a second conductive layer, a resistance-variable layer, between the first conductive layer and the second conductive layer, that includes germanium, antimony, and tellurium, a first layer, between the resistance-variable layer and the first conductive layer, that includes carbon, a second layer, between the resistance-variable layer and the second conductive layer, that includes carbon, a third layer, between the resistance-variable layer and the first layer, that includes at least one of tungsten nitride or tungsten carbide, and a fourth layer, between the resistance-variable layer and the second layer, that includes at least one of tungsten nitride or tungsten carbide.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
A magnetic storage device includes a first and a second stacked body including a first ferromagnetic body and a second ferromagnetic body, respectively. A first magnetoresistive effect element includes the first ferromagnetic body and a third ferromagnetic body with a first nonmagnetic body between the first and third ferromagnetic bodies. A second magnetoresistive effect element includes the first ferromagnetic body and a fourth ferromagnetic body with a second nonmagnetic body between the first and fourth ferromagnetic bodies. A third magnetoresistive effect element includes the second ferromagnetic body and a fifth ferromagnetic body with a third nonmagnetic body between the second and fifth ferromagnetic bodies. A fourth magnetoresistive effect element includes the second ferromagnetic body and a sixth ferromagnetic body with a fourth nonmagnetic body between the second and sixth ferromagnetic bodies. The third and fourth ferromagnetic bodies are between the first and second stacked bodies.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
A nonvolatile storage device includes first and second interconnections and a memory cell between the first and second interconnections. The memory cell includes a storage element, a first switch, and a second switch. The first switch has two terminals and transitions from an off-state to an on-state when a first threshold voltage is applied between its terminals and then voltage between the terminals falls to a first hold voltage. The second switch has two terminals and transitions from an off-state to an on-state when a second threshold voltage is applied between its terminals and then voltage between the terminals falls to a second hold voltage. An off-current of the first switch is less than an off-current of the second switch. The first threshold voltage is greater than the second threshold voltage, which is greater than the first hold voltage, which is greater than or equal to the second hold voltage.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
According to one embodiment, a storage device includes: a memory cell including a storage component to which a plurality of data values are allowed to set in response to a plurality of resistance values of the storage component and a selector connected in series to the storage component; a word line configured to provide a signal to select the memory cell; a bit line configured to receive a data signal from the memory cell; a first conversion circuit configured to nonlinearly convert a first current, generated in response to the data signal input to the bit line, into a first voltage; and a comparison circuit configured to compare the first voltage, converted by the first conversion circuit, with a plurality of reference voltages.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
41.
Semiconductor storage device and method of manufacturing the same
A semiconductor storage device includes a first chip bonded to a second chip. The first chip includes electrode layers stacked in a first direction, a pillar extending through the stacked electrode layers and including a semiconductor film, and a memory film between the semiconductor film and the electrode layers. The second chip includes a semiconductor substrate having transistors formed thereon, a wiring connected to the transistors and between the semiconductor substrate and the first chip, bonding pads at a level closer to the first chip than the transistors. The bonding pads have a bonding surface facing away from the first chip. An opening extends through the semiconductor substrate to the bonding surface of the bonding pad.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
42.
Semiconductor integrated circuit and reception device
According to one embodiment, in a semiconductor integrated circuit, a variable delay circuit is electrically connected to the correction circuit and configured to change a delay amount of the second clock. An adjustment circuit is electrically connected to a summer circuit. The adjustment circuit is configured to perform sampling of values in a plurality of edge periods and values in a plurality of data periods of data output from the summer circuit, and adjust a delay amount of the variable delay circuit such that timing of the second clock supplied from the variable delay circuit to the correction circuit becomes close to target timing according to a plurality of sampling results.
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
According to one embodiment, there is provided a semiconductor device including a substrate, a semiconductor chip, and a conductive film. The substrate has a main face. The semiconductor chip has a surface equipped with an SRAM circuit. The semiconductor chip is mounted on the main face via a plurality of bump electrodes in a state where the surface faces the main face. The conductive film is disposed on the main face or the surface. The conductive film extends planarly between the plurality of bump electrodes. A region in the main face or the surface where the conductive film is disposed overlaps the SRAM circuit in a direction perpendicular to the main face.
According to one embodiment, a semiconductor memory device comprising: a first memory layer including a plurality of memory units electrically coupled to one another; a first memory area including a first memory unit for data writing of the memory units; a second memory area including a second memory unit for data reading of the memory units; and a controller configured to write data in the first memory unit, shift the data written in the first memory unit to the second memory unit, and read data written in the second memory unit.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
45.
Semiconductor device manufacturing method and semiconductor device
A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; forming a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
46.
Magnetic memory device having an incline side surface
According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The first magnetic layer includes a first surface in contact with the nonmagnetic layer and a second surface on an opposite side to the first surface, a diameter of the second surface of the first magnetic layer is less than a diameter of the first surface of the first magnetic layer and is 10 nm or more, and a ratio of a height of the first magnetic layer to the diameter of the second surface of the first magnetic layer is 0.9 or more.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
In an alignment mark of an embodiment, a first pattern includes a first portion and a second portion, a second pattern includes a third portion and a fourth portion, the first portion and the third portion partially overlap each other, the second portion and the fourth portion partially overlap each other, a pitch length of each structural periods of the first portion and the third portion are equal within 1.2 times, a pitch length of each structural periods of the second portion and the fourth portion are equal within 1.2 times, a duty ratio of each of the first and third portions is 1:1, and a duty ratio of the second portion is D:2, and D is an integer of two or more, the duty ratio being a ratio between a light-shielding portion and a light-transmitting portion.
G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
According to one embodiment, a magnetic memory device includes a magnetoresistive element including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. The first magnetic layer contains nickel (Ni), cobalt (Co), manganese (Mn) and gallium (Ga) and has a spin polarization less than 0.71.
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A storage device includes a first conductor, a second conductor, a variable resistance layer, a first portion, and a second portion. The variable resistance layer connects with the first conductor or the second conductor. The first portion is provided between the first conductor and the second conductor, and has a first threshold voltage value at which the resistance value changes. The second portion is provided between the first conductor and the first portion and/or between the second conductor and the first portion, and has a second threshold voltage value at which the resistance value changes and which is higher than the first threshold voltage value.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
According to one embodiment, a semiconductor device includes a wiring board, a spacer board that is mounted on the wiring board and in which a power supply conductor layer and a ground conductor layer are provided, at least one first semiconductor chip that is mounted on the spacer board including a power supply layer electrically connected to the power supply conductor layer and a ground layer electrically connected to the ground conductor layer, and a second semiconductor chip that is mounted on the wiring board.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
According to one embodiment, a semiconductor device includes a semiconductor layer, a charge storage layer provided on the surface of the semiconductor layer via a first insulating film, and an electrode layer provided on the surface of the charge storage layer via a second insulating film. The first insulating film includes a first region where the compositional ratio of nitrogen to silicon, oxygen and nitrogen varies from a first value to a second value, which is lower than the first value, along a first direction from the semiconductor layer toward the charge storage layer.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
53.
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a semiconductor wafer chip, a semiconductor device layer, and a reflectance reducing layer. The semiconductor wafer chip includes a device region and a peripheral region around the device region. The peripheral region includes a plurality of voids aligned along a side surface of the semiconductor wafer chip at a predetermined depth from a first surface of the semiconductor wafer chip. The semiconductor device element layer is on the first surface in the device region. The reflectance reducing layer is on the first surface of the semiconductor wafer chip in the peripheral region, that reduces a reflection of laser light incident from a second surface of the semiconductor wafer chip.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit.
G06F 3/06 - Digital input from, or digital output to, record carriers
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
In a manufacturing method of a semiconductor device according to one embodiment, a first gas containing a first metal element is introduced into a chamber having a substrate housed therein. Next, the first gas is discharged from the chamber using a purge gas. Subsequently, a second gas reducing the first gas is introduced into the chamber. Next, the second gas is discharged from the chamber using the purge gas. Further, a third gas different from the first gas, the second gas, and the purge gas is introduced into the chamber at least either at a time of discharging the first gas or at a time of discharging the second gas.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/14 - Deposition of only one other metal element
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
A method for scheduling tasks on a processor includes detecting, in a task selection device communicatively coupled to the processor, a condition of each of a plurality of components of a computer system comprising the processor, determining a plurality of tasks that can be next executed on the processor based on the condition of each of the plurality of components, transmitting a signal to an arbiter of the task selection device that the plurality of tasks can be executed, determining, at the arbiter, a next task to be executed on the processor, storing, by the task selection device, the entry point address of the next task to be executed on the processor, and transferring, by the processor, execution to the stored entry point address of the next task to be executed.
According to one embodiment, an electronic apparatus includes a first processor, a second processor with a security capability higher than a security capability of the first processor, a first nonvolatile memory to store a program which is to be executed by the first processor, and a volatile second memory to store the program and data that is to be referred to by the first processor while the first processor executes the program. The second processor is configured to authenticate a rewrite command requesting to change the data in the second memory and selectively execute the rewrite command based on the authentication.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/34 - User authentication involving the use of external additional devices, e.g. dongles or smart cards
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures
According to one embodiment, a memory system includes a NAND flash memory that has a first area, a second area, and a third area, and a controller that controls data transfer between a host device and the memory system. The controller writes data transmitted from the host device to the first area by a first method of storing 1-bit data per memory cell, and at a first timing, reads at least a part of data stored in the first area to generate one unit data, compresses the unit data, and writes the compressed unit data to the second area. At a second timing, the controller decompresses the read compressed unit data from the second area, and writes the decompressed unit data to the third area by a second method of storing a plurality of bits of data per memory cell.
A nonvolatile semiconductor storage device includes a memory cell array layer that includes a plurality of nonvolatile memory cells connected in series in a vertical direction above a semiconductor substrate, a plurality of word lines respectively connected to gates of the plurality of nonvolatile memory cells, a select gate transistor layer that is located above the memory cell array and includes at least first and second select gate transistors connected in series in the vertical direction and to the plurality of nonvolatile memory cells, and at least first and second select gate lines respectively connected to the at least first and second select gate transistors, and a control circuit configured to execute a read operation on the nonvolatile memory cells, such that during a read period of the read operation, signals having different voltage levels are supplied to the at least first and second select gate lines.
G11C 16/26 - Sensing or reading circuits; Data output circuits
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
60.
Semiconductor storage device and method of manufacturing the same
A semiconductor storage device includes a first stacked body, a second stacked body, a first division film, a second division film, and a plurality of discrete films. The a first stacked body includes first electrode layers stacked in a first direction. The second stacked body, above the first stacked body, includes second electrode layers stacked in the first direction. The second semiconductor layer is electrically connected to the first semiconductor layer. The first division film, extending in the first direction through the first stacked body, divides the first stacked body in a second direction crossing the first direction. The second division film, extending in the first direction through the second stacked body, divides the second stacked body in the second direction. The discrete films, extending in the first direction through the second stacked body, are disposed above the first division film.
H01L 27/11578 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11568 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region
According to one embodiment, a measurement apparatus includes a magnetic field generation section that applies a predetermined magnetic field to a device under test. A current source supplies a current of a rectangular wave to the device under test in a direction of crossing the magnetic field. A voltage measurement section measures a voltage difference generated in the device under test. A restoration section demodulates the voltage difference using a demodulated signal having the same frequency as a frequency of the rectangular wave and synchronized with the rectangular wave, removes harmonic components from the demodulated voltage difference, and restores an electromotive voltage generated in the device under test. A computing section measures the device under test using low frequency components of the electromotive voltage.
A device includes: a substrate; a first wiring layer above the substrate; a second wiring layer above the first wiring layer; a first insulating film on the first and second wiring layers; a second insulating film in the first insulating film, provided at a position overlapping with a part of the first wiring layer and a part of the second wiring layer in a first direction perpendicular to a surface of the substrate, and including a first portion higher than an upper surface of an end portion of the second wiring layer and a second portion lower than the upper surface of the end portion of the second wiring layer; and a plug via the second insulating film in the first insulating film, provided on the upper surface of the end portion of the second wiring layer, and electrically connected to the second wiring layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
A semiconductor storage device includes interconnections in a first layer and a second layer, a first memory cell between a first and a second interconnection, and a dummy memory cell between the first interconnection and a third interconnection. A controller applies a first voltage of a first polarity to the first interconnection and a second voltage of a second polarity opposite the first polarity to the second interconnection at a first time. The controller applies a third voltage at a second time after the first time to the first interconnection. The third voltage having a smaller magnitude smaller than first voltage. The controller applies a fourth voltage to the third interconnection at the second time. The fourth voltage has a magnitude larger than the third voltage but smaller than the first voltage.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 23/528 - Layout of the interconnection structure
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
A semiconductor memory device includes a first transistor connected between a high voltage line connected to a first end of a memory element and a first power supply terminal, and a second transistor connected between the high voltage line and a second power supply terminal, a third transistor connected between a low voltage line connected to a second end of the memory element and a third power supply terminal, and a fourth transistor connected between the low voltage line and a fourth power supply terminal. The second and fourth transistors satisfy the condition: |Vth|<|VG−VB|+VF, where Vth is a threshold voltage thereof, VG is a voltage difference between a gate and a source or drain thereof, VB is a bias voltage applied to a body thereof, and VF is a minimum voltage at which a parasitic diode current flows.
According to one embodiment, a semiconductor device comprises a circuit board and a semiconductor package mounted on the circuit board. The semiconductor package comprises a semiconductor chip, a first connector on a bottom surface of the semiconductor package and electrically connected to the semiconductor chip, and a metal bump coupled to the first connector and electrically connected to a second connector on the circuit board. The first connector has a contact surface facing the second connector. The contact surface has a recessed portion into which the metal bump extends.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
According to one embodiment, a semiconductor device includes: a printed wiring substrate that includes a substrate, a wiring layer on the substrate, and a first insulating layer on the wiring layer. The wiring layer includes a connection terminal and a wiring electrically connected to the connection terminal. The first insulating layer includes an opening that exposes at least a portion of the connection terminal and at least a portion of the wiring, and at least one of a protrusion portion or a recess portion, provided along an edge of the opening, that overlaps the wiring. The semiconductor device includes a semiconductor chip mounted on the printed wiring substrate; a bonding wire that electrically connects the connection terminal and the semiconductor chip; and a second insulating layer that covers the semiconductor chip, the bonding wire, and the opening.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
According to one embodiment, a magnetic memory puts a first magnetic domain having a magnetization direction which is the same as or opposite to a magnetic domain of a first layer of a magnetic memory line, into the first layer, based on a value of data and the magnetization direction of the first layer. When receiving a first command, the magnetic memory puts a first additional magnetic domain and a second additional magnetic domain having a magnetization direction opposite to the first additional magnetic domain into the magnetic memory line. When receiving a second command, the magnetic memory read the first and second additional magnetic domains to determine the magnetization direction of the first magnetic domain.
G11C 19/08 - Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G06F 3/06 - Digital input from, or digital output to, record carriers
According to one embodiment, a pattern forming method is disclosed. The method includes forming a guide pattern, forming a block copolymer film that covers the guide pattern and includes first and second polymers, and forming a microphase-separation pattern including first portions of the first polymer and second portions of the second polymer which are alternately arranged by subjecting the block copolymer film to microphase separation. The method further includes measuring a position of the guide pattern, the first portions or the second portions by using a scanning probe microscope, determining whether a misalignment amount of the first portions with respect to the guide pattern is within a first range, based on the measured position of the first and the guide pattern, and removing the first portions, when the misalignment amount is within the first range.
According to one embodiment, a semiconductor storage device includes a memory cell and a memory cell connected to a word line, a first bit line BL connected to the memory cell, a second bit line BL connected to the memory cell, and a control circuit. The control circuit includes a first transistor provided between the first bit line and the node and including one end electrically connected to the node, and a second transistor provided between the second bit line and the node and including one end electrically connected to the node; the second transistor is provided adjacent to the first transistor; and the control circuit is configured to set one of the first transistor and the second transistor in an ON state while setting the other in an OFF state.
According to one embodiment, a semiconductor storage device includes: a substrate; a plurality of first gate electrodes arranged in a first direction intersecting with a substrate surface; a first semiconductor film extending in the first direction and facing the plurality of first gate electrodes; a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film; a second gate electrode disposed farther away from the substrate than the plurality of first gate electrodes; a second semiconductor film that extends in the first direction, faces the second gate electrode, and has, in the first direction, one end connected to the first semiconductor film; and a second gate insulating film provided between the second gate electrode and the second semiconductor film. The second gate electrode includes: a first portion; and a second portion provided between the first portion and the second semiconductor film, and facing the second semiconductor film. At least a portion of the second portion is provided closer to a side of the substrate than a surface of the first portion on the side of the substrate side in the first direction.
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11553 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
H01L 27/1158 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
71.
Semiconductor storage device and method for manufacturing semiconductor storage device
According to one embodiment, a semiconductor storage device includes: a first stair portion which descends in a second direction that is a direction away from a pillar, and has a plurality of steps; and a third stair portion which is provided to face the first stair portion, and ascends in the second direction, and has a plurality of steps. A distance from an upper end of an uppermost step surface of the first stair portion to an upper end of a lowermost step surface of the first stair portion at a position identical to the upper end in the third direction is longer than a distance from an upper end of an uppermost step surface of the third stair portion to an upper end of a lowermost step surface of the third stair portion at a position identical to the upper end in the third direction.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
72.
Image acquisition apparatus and image acquisition method
According to one embodiment, an image acquisition apparatus includes a light source, a stage on which an object to be observed is placed, a reflection mirror reflecting light from the light source and supplying reflected light to a surface of the object placed on the stage, an imaging optical system receiving an optical image from the surface of the object illuminated by the reflected light from the reflection mirror, and a detector detecting the optical image acquired by the imaging optical system. The reflection mirror includes a first portion reflecting light from the light source, and a second portion provided at a position opposite to the first portion with respect to a center of the reflection mirror and through which light from the surface of the object passes.
A storage device according to embodiments includes a first conductive layer; a second conductive layer; a resistance change element provided between the first conductive layer and the second conductive layer; and an intermediate layer provided in any one of a position between the resistance change element and the first conductive layer and a position between the resistance change element and the second conductive layer, the intermediate layer containing at least one element of silicon (Si) and germanium (Ge), tellurium (Te), and aluminum (Al).
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
74.
Semiconductor memory device in which a conductive line connected to a word line selected for programming is charged to a voltage larger than the program voltage
A semiconductor memory device includes a first memory transistor, a first wiring connected to a gate electrode of the first memory transistor, a connection transistor connected to the first wiring, and a second wiring connected to the connection transistor. In a first write operation for the first memory transistor, during a first time period, a voltage of the first wiring increases to a first voltage and a voltage of the second wiring increases to a second voltage larger than the first voltage, and during a second time period directly after the first time period and directly after the connection transistor is turned ON, the voltage of the first wiring increases to a third voltage larger than the first voltage and smaller than the second voltage, and the voltage of the second wiring decreases to a fourth voltage larger than the first voltage and smaller than the second voltage.
H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A memory controller that controls a nonvolatile memory in response to commands from a host, includes a normal transfer queue and a priority transfer queue, a transfer packet priority determination unit, a transfer queue selector, and a transfer packet selector. The transfer packet priority determination unit determines whether a transfer packet is a priority packet based on transmission information of the transfer packet. The transfer queue selector selects the priority transfer queue and stores the transfer packet in the priority transfer queue when the transfer packet is determined as the priority packet, and selects the normal transfer queue and stores the transfer packet in the normal transfer queue when the transfer packet is not determined as the priority packet. The transfer packet selector transfers to a host a priority packet stored in the priority transfer queue preferentially with respect to a normal packet stored in the normal transfer queue.
A memory system includes a first memory chip that includes a first temperature sensor, and a memory controller that includes a second temperature sensor. The memory controller is configured to: perform, at a first timing, a first temperature acquisition process including acquiring a first measured temperature using the first temperature sensor or the second temperature sensor; select one of the first temperature sensor and the second temperature sensor for a second temperature acquisition process based the first measured temperature; and perform, at a second timing later than the first timing, the second temperature acquisition process including acquiring a second measured temperature using the selected one of the first temperature sensor or the second temperature sensor.
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 29/52 - Protection of memory contents; Detection of errors in memory contents
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
A memory device includes a non-volatile first memory in which a conversion table is stored, a second memory, and a controller configured to control the first memory and the second memory, and including a cache control circuit. The cache control circuit is configured to set up a circular buffer with a write pointer, and store portions of the conversion table in the circular buffer. Each of the portions of the conversion table contain a plurality of logical address to physical address mappings, and each of the portions have a corresponding entry in a management table stored in the second memory, and each entry of the management table includes an address field for storing an address of the circular buffer used in locating the corresponding portion of the conversion table and a size field for storing a size of the corresponding portion.
A semiconductor memory device includes first wirings above a substrate and extending in a first direction, second wirings above the first wirings and extending in a second direction crossing the first direction, third wirings above the second wirings and extending in the first direction, memory cells between the first and second wirings and between the second and third wirings, a first multiplexer that extends in the second direction, is connected to the first wirings, and is provided in a first region which overlaps with the first, second, and third wirings in a third direction that crosses the first and second directions, and a second multiplexer that extends in the first direction, is connected to the second wirings, and is provided in a second region which overlaps with the first, second, and third wirings in the third direction.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 23/528 - Layout of the interconnection structure
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
A receiving device includes first, second, and third circuits, and a processing circuit. The first circuit is configured to calculate a phase difference between a first clock signal and a data signal, which is a signal modulated by pulse-amplitude modulation. The second circuit is configured to generate a second clock signal based on the first clock signal and the phase difference. Jitter is added to second clock signal. The third circuit is configured to demodulate the data signal by comparing an amplitude of each pulse of the data signal with a threshold value at a timing synchronized to the second clock signal added the jitter. The processing circuit is configured to count the number of errors in the demodulated data signal and then calibrate the threshold value based on the counted number of errors.
According to one embodiment, a semiconductor storage device includes a first wiring, a first resistance change element which is connected to the first wiring, a first nonlinear element which is connected to the first resistance change element, and a second wiring which is connected to the first nonlinear element. In a read operation for the first resistance change element, a voltage between the first wiring and the second wiring increases to a first voltage, and after the voltage between the first wiring and the second wiring increases to the first voltage, the voltage between the first wiring and the second wiring increases to a second voltage which is larger than the first voltage.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 17/14 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
A semiconductor memory device includes a first wiring, a first memory transistor connected to the first wiring, a first transistor connected between the first wiring and the first memory transistor, a second transistor connected between the first wiring and the first transistor, and second to fourth wirings respectively connected to gate electrodes of the first memory transistor, the first transistor, and the second transistor. From a first timing to a second timing, a voltage difference between the first wiring and the third wiring is maintained at a predetermined value, a voltage difference between the third wiring and the fourth wiring is maintained at a predetermined value, a voltage of the first wiring becomes larger than a voltage of the third wiring, and the voltage of the third wiring becomes larger than a voltage of the fourth wiring.
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11565 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the top-view layout
H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
A semiconductor storage device includes a source line, a first selection line, word lines, a dummy word line, and a second selection line. A first pillar having a first semiconductor layer extends through the first selection line, the word lines, and the first dummy word line and is connected to the source line. Memory cells are at intersections of the word lines and the first pillar. A conductive layer is on the first semiconductor layer and extends into the first dummy word line. A second pillar with a second semiconductor layer extends through the second selection line and contacts the conductive layer. A bit line is electrically connected to the second semiconductor layer. A control circuit is configured to apply voltages to the various lines during an erasing of the memory cells. A voltage between a source line voltage and a world line voltage is applied to dummy word line.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/08 - Address circuits; Decoders; Word-line control circuits
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 16/26 - Sensing or reading circuits; Data output circuits
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
84.
Semiconductor storage device and method of manufacturing semiconductor storage device
According to one embodiment, a semiconductor storage device includes a stacked body, a first semiconductor layer extending in the stacked body, a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer, a second conductor layer disposed above the stacked body, a second semiconductor layer extending through the second conductor layer, a third conductor layer disposed between the second semiconductor layer and the second conductor layer, a first insulator layer disposed above the third conductor layer, and a second insulator layer including a first portion disposed between the second semiconductor layer and the third conductor layer and a second portion disposed between the second semiconductor layer and the first insulator layer. A diameter of the second insulator layer is larger in the second portion than in the first portion.
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
85.
Semiconductor storage device with columnar body having impurity containing channel film
A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked in a first direction. The columnar body extends through the stacked body in the first direction and includes a core portion, a channel film, a tunnel oxide film, and a charge storage film in this order from a center portion thereof. The channel film has a first region in contact with the core portion and a second region in contact with the tunnel oxide film. The first region is a semiconductor doped with impurities. The second region is a semiconductor. A concentration of the impurities in the second region is lower than that in the first region.
H01L 27/11524 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/1157 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
According to one embodiment, a storage device includes a non-volatile memory, an interface circuit, a first control circuit, a wireless transmitting and receiving circuit, and a second control circuit. The interface circuit is electrically connected to the host device and is capable of communicating the host device. The first control circuit performs control of writing write data received from the host device via the interface circuit into the non-volatile memory. The wireless transmitting and receiving circuit is capable of wirelessly communicating with a wireless device. The second control circuit determines whether or not the write data include a predetermined type of data based on measurement data of the write data, and stops wireless communication performed by the wireless transmitting and receiving circuit if it is determined that the write data include the predetermined type of data.
A semiconductor storage device includes a first conductive layer, a second conductive layer, and a first chalcogen layer provided therebetween. A third conductive layer and a fourth conductive layer have a second chalcogen layer provided therebetween. The second chalcogen layer contains tellurium (Te). When a minimum value and a maximum value of a composition ratio of tellurium in the second chalcogen layer observed along the first direction are a first minimum value and a first maximum value, respectively, the first minimum value is observed at a position closer to the third conductive layer than a center position in the first direction of the second chalcogen layer, and the first maximum value is observed at a position closer to the fourth conductive layer than the center position in the first direction of the second chalcogen layer.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
88.
Semiconductor device, substrate for semiconductor device and method of manufacturing the semiconductor device
A semiconductor device includes a device layer having a semiconductor element and a wiring layer, a first structure, a second structure at an outer periphery of the first structure and having a thickness smaller than that of the first structure, and a conductive layer that covers the first structure and the second structure. The first structure comprises a first substrate having the device layer formed on a first surface thereof and a through hole formed through a second surface thereof that is opposite to the first surface to reach the device layer, and an inner portion of a second substrate facing the first surface and bonded to the first surface by a first adhesive layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
C25D 5/02 - Electroplating of selected surface areas
According to one embodiment, an inspection device includes a stage on which a substrate having a protrusion portion on a surface thereof is mountable. A ring member presses an outer periphery of the substrate on the stage. A liquid supply unit supplies a liquid on the surface of the substrate from the surface thereof to a first height. An imaging unit captures an image of a surface of the liquid and the protrusion portion from above the surface of the substrate. An arithmetic operation unit determines a size of an exposed portion of the protrusion portion which is exposed from the surface of the liquid by using the image obtained from the imaging unit, and determines a height of the protrusion portion on the basis of the size of the exposed portion.
G06T 7/62 - Analysis of geometric attributes of area, perimeter, diameter or volume
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A clock recovery circuit includes a multi-phase sampling circuit, a phase comparison circuit, a recovery clock generation circuit, and a phase shifter. The multi-phase sampling circuit includes edge samplers and data samplers. A data signal is input to each of the edge samplers and each of the data samplers. The phase comparison circuit is disposed at an output side of the multi-phase sampling circuit. The recovery clock generation circuit is configured to output multi-phase clock signals. The phase shifter is disposed between the recovery clock generation circuit and the multi-phase sampling circuit and configured to generate a plurality of clock signals to be supplied to the multi-phase sampling circuit by shifting a phase of a first one of the multi-phase clock signals output from the recovery clock generation circuit by a shift amount different from a shift amount of a second one of the multi-phase clock signals.
H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop
H03L 7/091 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H04L 7/08 - Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
H03L 7/14 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
A semiconductor storage device includes a first wire extending in a first direction from a first end to a second end, a plurality of second wires spaced from each other in the first direction and extending in a second direction intersecting the first direction, and a plurality of memory films spaced from each other along the first wire from the first end to the second end and respectively being between the first wire and a second wire of the plurality of second wires. A first memory film of the plurality is at position along the first wire that is between a position of a second memory film and the first end. A contact area between the second memory film and the first wire is greater than a contact area between the first memory film and the first wire.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
According to one embodiment, in a first differential amplifier circuit of a semiconductor device, a first transistor receives an input signal at the gate. A second transistor forms a differential pair with the first transistor. The second transistor receives a reference signal at the gate. A third transistor is connected in series with the first transistor. A fourth transistor is connected in series with the second transistor. A fifth transistor is disposed on the output side. The fifth transistor forms a first current mirror circuit with the fourth transistor. A sixth transistor is connected to the drain of the second transistor in parallel with the fourth transistor. The sixth transistor forms a second current mirror circuit with the fifth transistor. A first discharge circuit is connected to the source of the sixth transistor.
H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
A semiconductor device inspection device includes a semiconductor device stage, a sound wave generator, a laser emitter, a photoreceiver, and a processing circuit. The sound wave generator is configured to generate a sound wave having a natural frequency of a bonding wire included in a semiconductor device placed on the semiconductor device stage. The laser emitter is configured to direct laser toward the bonding wire while the sound wave generator generates the sound wave. The photoreceiver is configured to receive the laser reflected by the bonding wire and output a signal corresponding to the received laser. The processing circuit is configured to detect a bonding failure of the bonding wire based on the signal output by the photoreceiver.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
A method is for verifying a logic operation of a target circuit including a circuit module configured to dynamically switch between synchronous transfer and asynchronous transfer. The method includes setting a time window for detecting an erroneous change of a logical value of a data signal. The time window ranges a first time period forward and a second time period backward from an edge of a clock signal and excludes a certain sub range. The method includes, during a simulation, determining whether or not the erroneous change of the logical value of the data signal is detected during the set time window. The method includes, upon detection of the erroneous change, inserting an erroneous sample into a test vector for the simulation, and upon non detection of the erroneous change, continuing the simulation without inserting the erroneous sample.
According to one embodiment, a method of manufacturing a semiconductor device includes: forming a semiconductor feature on a first surface of a substrate; forming a first insulating film on the semiconductor feature; forming a first wiring layer on the first insulating film; forming a second insulating film on the first wiring layer; forming a second wiring layer on the second insulating film; forming a first electrode on the second wiring layer; providing a protective adhesive that covers the first electrode and the second wiring layer; bonding a supporting substrate onto the protective adhesive; polishing a second surface of the substrate opposite to the first surface; removing the supporting substrate from the protective adhesive; and removing at least a portion of the protective adhesive to expose the first electrode.
A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
According to one embodiment, a memory system receives from a host read commands each designating both of a block address of a read target block and a read target storage location in the read target block, and executes a data read operation in accordance with each of the received read commands. In response to receiving from the host a first command to transition a first block to which data is already written to a reusable state of being reusable as a new write destination block, the memory system determine whether an incomplete read command designating a block address of the first block exists or not. In a case where the incomplete read command exists, the memory system executes the first command after execution of the incomplete read command is completed.
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
99.
Nonvolatile memory system and method for controlling write and read operations in the nonvolatile memory by a host
According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.
A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
patents
