Abstract

The invention concerns a process for testing an integrated circuit including a collection stage for a set of points (Wk,i,j) of a physical size while the integrated circuit executes a multiplication. The process includes steps consisting in dividing the set of points into a plurality of subsets of points (Ci,j), calculating an estimate (HWi,j) of the value of the physical size for each subset (Ci,j), and applying a transverse horizontal statistical treatment step to the subsets of lateral points (Ci,j) using the estimates of the value of the physical size to validate the hypothesis about variables manipulated by the integrated circuit.

IPC Classes  ?

• G01R 31/319 - Tester hardware, i.e. output processing circuits
• G01R 31/3173 - Marginal testing
• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips

Abstract

The invention relates to an integrated circuit (ClC2) comprising a multiplication function (SMT2) that is configured to execute a multiplication operation of two binary words x (a) and y (a, m) involving a plurality of basic multiplication steps of components xi (ai) of word x by components yj (aj, mj) of word y. According to the invention, the multiplication function of the integrated circuit is configured to execute two successive multiplications by modifying, in a random or pseudo-random manner, the order in which the basic multiplication steps of components xi by components yj are executed.

IPC Classes  ?

• G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
• G06F 7/523 - Multiplying only