Commissariat à l'énergie atomique et aux energies alternatives

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1.

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

      
Application Number 18538379
Status Pending
Filing Date 2023-12-13
First Publication Date 2024-06-13
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Acosta Alba, Pablo
  • Reboh, Shay

Abstract

A method for manufacturing a semiconductor device including a first semiconductor zone optimised for electron conduction and a second semiconductor zone optimised for hole conduction, the method including providing a multilayer structure including a substrate and a silicon-germanium layer disposed on the substrate; defining in the multilayer structure a first region for containing the first semiconductor zone and a second region for containing the second semiconductor zone; subjecting the multilayer structure to laser annealing so as to modify a portion of the multilayer structure located in the first region, the portion including prior to laser annealing a part of the silicon-germanium layer, the portion including after the laser annealing a germanium-depleted part and a germanium-enriched part disposed on the germanium-depleted part, and etching the germanium-enriched part so as to expose the germanium-depleted part.

IPC Classes  ?

  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group

2.

POWER SUPPLY SYSTEM SUPPLYING AN ELECTRICAL LOAD VIA A POLYPHASE VOLTAGE AND AN AUXILIARY NETWORK VIA A HOMOPOLAR COMPONENT OF THE VOLTAGE, AND RELATED ELECTRICAL INSTALLATION

      
Application Number 18534493
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-06-13
Owner Commissariat à l'énergie atomique et aux énergies alternatives (France)
Inventor
  • Despesse, Ghislain
  • Blatter, Jérôme

Abstract

A power supply system includes a main power supply system generating, from a main network, at least one polyphase voltage for supplying at least one load. Each load includes a winding for each phase. The windings are connected in star connection at a midpoint. An auxiliary power supply system of an auxiliary network includes a first power supply terminal and a second power supply terminal. The main power supply system is configured to generate the at least one polyphase voltage with at least one non-zero homopolar component. The auxiliary power supply system includes a module for connecting the first power supply terminal to the midpoint and the second power supply terminal to a reference point, for supplying the auxiliary network via at least one homopolar component coming from the midpoint.

IPC Classes  ?

  • H02P 27/06 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
  • B60L 15/00 - Methods, circuits or devices for controlling the propulsion of electrically-propelled vehicles, e.g. their traction-motor speed, to achieve a desired performance; Adaptation of control equipment on electrically-propelled vehicles for remote actuation from a stationary place, from alternative parts of the vehicle or from alternative vehicles of the same vehicle train
  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02P 25/022 - Synchronous motors

3.

METHOD FOR MAKING A WITH BULK ACOUSTIC WAVE FILTER

      
Application Number 18538430
Status Pending
Filing Date 2023-12-13
First Publication Date 2024-06-13
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Reinhardt, Alexandre
  • Bousquet, Marie

Abstract

A method for making a bandpass filter including a first and second bulk acoustic wave resonators, the resonant frequency of the second resonator being offset from that of the first resonator by a predetermined offset, the method including providing a piezoelectric on insulator substrate, forming a lower electrode of the first resonator and a lower electrode of the second resonator, assembling by bonding the donor substrate to a receiver substrate, removing the donor substrate with a barrier on the piezoelectric layer, forming an upper electrode of the first resonator and an upper electrode, forming the lower electrodes being preceded by forming a mass overload pattern at the second zone, and/or forming the upper electrodes being preceded by forming a mass overload pattern at the second zone, the total thickness of the mass overload pattern or patterns being chosen to offset the resonant frequency of the second resonator by the offset.

IPC Classes  ?

  • H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
  • H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
  • H03H 9/56 - Monolithic crystal filters

4.

CURRENT-ASSISTED PHOTONIC DEMODULATOR INCLUDING DOPED MODULATION AND COLLECTION REGIONS ARRANGED VERTICALLY AND LOCATED IN A COMPRESSIVE ZONE

      
Application Number 18535194
Status Pending
Filing Date 2023-12-11
First Publication Date 2024-06-13
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Aliane, Abdelkader
  • Kaya, Hacile

Abstract

A current-assisted photonic demodulator, including a detection portion produced based on germanium, containing at least two doped modulation regions and at least one doped collection region, surrounded by a peripheral lateral portion generating in the detection portion horizontal tensile and vertical compressive mechanical stress. The doped collection region(s) are disposed according to a vertical arrangement in relation to the doped modulation regions.

IPC Classes  ?

  • G02B 6/122 - Basic optical elements, e.g. light-guiding paths
  • G02B 6/134 - Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

5.

STRAIN GAUGE

      
Application Number 18528444
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-06-13
Owner Commissariat à I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Jourdan, Guillaume
  • Gely, Marc

Abstract

A device including a substrate; a first layer resting on the substrate, the first layer including a first portion and a second portion mobile with respect to each other; and a ring-shaped optical resonator defined in a second layer. The resonator includes a first portion fixed to a first anchor pad connected to the first portion of the first layer and a second portion fixed to a second anchor pad connected to the second portion of the first layer.

IPC Classes  ?

  • G01L 1/24 - Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis
  • G01D 5/26 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using optical means, i.e. using infrared, visible or ultraviolet light

6.

PHOTONIC DEVICE MECHANICALLY ISOLATED FROM A SUBSTRATE

      
Application Number 18528485
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-06-13
Owner Commissariat à I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Jourdan, Guillaume
  • Gely, Marc

Abstract

A photonic device including a substrate and a structure. The structure includes a support, an optical resonator fixed to the support, and a portion of a waveguide optically coupled to the resonator and fixed to the support. The structure is suspended above the substrate. The portion of the waveguide and the resonator are arranged on a same side of the support. The support is a first portion of a layer. A second portion of the layer is fixed to the substrate. The support is mechanically coupled to the second portion of the layer.

IPC Classes  ?

  • G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
  • G02B 6/35 - Optical coupling means having switching means

7.

METHOD OF MANUFACTURING AN OPTOELECTRONIC DEVICE COMPRISING A LED AND A PHOTODIODE

      
Application Number 18530054
Status Pending
Filing Date 2023-12-05
First Publication Date 2024-06-13
Owner Commissariat à I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Simon, Julia
  • Rol, Fabian
  • Le Maitre, Patrick

Abstract

A method of manufacturing an optoelectronic device including at least one LED and at least one photodiode, including the following steps: a) forming a semiconductor support stack including at least one doped semiconductor layer; b) simultaneously forming, during a common epitaxy step, an active emission semiconductor stack of the LED and an active reception semiconductor stack of the photodiode; c) forming trenches delimiting first and second support pads; and d) porosifying the doped semiconductor layer in the first support pad without porosifying this layer in the second support pad, or porosifying the doped semiconductor layer in the second support pad without porosifying this layer in the first support pad.

IPC Classes  ?

  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission

8.

REFLECTOR DEVICE FOR EMITTING A PLURALITY OF REFLECTED BEAMS FROM A SINGLE MAIN LIGHT BEAM

      
Application Number 18554916
Status Pending
Filing Date 2022-04-08
First Publication Date 2024-06-13
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Mollard, Laurent
  • Frey, Laurent
  • Gardien, François
  • Hue, Jean

Abstract

A reflector device that includes a support, a light source arranged to emit a principal light beam, N mirrors, partially transparent, assembled on the support, and delimited by a partially reflective front face, and a rear face, the mirrors are arranged from a first position to an Nth position, so that the principal light beam is incident on the front face of the mirror in the first position, and interacts successively, in the order, with each mirror to form a beam reflected by the front face and a beam transmitted by the rear face, the beam reflected by the front face of a mirror in a position i resulting from the reflection of the beam transmitted by the rear face of the mirror in position i−1.

IPC Classes  ?

  • G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
  • G02B 27/14 - Beam splitting or combining systems operating by reflection only

9.

VARIABLE RESONANT FREQUENCY ELECTROMECHANICAL DEVICE AND ASSOCIATED ACOUSTIC DEVICE

      
Application Number 18529717
Status Pending
Filing Date 2023-12-05
First Publication Date 2024-06-13
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Liechti, Romain
  • Casset, Fabrice

Abstract

An electromechanical device includes at least one movable mechanical structure including at least one movable mechanical element; for each movable mechanical element of each movable mechanical structure a first piezoelectric layer, the first layer being disposed on a first part of the movable element so as to be able to actuate the movable mechanical element, and a second piezoelectric layer, the second layer being disposed on a second part of the movable element, distinct from the first part, so as to be able to convert mechanical energy associated with the movement of the movable mechanical element into electric energy, the layer forming a capacitance; the device further including an electrical circuit connected to the second piezoelectric layer in parallel with the capacitance formed by the layer and including an adjustable capacitance which can assume a negative value.

IPC Classes  ?

  • H04R 17/10 - Resonant transducers, i.e. adapted to produce maximum output at a predetermined frequency
  • H04R 17/00 - Piezoelectric transducers; Electrostrictive transducers

10.

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

      
Application Number 18538339
Status Pending
Filing Date 2023-12-13
First Publication Date 2024-06-13
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Acosta Alba, Pablo
  • Reboh, Shay

Abstract

A method for manufacturing a semiconductor device including a first semiconductor zone optimised for electron conduction and a second semiconductor zone optimised for hole conduction, the method including providing a multilayer structure including a substrate and a silicon-germanium layer disposed on the substrate; defining in the multilayer structure a first region for containing the first semiconductor zone and a second region for containing the second semiconductor zone, and subjecting the multilayer structure to laser annealing so as to modify a portion of the multilayer structure located in the second region, the portion including prior to laser annealing a part of the silicon-germanium layer, the portion having after laser annealing a germanium concentration gradient with a germanium concentration which increases towards an upper face of the portion.

IPC Classes  ?

  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
  • H01L 21/762 - Dielectric regions

11.

METHOD AND DEVICE FOR TRANSPORTING POWDERS

      
Application Number 18553506
Status Pending
Filing Date 2022-03-30
First Publication Date 2024-06-13
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Brothier, Meryl
  • Vaudez, Stéphane
  • Robisson, Anne-Charlotte
  • Li, King-Wo

Abstract

A method for transporting non-flowable powders includes the following steps: mixing and suspending powders and carbon dioxide in the solid form, with the introduction of a cryogenic fluid, to obtain a cryogenic suspension; setting the cryogenic suspension in motion to enable transport thereof, controlling the motion of the cryogenic suspension according to one or more parameter(s) related to the first mixing and suspending step.

IPC Classes  ?

  • B65G 53/24 - Gas suction systems
  • B65G 53/30 - Conveying materials in bulk through pipes or tubes by liquid pressure
  • B65G 53/52 - Adaptations of pipes or tubes

12.

METHOD FOR MANUFACTURING A SIGE CHANNEL FIELD EFFECT TRANSISTOR

      
Application Number 18538292
Status Pending
Filing Date 2023-12-13
First Publication Date 2024-06-13
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Acosta Alba, Pablo
  • Fenouillet-Beranger, Claire
  • Gassilloud, Rémy
  • Kerdiles, Sébastien
  • Reboh, Shay

Abstract

A method for manufacturing a field effect transistor including a silicon-germanium active layer and a gate oxide layer disposed on the active layer, the method including providing a stack including a substrate and a silicon-germanium first layer disposed on the substrate; forming the gate oxide layer on the stack; subjecting the stack to laser annealing so as to melt a region of the stack, the region including at least one part of the first layer, and recrystallising the molten region of the stack to obtain the silicon-germanium active layer in contact with the gate oxide layer, the active layer having a germanium concentration gradient.

IPC Classes  ?

  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/66 - Types of semiconductor device

13.

INERTIAL SENSOR ARCHITECTURE WITH BALANCED SENSE MODE AND IMPROVED IMMUNITY TO QUADRATURE EFFECTS

      
Application Number 18530792
Status Pending
Filing Date 2023-12-06
First Publication Date 2024-06-13
Owner
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
  • POLITECNICO DI MILANO (Italy)
Inventor
  • Buffoli, Andrea
  • Langfelder, Giacomo
  • Zega, Valentina
  • Verdot, Thierry

Abstract

An inertial sensor including a substrate, sense frames, drive frames configured to put into motion the sense frames, and a sense lever pivotably mounted around a rotation axis. The sense frames, drive frames and sense lever are connected to each other in such a way that when the inertial sensor is subjected to a rotational movement around the rotation axis, the first sense frame, the second sense frame and the sense lever respectively feature a first tilt θ1 a second tilt θ2 and a lever tilt θs relatively to the device plane, and both θ1/θs and θ2/θs are lower than 0.1. The inertial sensor features strain gauges that get stressed when the lever rotates due to the motion of the sense frames.

IPC Classes  ?

  • G01C 19/574 - Structural details or topology the devices having two sensing masses in anti-phase motion

14.

UNINTERRUPTIBLE POWER SUPPLY CIRCUIT

      
Application Number 18533987
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-06-13
Owner COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Lanneluc, Charley
  • Perichon, Pierre
  • Sterna, Léo

Abstract

An uninterruptible power supply circuit includes an inverter circuit configured to be connected to a first AC power grid, the power supply circuit moreover being configured to adopt a first configuration for supplying power to the first AC power grid from a second AC power grid, wherein first configuration a power factor correction circuit is configured to be connected to the second AC power grid so as to deliver a DC voltage to the inverter circuit, the power factor correction circuit comprising an inductor, and a first switch branch pertaining to the power factor correction circuit and the inverter circuit; and a second configuration for supplying power to the first AC power grid from a DC voltage source, wherein second configuration a DC-DC converter circuit is configured to be connected to the DC voltage source so as to deliver a DC voltage to the inverter circuit, the inductor moreover pertaining to the DC-DC converter circuit.

IPC Classes  ?

  • H02J 9/06 - Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over
  • H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
  • H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

15.

METHOD OF MANUFACTURING A MULTILAYER STRUCTURE

      
Application Number 18287148
Status Pending
Filing Date 2022-04-12
First Publication Date 2024-06-13
Owner
  • COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
  • SOITEC (France)
Inventor
  • Roumanie, Marilyne
  • Navone, Christelle
  • Quenard, Sébastien
  • Landru, Didier
  • Veytizou, Christelle

Abstract

A method for producing a multilayer structure includes the following steps: a) providing a first substrate, b) depositing a thick layer of a precursor formulation including a preceramic polymer filled with inorganic particles on the first substrate, c) providing a second substrate, d) adhesively bonding the thick layer and the second substrate, e) thinning the first substrate or the second substrate so as to obtain an active layer, f) applying a pyrolysis heat treatment so as to ceramize the preceramic polymer of the thick layer and to obtain a ceramic matrix composite material, the filler content and the nature of the inorganic particles being chosen so that the thick layer has a coefficient of thermal expansion which differs, at most, by 15% from that of the first substrate and from that of the second substrate.

IPC Classes  ?

  • B32B 37/12 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives
  • B32B 7/12 - Interconnection of layers using interposed adhesives or interposed materials with bonding properties
  • B32B 37/06 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the heating method
  • B32B 37/10 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the pressing technique, e.g. using direct action of vacuum or fluid pressure
  • B32B 38/00 - Ancillary operations in connection with laminating processes
  • B32B 38/08 - Impregnating

16.

POWER CONVERTER

      
Application Number 18521095
Status Pending
Filing Date 2023-11-28
First Publication Date 2024-06-06
Owner Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
Inventor
  • Pillonnet, Gaël
  • Oukassi, Sami
  • Perez, Emeric
  • Moursy, Yasser

Abstract

The present description concerns a DC-DC converter (100) comprising a first node (N1) and a second node (N2) intended to receive a DC voltage to be converted; a third node (N3) intended to deliver a DC voltage referenced to the second node; at least one first solid electrolyte capacitor (C1); at least one first switching cell (420) formed of four switches (421, 422, 431, 432) respectively coupling a first electrode of the capacitor to the first node and to the third node and a second electrode of the capacitor to the second node and to the third node; the switching frequency of the switches being adapted to the power required at the output and to selecting an operating mode of the first capacitor from among an electrostatic operating mode and an ionic operating mode.

IPC Classes  ?

  • H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
  • H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

17.

METHOD FOR MANUFACTURING, BY DIFFERENTIATED ELECTROCHEMICAL POROSIFICATION, A GROWTH SUBSTRATE INCLUDING MESAS HAVING VARIOUS POROSIFICATION LEVELS

      
Application Number 18522975
Status Pending
Filing Date 2023-11-29
First Publication Date 2024-06-06
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Dupre, Ludovic
  • Dussaigne, Amélie
  • Pernel, Carole
  • Rol, Fabian

Abstract

A method for manufacturing a growth substrate, including producing mesas based on GaN having various porosification levels, implementing differentiated steps of electrochemical porosification, non-photoassisted and photoassisted, of various portions of the mesas.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

18.

METHOD FOR POROSIFYING (Al,In,Ga)N/(Al,In,Ga)N MESAS

      
Application Number 18524628
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-06-06
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Audibert, Margaux
  • Pernel, Carole
  • Levy, François
  • Medjahed, Ilyes

Abstract

Method for porosifying mesas comprising the following steps: providing a structure (100) comprising a substrate (110) covered with (Al,In,Ga)N/(Al,In,Ga)N mesas (120), the substrate (110) comprising a support layer (114), a first layer of non-doped GaN (111) and a second layer of doped GaN (112), the mesas (120) comprising a third layer of heavily doped (Al,In,Ga)N(123) and a fourth layer of non-doped or lightly doped (Al,In,Ga)N(124), a part (112b) of the second layer (112) of doped GaN being extended in the mesas (120) or a part (123a) of the third layer (123) of heavily doped (Al,In,Ga)N being extended in the base substrate (110), immersing the structure (100) and a counter-electrode in an electrolytic solution, applying a voltage or a current between the structure (100) and the counter-electrode so as to porosify the third layer (123) of heavily doped (Al,In,Ga)N of the mesas (120).

IPC Classes  ?

  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/14 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
  • H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

19.

OPTICAL SYSTEM COMPRISING A PHOTOELECTRIC TRANSDUCER COUPLED TO A WAVEGUIDE, AND MANUFACTURING METHOD THEREFOR

      
Application Number 18529296
Status Pending
Filing Date 2023-12-05
First Publication Date 2024-06-06
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Michit, Nicolas
  • Le Maitre, Patrick

Abstract

An optical system includes a substrate and, being formed on the substrate, a reflective structure including a first inner reflection face with a parabolic profile, a second inner planar reflection face and a third inner planar reflection face, a photoelectric transducer including an active region configured to emit light waves or configured to receive light waves and positioned in the reflective structure, at a part of the foci, the material of the reflective structure being chosen to be transparent to the light waves, a waveguide arranged so that its longitudinal axis is parallel to the optical axes and its proximal end is adjoining the reflective structure between the second and third reflection faces and at the active region.

IPC Classes  ?

  • G02B 6/42 - Coupling light guides with opto-electronic elements

20.

SWITCH BASED ON PHASE-CHANGE MATERIAL

      
Application Number 18193230
Status Pending
Filing Date 2023-03-30
First Publication Date 2024-06-06
Owner
  • STMicroelectronics (Crolles 2) SAS (France)
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Cathelin, Philippe
  • Gianesello, Frederic
  • Fleury, Alain
  • Monfray, Stephane
  • Reig, Bruno
  • Puyal, Vincent

Abstract

The present description concerns a switch based on a phase-change material comprising: first, second, and third electrodes; a first region of said phase-change material coupling the first and second electrodes; and —a second region of said phase-change material coupling the second and third electrodes.

IPC Classes  ?

  • H01H 37/34 - Means for transmitting heat thereto, e.g. capsule remote from contact member
  • H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10N 70/20 - Multistable switching devices, e.g. memristors

21.

CARBONIC ANHYDRASE 1 (CA1) INHIBITORS FOR THE TREATMENT OR PREVENTION OF MYELOPROLIFERATIVE DISORDERS AND OTHER HEMATOPOIETIC MALIGNANCIES, AND AS BIOMARKER OF MYELOPROLIFERATIVE DISORDERS AND OTHER HEMATOPOIETIC MALIGNANCIES

      
Application Number 18552148
Status Pending
Filing Date 2022-03-25
First Publication Date 2024-06-06
Owner
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
  • INSERM (INSTITUT NATIONAL DE LA SANTE ET DE LA RECHERCHE MEDICALE) (France)
  • UNIVERSITÉ PARIS CITÉ (France)
  • UNIVERSITE PARIS-SACLAY (France)
Inventor
  • Romeo, Paul-Henri
  • Lewandowski, Daniel
  • Barroca, Vilma
  • Murakami, Shohei

Abstract

A method of treatment or prevention of myeloproliferative disorders and other hematopoietic malignancies is described. A carbonic Anhydrase 1 (CA1) inhibitor is used in a method for treating or preventing a myeloproliferative disorder, an acute myeloid leukemia (AML) and/or a primary or secondary myelofibrosis. The carbonic Anhydrase 1 is also used as a biomarker for myeloproliferative disorders and other hematopoietic malignancies, and as a biomarker of the efficacy of compounds for treating or preventing these conditions.

IPC Classes  ?

  • A61K 31/635 - Compounds containing para-N-benzene- sulfonyl-N-groups, e.g. sulfanilamide, p-nitrobenzenesulfonohydrazide having a heterocyclic ring, e.g. sulfadiazine
  • A61K 31/433 - Thiadiazoles
  • A61P 35/02 - Antineoplastic agents specific for leukemia
  • G01N 33/574 - Immunoassay; Biospecific binding assay; Materials therefor for cancer

22.

Method for dissolving a positive electrode material

      
Application Number 18553250
Status Pending
Filing Date 2022-03-28
First Publication Date 2024-06-06
Owner
  • COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
  • ORANO (France)
Inventor Billy, Emmanuel

Abstract

A method for dissolving a positive electrode material of a battery including a step during which the positive electrode material, comprising lithium and optionally cobalt and/or nickel, is submerged in an acid solution having a pH between 0 and 4, the acid solution containing either manganese ions or hydrogen peroxide, by means of which the lithium and optionally the cobalt and/or nickel is dissolved, and the manganese ions are selectively precipitated in the form of manganese oxyhydroxide.

IPC Classes  ?

  • C22B 47/00 - Obtaining manganese
  • C01G 45/02 - Oxides; Hydroxides
  • C22B 3/00 - Extraction of metal compounds from ores or concentrates by wet processes
  • C22B 3/08 - Sulfuric acid
  • C22B 3/22 - Treatment or purification of solutions, e.g. obtained by leaching by physical processes, e.g. by filtration, by magnetic means
  • C22B 3/44 - Treatment or purification of solutions, e.g. obtained by leaching by chemical processes
  • C22B 7/00 - Working-up raw materials other than ores, e.g. scrap, to produce non-ferrous metals or compounds thereof
  • C22B 21/00 - Obtaining aluminium
  • C22B 26/12 - Obtaining lithium
  • H01M 10/54 - Reclaiming serviceable parts of waste accumulators

23.

LAYER TRANSFER PROCESS

      
Application Number 18061839
Status Pending
Filing Date 2022-12-05
First Publication Date 2024-06-06
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Dupont, Florian
  • Rodriguez, Guillaume

Abstract

A method for transferring a layer of interest from a donor substrate to a receiver substrate includes providing the donor substrate made of a transparent material at a wavelength λ, forming at least one sacrificial buffer layer made of an absorbent sacrificial material at the wavelength λ, on the donor substrate, forming the layer of interest on the at least one sacrificial buffer layer, and bonding the layer of interest on the receiver substrate. The at least one sacrificial buffer layer is illuminated by a laser at the wavelength λ through the donor substrate so as to remove the at least one sacrificial buffer layer to separate the layer of interest from the donor substrate.

IPC Classes  ?

  • H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
  • B32B 37/00 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
  • B32B 37/24 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer not being coherent before laminating, e.g. made up from granular material sprinkled onto a substrate
  • C30B 23/02 - Epitaxial-layer growth
  • C30B 23/06 - Heating of the deposition chamber, the substrate, or the materials to be evaporated
  • C30B 29/30 - Niobates; Vanadates; Tantalates
  • H10N 30/853 - Ceramic compositions

24.

METHOD FOR LOCATING A NAVIGATION UNIT

      
Application Number 18328017
Status Pending
Filing Date 2023-06-02
First Publication Date 2024-06-06
Owner Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
Inventor
  • Villien, Christophe
  • Combettes, Christophe

Abstract

A method includes establishing, for a given time, measurement biases allowing an error affecting raw measurements of pseudoranges separating a navigation unit from at least three beacons to be decreased, and estimating an external position of the navigation unit at the given time based on: beacon positions, corrected pseudorange measurements computed for the given time using established measurement biases, and a preceding external position of the navigation unit estimated for a time preceding the given time. The measurement biases are established without taking into account the external position of the navigation unit.

IPC Classes  ?

  • G01S 5/14 - Determining absolute distances from a plurality of spaced points of known location
  • G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinations; Position-fixing by co-ordinating two or more distance determinations using radio waves

25.

VISIBLE AND INFRARED IMAGE SENSOR

      
Application Number 18520191
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-06-06
Owner Commissariat à I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor Becker, Sébastien

Abstract

A visible and infrared image sensor, including: a first active layer for detecting visible radiation, in which a plurality of visible detection pixels are defined; and superimposed on the first active layer, a second active layer for detecting infrared radiation, in which a plurality of infrared detection pixels are defined, the sensor further including, on the side of the face of the second active layer opposite the first active layer, a control integrated circuit superimposed on the first and second active layers, wherein the sensor includes isolation trenches extending vertically through at least part of the thickness of the second active layer, and laterally delimiting in the second active layer islands or mesas forming the infrared detection pixels.

IPC Classes  ?

26.

DEVICE FOR ACQUIRING A 2D IMAGE AND A DEPTH IMAGE OF A SCENE

      
Application Number 18526011
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-06-06
Owner Commissariat à I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Vaillant, Jérôme
  • Baylet, Jacques

Abstract

A method of manufacturing a device for acquiring a 2D image and a depth image, the method comprising the following steps: a) forming, on a first face of a first support semiconductor substrate, a first sensor comprising a plurality of depth pixels; b) forming, in the first support substrate, on the side of a second face of the first substrate opposite the first face, at least one optical concentrator; c) forming, in and on a second semiconductor substrate, a second sensor comprising a plurality of 2D image pixels; and d) placing the second sensor right next the first support substrate on the side of the second face of the first support substrate.

IPC Classes  ?

  • H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L 27/146 - Imager structures

27.

COLOUR AND TIME-OF-FLIGHT PIXEL PATTERN FOR AN IMAGE SENSOR

      
Application Number 18281944
Status Pending
Filing Date 2022-03-07
First Publication Date 2024-06-06
Owner Commissariat à l'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Jamin, Clémence
  • Vaillant, Jérôme
  • Rochas, Alexis
  • Cazaux, Yvon

Abstract

An image sensor including a plurality of pixels divided into elementary groups, each elementary group including a plurality of adjacent pixels arranged in a matrix, in rows and columns, each elementary group including first pixels, second and third visible image pixels sensitive in different wavelength ranges and fourth depth image pixels, wherein each row of each elementary group includes at least a fourth pixel.

IPC Classes  ?

  • H04N 23/84 - Camera processing pipelines; Components thereof for processing colour signals
  • H04N 25/11 - Arrangement of colour filter arrays [CFA]; Filter mosaics

28.

METHOD FOR GENERATING MULTI-RAY SPIN-EXCITATION SEQUENCES AND APPLICATION THEREOF TO MAGNETIC RESONANCE IMAGING

      
Application Number 18277735
Status Pending
Filing Date 2022-03-11
First Publication Date 2024-06-06
Owner COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Gras, Vincent
  • Mauconduit, Franck
  • Boulant, Nicolas

Abstract

A method for determining a global and regular parameterization for a family of spin-excitation pulse sequences in magnetic resonance imaging, with each pulse sequence of the family being a multi-spoke type sequence suitable for selectively exciting nuclear spins in a slice of a volume of interest of a body immersed in a static magnetic field and comprising radiofrequency pulses at a Larmor frequency of the nuclear spins alternated with magnetic gradient pulses. The global parameterization minimizes a function representing a mean deviation from a setpoint of the excitation of the nuclear spins, with the mean being computed for the volume of interest and for all the possible orientations and positions of the slices. It allows a selective excitation sequence to be simply designed for a slice with a random orientation and position.

IPC Classes  ?

  • G01R 33/483 - NMR imaging systems with selection of signal or spectra from particular regions of the volume, e.g. in vivo spectroscopy
  • G01R 33/48 - NMR imaging systems
  • G01R 33/561 - Image enhancement or correction, e.g. subtraction or averaging techniques by reduction of the scanning time, i.e. fast acquiring systems, e.g. using echo-planar pulse sequences
  • G01R 33/565 - Correction of image distortions, e.g. due to magnetic field inhomogeneities

29.

NOVEL FAMILY OF DNA POLYMERASES ACCEPTING 2-AMINOADENINE AND REJECTING ADENINE IN THEIR SUBSTRATES

      
Application Number 18286072
Status Pending
Filing Date 2022-04-13
First Publication Date 2024-06-06
Owner
  • THE EUROPEAN SYNDICATE OF SYNTHETIC SCIENTISTS AND INDUSTRIALISTS (France)
  • COMMISSARIAT À L´ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Bourguignon, Pierre-Yves Vincent
  • Marlière, Philippe
  • Pezo, Valérie
  • Meheust, Raphael

Abstract

Described is a novel family of DNA polymerases identified in bacteriophages (mainly from the family of Siphiroviridae) which are able to accept 2-amino-2′-deoxyadenosine 5′-triphosphate (dZTP) as a substrate but which do not accept deoxyadenosine 5′-triphosphate (dATP) as a substrate. Also described are recombinant nucleic acid molecules, encoding such polymerases, vectors comprising such nucleic acid molecules, host cells transformed with such nucleic acid molecules or vectors as well as to methods for producing DNA molecules containing 2-amino-2′-deoxyadenosine (dZ) instead of 2′-deoxyadenosine (dA) by making use of a novel polymerase.

IPC Classes  ?

  • C12N 9/12 - Transferases (2.) transferring phosphorus containing groups, e.g. kinases (2.7)
  • C12N 15/63 - Introduction of foreign genetic material using vectors; Vectors; Use of hosts therefor; Regulation of expression
  • C12P 19/34 - Polynucleotides, e.g. nucleic acids, oligoribonucleotides

30.

ANTIBODIES, FRAGMENTS OR DERIVATIVES SPECIFICALLY BINDING TO A PROTEIN ANTIGEN CAPABLE OF BINDING TO NUCLEIC ACIDS AND USES OF SAME

      
Application Number 18547471
Status Pending
Filing Date 2022-02-24
First Publication Date 2024-06-06
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Leonetti, Michel
  • Pereira Ramos, Oscar
  • Simon, Stephanie
  • Le Roux, Gwenaelle
  • Morel, Nathalie

Abstract

The present invention relates to a specific antibody of a protein antigen capable of binding to nucleic acids, or a fragment or a derivative of such an antibody binding to the antigen, for use as a drug, in particular in the treatment or prevention of inflammation, due especially to an infection or an autoimmune disease, characterised in that the antibody, fragment or derivative has a reduced capacity to bind to the FcγRIIA receptor and/or an increased capacity to bind to the FcγRIIB receptor. The antibody, fragment or derivative is preferably without an Fc domain, or with a modified Fc domain with a reduced capacity to bind to FcγRIIA and optionally FcγRIIA (or even a reduced capacity to bind to all FcγR), and/or with a modified Fc domain with an increased capacity to bind to FcγRIIB.

IPC Classes  ?

  • C07K 16/10 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from viruses from RNA viruses
  • A61K 39/00 - Medicinal preparations containing antigens or antibodies
  • A61P 37/06 - Immunosuppressants, e.g. drugs for graft rejection
  • C07K 16/08 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from viruses
  • C07K 16/18 - Immunoglobulins, e.g. monoclonal or polyclonal antibodies against material from animals or humans

31.

METHOD OF MEASURING BY ELECTRICAL IMPEDANCE TOMOGRAPHY

      
Application Number 18551338
Status Pending
Filing Date 2022-03-25
First Publication Date 2024-06-06
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Darnajou, Mathieu
  • Ricciardi, Guillaume

Abstract

An electrical impedance tomography method for the measurement of a body comprising a cylindrical part containing a fluid, the method comprising arranging a number of electrodes around a periphery of the cylindrical part of the body, simultaneously exciting each of the electrodes, each electrode being excited by a potential of a selected form, measuring the electrical properties of the body using electrodes, and processing the data from measuring step so as to obtain a signed data matrix representative of an image.

IPC Classes  ?

  • G01V 3/06 - Electric or magnetic prospecting or detecting; Measuring magnetic field characteristics of the earth, e.g. declination or deviation operating with propagation of electric current using ac

32.

DEVICE FOR PRODUCING A POLYCHROMATIC LIGHT BEAM BY COMBINING A PLURALITY OF INDIVIDUAL LIGHT BEAMS

      
Application Number 18556568
Status Pending
Filing Date 2022-04-14
First Publication Date 2024-06-06
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Monpeurt, Cyrielle
  • Dupoy, Mathieu
  • Jobert, Gabriel
  • Lartigue, Olivier
  • Mathieu, Grégoire

Abstract

A device includes several distinct laser sources each emitting an individual laser beam, a dispersive element, and a set of deflecting mirrors which, for each laser source, include a deflecting mirror associated to the source, the mirror reflecting the light beam emitted by the source towards the dispersive element, the mirror being positioned and oriented such that, after deflection by the dispersive element, the light beam is substantially centered on a common propagation axis, which is the same for the different light beams, the mirrors being integral with each other.

IPC Classes  ?

33.

SYSTÈME DE CHIFFREMENT HIÉRARCHIQUE HYBRIDE

      
Application Number 18516293
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-05-30
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Loiseau, Antoine
  • Lesaignoux, Doryan
  • Carmona, Mikael

Abstract

A hybrid cryptographic scheme for a network of nodes, in particular an IoT network, composed of a first subset and a second subset of separate nodes, the computing resources of the nodes of the first subset being greater than the computing resources of the nodes of the second subset, the scheme comprising a first functional cryptographic scheme deployed on the first subset of nodes and a second functional cryptographic scheme deployed on the second subset of nodes, a cryptographic primitive at the root of the second cryptographic scheme generating a pair of private and public master keys from a seed, the seed being obtained by a connection cryptographic primitive from at least the private key of an end node of the first subset, the connection cryptographic primitive being a one-way function.

IPC Classes  ?

  • H04L 9/08 - Key distribution
  • H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy

34.

Generic sterile sensor system on mobile mast

      
Application Number 18518769
Status Pending
Filing Date 2023-11-24
First Publication Date 2024-05-30
Owner
  • Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
  • GLOBAL PROCESS CONCEPT (France)
Inventor
  • Caroff, Tristan
  • Brulais, Sébastien
  • Gauroy, Martin
  • Burlet, Jean-Yves
  • Garaffa, Clément
  • Popse, Zsolt

Abstract

A device for analyzing at least one parameter of a chemical or biochemical or biological reaction in a reaction container, the analysis device includes an arm intended to be fastened by means of a sliding link against a face of a wall of the reaction container by means of a static end, the arm having a degree of freedom in translation in relation to the wall, a sensor designed to measure the at least one parameter, the sensor being fastened to a free end of the arm, a drive device designed to cause an axial displacement of the arm along the degree of freedom, a hermetic isolating device for isolating the arm from the reaction, the hermetic isolating device joining the arm to the face of the wall.

IPC Classes  ?

  • C12M 1/34 - Measuring or testing with condition measuring or sensing means, e.g. colony counters
  • C12M 3/00 - Tissue, human, animal or plant cell, or virus culture apparatus

35.

METHOD AND DEVICE FOR DETERMINING THE RELATIVE PERMITTIVITY OF A MATERIAL USING A GROUND-PENETRATING RADAR

      
Application Number 18520406
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-05-30
Owner COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Makhoul, Gloria
  • D’errico, Raffaele

Abstract

A new method for accurately estimating the relative permittivities and the thicknesses of each layer of a material such as the ground is provided. The method is based on acquisitions of measurements taken by a ground-penetrating radar provided with a plurality of transmitting antennas and a plurality of receiving antennas (multiple input multiple output or MIMO radar). The proposed method is based on a particular algorithm that aims to estimate the most probable (delay, relative permittivity) pairs that correspond to the different layers making up the structure of the ground.

IPC Classes  ?

  • G01S 13/88 - Radar or analogous systems, specially adapted for specific applications
  • G01S 13/42 - Simultaneous measurement of distance and other coordinates

36.

ADJUSTING AND MEASURING METHOD AND SYSTEM FOR A PHOTOVOLTAIC POWER PLANT

      
Application Number 18520429
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-05-30
Owner COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Amhal, Mohamed
  • Buttin, Hervé

Abstract

Adjusting and measuring method for a photovoltaic power plant comprising at least one photovoltaic string comprising solar panels connected in series and comprising at least one inverter configured to convert a DC voltage generated by the photovoltaic string into an AC voltage, the at least one inverter having a plurality of DC-voltage inputs, the method comprising the following steps: A. measuring a frequency f of an AC voltage generated by the photovoltaic power plant and computing a frequency variation Δf of the AC voltage with respect to a predetermined reference frequency fref such that: Δf=f−fref and computing a power variation ΔP to be applied by the photovoltaic power plant based on the frequency variation, B. selecting a DC-voltage input from the plurality of DC-voltage inputs, this input being referred to as the i-th input with i an integer ≥1, in order to start or resume a measurement of a curve of “current as a function of voltage” of the i-th input, the i-th input having what is referred to as an initial DC voltage Vini, then C. computing what is referred to as a residual power variation ΔP′ to be applied by the photovoltaic power plant such that ΔP′=ΔP−Pi, D. if ΔP′≠0: distributing the residual power variation ΔP′ over inputs different from the i-th input, E. repeating the preceding steps a plurality of times so as to create a plurality of different points of the measured curve of “current as a function of voltage”.

IPC Classes  ?

  • H02S 50/10 - Testing of PV devices, e.g. of PV modules or single PV cells

37.

ELECTRONIC DEVICE

      
Application Number 18522330
Status Pending
Filing Date 2023-11-29
First Publication Date 2024-05-30
Owner Commissariat à I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Bourjot, Emilie
  • Laviron, Cyrille
  • Charbonnier, Jean
  • Lamy, Yann

Abstract

An interposer including capacitors having a density greater than 700 nF/mm{circumflex over ( )}2. advantageously greater than 1 μF/mm{circumflex over ( )}2. the interposer being adapted to being bonded to a chip by hybrid bonding.

IPC Classes  ?

  • H01L 23/64 - Impedance arrangements
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/498 - Leads on insulating substrates

38.

OPTICAL FILTER FOR A MULTISPECTRAL SENSOR AND METHOD FOR MANUFACTURING SUCH A FILTER

      
Application Number 18193223
Status Pending
Filing Date 2023-03-30
First Publication Date 2024-05-30
Owner
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
  • STMicroelectronics (Crolles 2) SAS (France)
Inventor
  • Villenave, Sandrine
  • Abadie, Quentin

Abstract

The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, at least one resonant cavity comprising a transparent region having a first refraction index and laterally delimited by a reflective peripheral vertical wall, and at least one resonant element formed in said region.

IPC Classes  ?

  • G02B 26/00 - Optical devices or arrangements for the control of light using movable or deformable optical elements
  • G01J 3/26 - Generating the spectrum; Monochromators using multiple reflection, e.g. Fabry-Perot interferometer, variable interference filter
  • G02B 5/28 - Interference filters

39.

MICROELECTRONIC DEVICE WITH IMPROVED VERTICAL BREAKDOWN VOLTAGE

      
Application Number 18510858
Status Pending
Filing Date 2023-11-16
First Publication Date 2024-05-30
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Garnier, Gennie
  • Gwoziecki, Romain
  • Gillot, Charlotte

Abstract

A microelectronic device including a first transistor including a first active layer, a second field effect transistor including a second active layer, the second source being electrically connected to the first drain, a first rear electrode and a second rear electrode. The device in addition includes an insulating layer extending, between the first rear electrode and the first active layer, on the one hand, and the second rear electrode and the second active layer, on the other hand. The insulating layer is continuous and has a critical field Ec and a thickness called dielectric thickness e1500 of between 2*e1500,min and 10*e1500,min, with e1500,min=Vtarget/Ec, Vtarget being a target breakdown voltage of the insulating layer, the first dielectric having a heat conductivity λ1 greater than 1 W·m−1·K−1.

IPC Classes  ?

  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 29/786 - Thin-film transistors

40.

METHOD FOR PROVIDING A RANDOM FOR A CRYPTOGRAPHIC ALGORITHM, RELATED METHOD FOR PROCESSING A DATA AND COMPUTER PROGRAM

      
Application Number 18519145
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-05-30
Owner Commissariat à l'énergie atomique et aux énergies alternatives (France)
Inventor
  • Pebay-Peyroula, Florian
  • Cagli, Carlo
  • Fauriat, Mattieu

Abstract

The present method of providing element a random for a cryptographic algorithm is implemented by an electronic calculator comprising a core and a set of memory/memories, the set of memory/memories including a reference memory having an intrinsic randomness in a predefined state of generating randoms. The present method of providing element a random for a cryptographic algorithm is implemented by an electronic calculator comprising a core and a set of memory/memories, the set of memory/memories including a reference memory having an intrinsic randomness in a predefined state of generating randoms. The method comprises: reading a reference message in a first memory zone, the first memory zone being included in the reference memory, the reading step being performed in the state of generating random elements of the reference memory; writing the reference message in a second memory zone, distinct from the first memory zone, the second memory zone being included in the set of memory/memories; subsequent reading of the reference message in the second memory zone, the reference message read in the second memory zone forming the random element for the cryptographic algorithm.

IPC Classes  ?

  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system

41.

CURRENT-ASSISTED PHOTONIC DEMODULATOR WITH IMPROVED PERFORMANCES INCLUDING INTERMEDIATE ELECTRODES

      
Application Number 18519849
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-05-30
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Aliane, Abdelkader
  • Kaya, Hacile
  • Durlin, Quentin
  • Hartmann, Jean-Michel
  • Andre, Luc

Abstract

A current-assisted photonic demodulator includes a detection portion having two doped modulation regions and two doped collection regions, lying flush with a first face covered by a dielectric layer. Electrodes pass through the dielectric layer and come into contact with the doped regions. In addition, intermediate electrodes partly pass through the dielectric layer and are spaced apart from the first face by a non-zero distance, each being located, in projection in a main plane, between one of the doped modulation regions and the adjacent doped collection region.

IPC Classes  ?

  • G02F 2/00 - Demodulating light; Transferring the modulation of modulated light; Frequency-changing of light

42.

PHOTOACOUSTIC SYSTEM AND ASSOCIATED METHOD

      
Application Number 18521440
Status Pending
Filing Date 2023-11-28
First Publication Date 2024-05-30
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Ben Bakir, Badhise
  • Lartigue, Olivier
  • Constancias, Christophe

Abstract

A photoacoustic system includes a semiconductor substrate including a hollow volume and a window extending in vertical alignment with a part of the hollow volume, and a surface emitting device including a waveguide and a diffraction grating, the waveguide having an upper face and a lower face, the lower face being disposed on the window, the diffraction grating being disposed on the upper face or on the lower face.

IPC Classes  ?

  • H01S 3/063 - Waveguide lasers, e.g. laser amplifiers
  • G01N 29/24 - Probes
  • H01S 3/08 - Construction or shape of optical resonators or components thereof

43.

NANOCRYSTAL PARTICLES AND PRODUCTION METHOD THEREOF

      
Application Number 18517453
Status Pending
Filing Date 2023-11-22
First Publication Date 2024-05-30
Owner
  • SAMSUNG ELECTRONICS CO., LTD. (Republic of Korea)
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
  • CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (France)
  • UNIVERSITE GRENOBLE ALPES (France)
Inventor
  • Won, Yuho
  • Kim, Yongwook
  • Reiss, Peter
  • Saha, Avijit
  • Yadav, Ranjana

Abstract

A nanocrystal particle includes a Group III-VI compound including gallium and sulfur, wherein the nanocrystal particle is configured to emit a first light, a maximum emission peak of the first light is in a wavelength range of greater than or equal to about 300 nanometers and less than or equal to about 485 nanometers, an absolute quantum efficiency of the nanocrystal particle is greater than or equal to about 26%, and a full width at half maximum of the maximum emission peak of the first light is greater than or equal to about 10 nanometers and less than or equal to about 70 nanometers, when analyzed by photoluminescence spectroscopy.

IPC Classes  ?

  • C09K 11/64 - Luminescent, e.g. electroluminescent, chemiluminescent, materials containing inorganic luminescent materials containing aluminium
  • C09K 11/62 - Luminescent, e.g. electroluminescent, chemiluminescent, materials containing inorganic luminescent materials containing gallium, indium or thallium
  • G02F 1/1335 - Structural association of cells with optical devices, e.g. polarisers or reflectors
  • H10K 50/115 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising active inorganic nanostructures, e.g. luminescent quantum dots
  • H10K 59/38 - Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]

44.

PULSED LASER DEVICE COMPRISING A HYBRID LASER SOURCE WITH ACTIVE OPTICAL TRIGGERING

      
Application Number 18516176
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-05-23
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Charbonnier, Benoit
  • Mekemeza, Ona Keshia

Abstract

A pulsed laser device including: a III-V-on-silicon type hybrid pulsed laser source, including a gain section and a saturable absorber section which rest on a photonic substrate, and a longitudinal waveguide located in the photonic substrate; a control optical device including an optical pulse emitter source and a lateral waveguide located in the photonic substrate; the waveguides being sized so that the confinement factor Γlae/SA, Γlai/G in the quantum wells of the corresponding section of the optical mode of the lateral waveguide is higher than the confinement factor IL/ms, in the quantum wells of the semiconductor medium, of the optical mode of the longitudinal waveguide.

IPC Classes  ?

  • G02B 6/122 - Basic optical elements, e.g. light-guiding paths
  • H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
  • H01S 5/10 - Construction or shape of the optical resonator

45.

DISPLAY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE

      
Application Number 18507675
Status Pending
Filing Date 2023-11-13
First Publication Date 2024-05-23
Owner Commissariat à l'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Templier, François
  • Becker, Sébastien
  • Bourvon, Hélène

Abstract

A device including: a transfer substrate including electric connection elements; a plurality of first monolithic elementary chips bonded and electrically connected to the transfer substrate, each first elementary chip including at least one LED and one integrated electronic circuit for controlling said at least one LED, the device further including, associated with at least one of the first elementary chips, a second elementary chip including a vertical cavity surface-emitting laser diode, bonded and electrically connected to the transfer substrate, the first elementary chip including an integrated electronic circuit for controlling said laser diode.

IPC Classes  ?

  • H01S 5/0239 - Combinations of electrical or optical elements
  • H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
  • H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
  • H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
  • H01S 5/0237 - Fixing laser chips on mounts by soldering
  • H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

46.

PROCESS FOR MANUFACTURING AN ORGANIC ELECTROLUMINESCENT DEVICE

      
Application Number 18512193
Status Pending
Filing Date 2023-11-17
First Publication Date 2024-05-23
Owner Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
Inventor
  • Tournaire, Myriam
  • Maindron, Tony

Abstract

Process for manufacturing an organic electroluminescent device on a stack comprising, in succession: a substrate, incorporating n-type thin-film transistors each comprising a drain, a source and a gate; an interconnecting structure, electrically connected to the n-type transistors, and comprising: a common anode, electrically connected to the sources of the n-type transistors; vias, each electrically connected to a drain of one n-type transistor; the organic electroluminescent device being formed with a direct architecture, a cathode being singulated at the pixel scale, each pixel being drivable using an electrical contact pad dedicated thereto.

IPC Classes  ?

  • H10K 71/60 - Forming conductive regions or layers, e.g. electrodes
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays

47.

Photonic chip and infrared imaging system using such a photonic chip

      
Application Number 18513082
Status Pending
Filing Date 2023-11-17
First Publication Date 2024-05-23
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Dupoy, Mathieu
  • Monpeurt, Cyrielle

Abstract

A photonic chip for scene illumination, the photonic chip comprises a substrate comprising a face with an etching, a plurality of waveguides extending parallel to a plane formed by the etched face of the substrate, each waveguide being configured to guide at least one light beam, a plurality of diffraction gratings, respectively formed in a waveguide and each being configured to extract, out of the waveguide in which it is formed and towards the etching of the substrate, the light beam propagating in said waveguide, at least two waveguides being configured to receive light beams of different wavelengths, and wherein the etching of the substrate is configured to extract the light beams out of the substrate, towards the scene to be illuminated, said scene lying against the etched face of the substrate and at the level of the etching of the substrate.

IPC Classes  ?

  • G02B 6/34 - Optical coupling means utilising prism or grating
  • G02B 6/10 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type

48.

DEVICE FOR CONVERTING A PHOTONIC SIGNAL, ASSOCIATED LIDAR AND METHOD

      
Application Number 18549787
Status Pending
Filing Date 2022-03-11
First Publication Date 2024-05-23
Owner Commissariat à l'énergie atomique et aux énergies alternatives (France)
Inventor Dupont, Bertrand

Abstract

A device for converting a photonic signal to be analyzed includes two output branches, and one input for receiving a photonic signal to be analyzed and splitting off a part of the photonic signal to each output branch. The device imposes a phase shift of approximately 180 degrees between the two parts, each output branch including a photodiode generating a respective first electrical current. Each output branch generates a second electrical current according to a value of the first current of the branch considered. The device also includes an amplifier generating an output signal according to a difference between the values of the second currents, a gain being defined for each output branch, and at least one electronically controlled adjustment element configured to modify one of the gains.

IPC Classes  ?

49.

FIELD EFFECT TRANSISTOR WITH P-FET TYPE BEHAVIOUR

      
Application Number 18363242
Status Pending
Filing Date 2023-08-01
First Publication Date 2024-05-16
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Buckley, Julien
  • Escoffier, René
  • Le Royer, Cyrille
  • Mohamad, Blend

Abstract

A field effect transistor includes a substrate; an electron channel layer disposed on the substrate; a barrier layer disposed on the electron channel layer; a hole channel layer disposed on the barrier layer; a p-type doped semiconductor material layer disposed on the hole channel layer; a source electrode including a first portion in ohmic contact with the electron channel layer and a second portion in ohmic contact with the p-type doped semiconductor material layer; a drain electrode in ohmic contact with the electron channel layer; and a gate electrode disposed facing the p-type doped semiconductor material layer, between the source and drain electrodes.

IPC Classes  ?

  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/80 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate

50.

PROCESS FOR ACTIVATING A FUEL CELL

      
Application Number 18505367
Status Pending
Filing Date 2023-11-09
First Publication Date 2024-05-16
Owner
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
  • INSTITUT POLYTECHNIQUE DE GRENOBLE (France)
  • UNIVERSITE SAVOIE MONT BLANC (France)
  • CNRS (France)
  • UNIVERSITE GRENOBLE ALPES (France)
Inventor
  • Pinton, Eric
  • Bultel, Yann
  • Drugeot, Timothée
  • Micoud, Fabrice

Abstract

A method may activate a fuel cell including a plurality of electrochemical cells in a stack, the fuel cell being intended to operate, during at least one nominal operating phase, as an electric generator. Such a method may include, during an activation phase by electrolysis, prior to the at least one nominal operating phase: electrically supplying the fuel cell by an external electric generator, the electric supply being configured to apply an activation voltage greater than the voltage of the cell in an open circuit (OCV); fluid supplying a humid gas fluid at a first electrode and/or a second electrodes. The humid gas may have a relative humidity (RH) such that 40%≤RH<100%. The fuel cell may operate in electrolysis during the activation phase called by electrolysis.

IPC Classes  ?

  • H01M 8/04225 - Auxiliary arrangements, e.g. for control of pressure or for circulation of fluids during start-up or shut-down; Depolarisation or activation, e.g. purging; Means for short-circuiting defective fuel cells during start-up
  • H01M 4/86 - Inert electrodes with catalytic activity, e.g. for fuel cells
  • H01M 4/96 - Carbon-based electrodes
  • H01M 8/04089 - Arrangements for control of reactant parameters, e.g. pressure or concentration of gaseous reactants
  • H01M 8/04119 - Arrangements for control of reactant parameters, e.g. pressure or concentration of gaseous reactants with simultaneous supply or evacuation of electrolyte; Humidifying or dehumidifying
  • H01M 8/04223 - Auxiliary arrangements, e.g. for control of pressure or for circulation of fluids during start-up or shut-down; Depolarisation or activation, e.g. purging; Means for short-circuiting defective fuel cells
  • H01M 8/04828 - Humidity; Water content
  • H01M 8/0656 - Combination of fuel cells with means for production of reactants or for treatment of residues with means for production of gaseous reactants by electrochemical means
  • H01M 8/1004 - Fuel cells with solid electrolytes characterised by membrane-electrode assemblies [MEA]

51.

METHOD AND SYSTEM FOR TREATING A STACK INTENDED FOR THE MANUFACTURE OF A HETEROJUNCTION PHOTOVOLTAIC CELL

      
Application Number 18549757
Status Pending
Filing Date 2022-02-16
First Publication Date 2024-05-16
Owner COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor Jeronimo, Pedro

Abstract

A process for treating a stack intended for manufacture of a photovoltaic cell includes placing the stack in an enclosure, exposing the stack to electromagnetic radiation, and cooling the stack during exposure. The photovoltaic cell is cooled by injecting a gas flow into the enclosure, regulating the injected gas flow taking into account the temperature of the stack, and evacuating the gas flow from the enclosure taking into account the ambient temperature present in the enclosure.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/20 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor material

52.

THREE-DIMENSIONAL NOR MEMORY STRUCTURE

      
Application Number 18388164
Status Pending
Filing Date 2023-11-08
First Publication Date 2024-05-09
Owner
  • COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
  • Centre national de la recherche scientifique (France)
  • UNIVERSITE D’AIX-MARSEILLE (France)
Inventor
  • Ezzadeen, Mona
  • Andrieu, François
  • Portal, Jean-Michel

Abstract

A data storage circuit of NOR type includes a three-dimensional memory structure, produced on a first semiconductor substrate, and comprising a plurality of memory planes, each plane forming a two-dimensional array of memory cells. Each memory cell has a selection node, a first input/output node and a second input/output node. The three-dimensional memory structure has an upper surface comprising a plurality of connectors distributed over the surface; each connector is connected to at least one among the first or second input/output nodes of a given column; a control circuit produced on a second semiconductor substrate; an interconnection structure comprising: a plurality of bonding pads placed between the control circuit and the upper surface; the plurality of bonding pads forms a periodic repetition of a unit pattern in a plane parallel to the upper surface.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuits; Data output circuits
  • G11C 16/10 - Programming or data input circuits
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

53.

MONOLITHICALLY-INTEGRATED CURRENT-FEEDBACK INSTRUMENTATION AMPLIFIER AND SENSING SYSTEM COMPRISING SAID AMPLIFIER

      
Application Number 18388168
Status Pending
Filing Date 2023-11-08
First Publication Date 2024-05-09
Owner
  • COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
  • Politecnico di Milano (Italy)
Inventor
  • Langfelder, Giacomo
  • Buffoli, Andrea
  • Gadola, Marco

Abstract

A monolithically-integrated current-feedback instrumentation amplifier includes two differential pairs of transistors. A drain terminal of transistor is directly connected to a drain terminal of transistor and to a differential voltage amplifier, and is connected to a ground terminal by means of a first sink resistor. A drain terminal of transistor is directly connected to a drain terminal of transistor and to the differential voltage amplifier, and is connected to a ground terminal by means of a second sink resistor. An output terminal of the differential voltage amplifier is connected to a resistive voltage divider. Source terminals of the transistors are directly connected together and to a first bias current source without a degeneration resistor, and source terminals of the transistors are directly connected together and to a second bias current source without a degeneration resistor. A sensing system comprising a piezoresistive N&MEMS sensor and a monolithically-integrated differential readout circuit comprising the amplifier are also provided.

IPC Classes  ?

  • H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
  • G01C 19/5712 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis the devices involving a micromechanical structure

54.

GROWTH SUBSTRATE OF A DIODE ARRAY, INCLUDING MESAS HAVING DIFFERENT POROSIFICATION LEVELS

      
Application Number 18495045
Status Pending
Filing Date 2023-10-26
First Publication Date 2024-05-09
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Dupre, Ludovic
  • Dussaigne, Amélie
  • Pernel, Carole
  • Rol, Fabien

Abstract

A growth substrate adapted for making by epitaxy an array of InGaN based diodes, including mesas M(i), made of GaN based crystalline materials, each including N doped layers, with N≥2, separated in pairs by an insulation intermediate layer made of a non-porous material, and each having a free upper face adapted for making a diode of the array by epitaxy; the mesas being configured according to at least three different categories including: a so-called M(N) mesas category where the N doped layers are porous; a so-called M(0) mesas category where none of the doped layers (13, 15) is porous; and a so-called M(n) mesas category where n doped layers are porous, with 1≤n

IPC Classes  ?

  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/18 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
  • H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

55.

DEVICE FOR CONVERTING A PHOTONIC SIGNAL, ASSOCIATED LIDAR AND METHOD

      
Application Number 18550057
Status Pending
Filing Date 2022-03-11
First Publication Date 2024-05-09
Owner Commissariat à l'énergie atomique et aux énergies alternatives (France)
Inventor Dupont, Bertrand

Abstract

The invention relates to a device for converting a photonic signal to be analyzed, comprising two output branches, one input for receiving a photonic signal to be analyzed and splitting off a part of the photonic signal to each output branch, the device imposing a phase shift of approximately 180 degrees between the two parts, each output branch including a photodiode generating a respective first electrical current, each output branch generating a second current according to a value of the first current of the branch considered, the device comprising an amplifier generating an output signal according to a difference between the values of the second currents, a gain being defined for each output branch, the device including at least one electronically controlled adjustment element apt to modify one of the gains.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements

56.

METHOD FOR BONDING TWO HYDROPHILIC SURFACES

      
Application Number 17755450
Status Pending
Filing Date 2020-10-20
First Publication Date 2024-05-09
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Fournel, Frank
  • Calvez, Aziliz
  • Eleouet, Gaelle
  • Larrey, Vincent
  • Morales, Christophe

Abstract

A method of direct bonding comprising the following steps: supplying a first substrate and a second substrate, the first substrate being covered by a first hydrophilic surface and the second substrate being covered by a second hydrophilic surface, deposition of a specific molecule on the first hydrophilic surface and/or on the second hydrophilic surface, the specific molecule comprising a hydrophilic functional group and a basic functional group, separated by at least one atom, contacting the first hydrophilic surface with the second hydrophilic surface, whereby the two hydrophilic surfaces are bonded one with the other, and the first substrate and the second substrate are assembled, optionally, application of a bonding annealing heat treatment, preferably at a temperature less than or equal to 500° C.

IPC Classes  ?

  • C09J 5/02 - Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving pretreatment of the surfaces to be joined
  • C09J 5/06 - Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive

57.

STACK OF MONOCRYSTALLINE LAYERS FOR PRODUCING MICROELECTRONIC DEVICES WITH 3D ARCHITECTURE

      
Application Number 18502862
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-05-09
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Barraud, Sylvain
  • Reboh, Shay

Abstract

Stack of layers of monocrystalline materials suitable for producing microelectronic devices with 3D architecture comprising transistors, including several first layers of monocrystalline material, several second layers of monocrystalline material different from that of the first layers, and at least one third layer of monocrystalline material different from those of the first and second layers, wherein: a first of the monocrystalline materials of the first, second and third layers corresponds to intrinsic silicon; a second of the monocrystalline materials of the first, second and third layers corresponds to intrinsic SiGe; a third of the monocrystalline materials of the first, second and third layers corresponds to p-doped silicon or p-doped SiGe.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 29/786 - Thin-film transistors

58.

NEURAL ACTIVITY MEASURING SYSTEM WITH IMPROVED FIXING DEVICE

      
Application Number 18493852
Status Pending
Filing Date 2023-10-25
First Publication Date 2024-05-02
Owner Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
Inventor
  • Sauter-Starace, Fabien
  • Charvet, Guillaume

Abstract

A system for measuring the neural activity of a living being, including an implantable measuring device equipped with a housing to be accommodated, at least partially, in a cavity formed in the cranium (C) of a living being, and including a system of electrodes for measuring the neural activity, arranged on one face of the housing, and electronic signal-processing device, which are accommodated in the housing and to which the electrode system is connected, a device for fixing the housing in the cavity, the fixing device including at least one device for mechanically holding the housing in the cavity, a device for fixing the mechanical holding device, which are arranged to fix the holding device in the cranium (C) on the periphery of the cavity, a device for adjusting the depth position of the housing in the cavity.

IPC Classes  ?

  • A61B 5/293 - Invasive
  • A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons

59.

LIGHT EMITTING AND RECEIVING DEVICE

      
Application Number 18493608
Status Pending
Filing Date 2023-10-24
First Publication Date 2024-05-02
Owner Commissariat à I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor Dupont, Florian

Abstract

The present description relates to a light emitting and receiving device including:-a light-emitting diode including a first active layer, a first electrode in contact with the lower face of the first active layer, and a second electrode in contact with the upper face of the first active layer; and opposite the light-emitting diode, on an emission face of the light-emitting diode, a light conversion and detection element comprising a second active layer, a third electrode in contact with the lower face of the second active layer, and a fourth electrode in contact with the upper face of the second active layer.

IPC Classes  ?

  • H01L 31/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
  • H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 31/0224 - Electrodes
  • H01L 31/0232 - Optical elements or arrangements associated with the device

60.

MEMS RESONANT SENSOR ADAPTED TO GENERATE A PULSE OUTPUT SIGNAL

      
Application Number 18381027
Status Pending
Filing Date 2023-10-16
First Publication Date 2024-04-25
Owner COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Hardy, Emmanuel
  • Fain, Bruno
  • Vianello, Elisa

Abstract

A MEMS resonant sensor adapted to generate a pulse output signal from a signal of interest, the signal of interest being a signal having a frequency oscillating around a carrier frequency, the MEMS sensor comprising at least one processing channel for processing the signal of interest, each processing channel comprising: a demodulation unit for demodulating the signal of interest in order to form a demodulated signal, the demodulation unit comprising a frequency mixer between the signal of interest and a reference signal, the demodulated signal having a low-frequency component and a high-frequency component; a filtration unit for filtering the demodulated signal in order to form a filtered signal, the filtration unit being adapted to allow through the low-frequency component of the demodulated signal; a comparison unit for comparing the filtered signal with a fixed threshold signal in order to form a comparison signal, the comparison signal comprising rising edges and falling edges; a detection unit for detecting rising edges, each rising edge corresponding to a pulse of the output signal.

IPC Classes  ?

  • B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems (MEMS)
  • G01P 15/125 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up

61.

ELECTRONIC CIRCUIT WITH RRAM CELLS

      
Application Number 18483638
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-04-25
Owner
  • Commissariat à l'énergie atomique et aux énergies alternatives (France)
  • Centre national de la recherche scientifique (France)
  • Université d'Aix-Marseille (France)
Inventor
  • Ezzadeen, Mona
  • Giraud, Bastien
  • Noel, Jean-Philippe
  • Portal, Jean-Michel

Abstract

The electronic circuit performs binary computation operations and comprises word, bit and source lines, and memory cells organized in rows and columns. The electronic circuit performs binary computation operations and comprises word, bit and source lines, and memory cells organized in rows and columns. Each cell includes one pair of memristors and one pair of switches, each memristor being connected to a switch and linked to the same source line during each computation operation, each pair of memristors storing a binary value; the switches being linked to a word line and to a pair of complementary bit lines. The electronic circuit performs binary computation operations and comprises word, bit and source lines, and memory cells organized in rows and columns. Each cell includes one pair of memristors and one pair of switches, each memristor being connected to a switch and linked to the same source line during each computation operation, each pair of memristors storing a binary value; the switches being linked to a word line and to a pair of complementary bit lines. The circuit comprises a reading module including: a logic unit for each column, each comprising an input terminal connected to a source line to receive a column value, the logic unit toggling between values, depending on a comparison of the column value with a toggle threshold value; a modification unit for modifying, for at least one logic unit and depending on the computation operation, a difference between the column and threshold values.

IPC Classes  ?

  • G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
  • G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron

62.

DEVICE FOR DETECTING A MAGNETIC FIELD AND SYSTEM OF MAGNETIC FIELD MEASUREMENT COMPRISING SUCH A DEVICE

      
Application Number 18489080
Status Pending
Filing Date 2023-10-17
First Publication Date 2024-04-25
Owner Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
Inventor Nikolovski, Jean-Pierre

Abstract

The present description relates to a device (20) for detecting a magnetic field (Bz) comprising a first tapered acoustic waveguide (40) having a first base (41) and a first tapered end (42), a first electrically conductive wire (50) rigidly coupled to the first tapered end (42), and an electroacoustic transducer (60) rigidly coupled to the first base (41).

IPC Classes  ?

  • G01R 33/038 - Measuring direction or magnitude of magnetic fields or magnetic flux using permanent magnets, e.g. balances, torsion devices
  • G01H 11/08 - Measuring mechanical vibrations or ultrasonic, sonic or infrasonic waves by detecting changes in electric or magnetic properties by electric means using piezoelectric devices
  • G01R 33/028 - Electrodynamic magnetometers

63.

PROCESS FOR MANUFACTURING A SOLID-STATE MICROBATTERY AND CORRESPONDING MICROBATTERY

      
Application Number 18489908
Status Pending
Filing Date 2023-10-18
First Publication Date 2024-04-25
Owner Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
Inventor
  • Colonna, Jean-Philippe
  • Oukassi, Sami
  • Bert, Maude
  • Dechamp, Jérôme

Abstract

A solid-state microbattery, including a substrate; a lithium-cobalt-oxide layer forming a cathode having first and second opposite surfaces; a lithium-based solid-state electrolyte formed on the first surface of the cathode; the second surface of the cathode is oriented towards the substrate; an anode formed on the solid-state electrolyte; noteworthy in that the lithium-cobalt-oxide layer possesses a grain size that increases from the first surface to the second surface.

IPC Classes  ?

  • H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
  • H01M 10/0525 - Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodes; Lithium-ion batteries
  • H01M 10/0562 - Solid materials
  • H01M 10/0585 - Construction or manufacture of accumulators having only flat construction elements, i.e. flat positive electrodes, flat negative electrodes and flat separators

64.

NEURAL NETWORK CIRCUIT WITH DELAY LINE

      
Application Number 18491017
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-04-25
Owner
  • Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
  • Universität Zürich (Switzerland)
Inventor
  • Moro, Filippo
  • Vianello, Elisa
  • D'Agostino, Simone
  • Indiveri, Giacomo
  • Payvand, Melika

Abstract

The present disclosure relates to a neural network comprising a first synapse circuit (106) configured to apply a first time delay to a first input signal (READ1) using a first resistive memory element (108) and to generate a first output signal at an output of the first synapse circuit by applying a first weight to the delayed first input signal; and a second synapse circuit (106) configured to apply a second time delay, different to the first time delay, to the first input signal, or to a second input signal (READN), using a second resistive memory element (108) and to generate a second output signal at an output of the second synapse circuit by applying a second weight to the delayed second input signal.

IPC Classes  ?

  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

65.

METHOD FOR MANUFACTURING AN ELECTRONIC POWER DEVICE, AND DEVICE OBTAINED BY THIS METHOD

      
Application Number 18493562
Status Pending
Filing Date 2023-10-23
First Publication Date 2024-04-25
Owner Commissariat á I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor Dupont, Florian

Abstract

A method for manufacturing a power electronic device including the following successive steps: a) providing a silicon semiconductor substrate, the substrate having a front face and a rear face, opposite the front face; b) forming, by epitaxial growth from the front face of the substrate, a first continuous layer of at least one nitrided transition metal coating the front face of the substrate; and c) forming, on the first layer, by epitaxial growth from the front face of the substrate, at least one second layer of a III-V material, preferably III-N.

IPC Classes  ?

  • H01L 29/861 - Diodes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

66.

RESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD

      
Application Number 18493921
Status Pending
Filing Date 2023-10-24
First Publication Date 2024-04-25
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Charpin-Nicolle, Christelle
  • Blonkowski, Serge
  • Gassilloud, Rémy
  • Magis, Thomas

Abstract

A resistive memory device including at least one first electrode based on a first metal and a second electrode based on a second metal, and a memory element in the form of a metal filament based on a third metal and inserted between the first and second electrodes, the memory element having a filament cross-section strictly smaller than the electrode cross-sections, wherein the third metal has a chemical composition, different from those of the first and second metals giving it an etching speed greater than those of the first and second metals, preferably such that the selectivity at the etching is greater than or equal to 3:1, vis-á-vis the first and second metals. A method for manufacturing such a device is also disclosed.

IPC Classes  ?

  • H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10N 70/20 - Multistable switching devices, e.g. memristors

67.

METHOD FOR SYNTHESISING A LIQUID ORGANIC HYDROGEN CARRIER (LOHC) LOADED WITH HYDROGEN USING HYDROGEN PRODUCED FROM A METHANISATION DIGESTATE

      
Application Number 18569889
Status Pending
Filing Date 2022-06-07
First Publication Date 2024-04-25
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Leturcq, Gilles
  • Delahaye, Thibaud

Abstract

A synthesis process of a liquid organic hydrogen carrier charged with hydrogen, Hn-LOHC, wherein a methanisation digestate is used as a hydrogen source, including at least the steps of: a) production of gaseous ammonia from the methanisation digestate; b) division of the gaseous ammonia produced in step a) into a first and a second flow; c) catalytic amination of a liquid organic hydrogen carrier not charged with hydrogen, H0-LOHC, by reaction with the gaseous ammonia from the first flow to convert the H0-LOHC into an aminated H0-LOHC and produce hydrogen; d) catalytic dissociation of gaseous ammonia from the second flow to produce hydrogen; and e) catalytic hydrogenation of the aminated H0-LOHC obtained in step c), by reacting with the hydrogen produced in steps c) and d), whereby the Hn-LOHC is obtained.

IPC Classes  ?

  • C01B 3/00 - Hydrogen; Gaseous mixtures containing hydrogen; Separation of hydrogen from mixtures containing it; Purification of hydrogen
  • C01B 3/04 - Production of hydrogen or of gaseous mixtures containing hydrogen by decomposition of inorganic compounds, e.g. ammonia

68.

INFRARED DETECTOR IMPROVED VIA ENGINEERING OF THE EFFECTIVE MASS OF CHARGE CARRIERS

      
Application Number 18275174
Status Pending
Filing Date 2022-02-01
First Publication Date 2024-04-25
Owner
  • LYNRED (France)
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Evirgen, Axel
  • Reverchon, Jean-Luc
  • Trinite, Virgnie

Abstract

A device for detecting infrared radiation, includes at least one pixel having an axis in a direction Z, the pixel comprising a first absorbent planar structure comprising at least one semiconductor layer. The composition of the materials used to produce the at least one layer of the first absorbent planar structure is chosen such that: the first absorbent planar structure has an effective valence band formed by a plurality of energy levels. Each energy level is occupied by one of: a first type of positive charge carrier, called heavy holes, having a first effective mass; or a second type of positive charge carrier, called light holes, having a second effective mass strictly less than the first effective mass. The maximum energy level of the effective valence band is occupied by light holes along the axis of the pixel.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions

69.

HYBRID FeRAM/OxRAM DATA STORAGE CIRCUIT

      
Application Number 18379132
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-04-25
Owner COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Martemucci, Michele
  • Rummens, François
  • Vianello, Elisa
  • Hirtzlin, Tifenn

Abstract

A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to the word line or the source line and having the same direction as the common bit line.

IPC Classes  ?

  • G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

70.

METHOD FOR MANAGING RADIO RESOURCES IN A CELLULAR NETWORK BY MEANS OF A HYBRID MAPPING OF RADIO CHARACTERISTICS

      
Application Number 18484081
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-04-25
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor Sana, Mohamed

Abstract

The present invention relates to a method for managing radio resources in a cellular network. For each node of interest (Nj) of the network, a set (Vj(t)) of neighbouring nodes is determined. Each neighbouring node (Ni∈Vj(t)) performs a local observation of its environment (oi(t,f)) and extracts thereform a plurality of radio characteristics, then encodes each of these radio characteristics in the form of a message (mi,jk(t,f)) which is transmitted to the node of interest. The node of interest then generates a local mapping (Φjk(t,f)) of each radio characteristic by aggregating the messages encoding this characteristic. Afterwards, the different local mappings are fused using fusion parameters so as to provide a hybrid local mapping (Φja(t,f)) of the radio characteristics. The node of interest decides at all times to perform an action (aj(t)) amongst a finite set (A) of possible actions, based on said hybrid local mapping and on a radio resource management strategy defined by a conditional probability parameterised distribution of each action (πj,θ(aj(t)|Φja(t,f)). The set of fusion parameters as well as the set (θ) of the parameters of the conditional probability distribution undergo a reinforcement learning so as to maximise a reward over time, dependent on an objective function of the network.

IPC Classes  ?

  • H04W 72/50 - Allocation or scheduling criteria for wireless resources
  • H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence

71.

INCREASING THE DENSIFICATION OF SOLAR MODULES BY MAXIMIZED SUPERIMPOSED INTERCONNECTION

      
Application Number 18489940
Status Pending
Filing Date 2023-10-18
First Publication Date 2024-04-25
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Soulas, Romain
  • Chambion, Bertrand

Abstract

A photovoltaic device comprising an assembly of several strings of photovoltaic cells, each of the strings being formed by a plurality of cells aligned in a first direction y, the strings being aligned in a second direction x forming a non-zero angle with the first direction and typically orthogonal or substantially orthogonal to the first direction, the assembly of cells including a first string laterally overlapped by a second chain of the plurality of strings, so that a peripheral portion of the second string covers a peripheral portion of the first string, the first string and the second string being electrically insulated via an insulating region interposed between the respective peripheral portions of the first string and of the second string.

IPC Classes  ?

  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

72.

Method for fabricating radiation-hardened heterojunction photodiodes

      
Application Number 18381038
Status Pending
Filing Date 2023-10-16
First Publication Date 2024-04-25
Owner
  • THALES (France)
  • COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Demiguel, Stéphane
  • Reverchon, Jean-Luc
  • Benfante, Marco

Abstract

A method for fabricating an optoelectronic component includes at least one photodiode, the steps of the method making it possible to move the electric carrier collection field to the layer least sensitive to radiation, thus reducing the influence of irradiation on the dark current.

IPC Classes  ?

73.

OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME

      
Application Number 18276862
Status Pending
Filing Date 2022-02-11
First Publication Date 2024-04-18
Owner Commissariat à I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Dupont, Florian
  • Templier, Francois

Abstract

An optoelectronic device including a light-emitting diode covered with a photoluminescent conversion layer based on a perovskite material.

IPC Classes  ?

  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission

74.

COHERENT SAMPLING TRUE RANDOM NUMBER GENERATION IN FD-SOI TECHNOLOGY

      
Application Number 18483251
Status Pending
Filing Date 2023-10-09
First Publication Date 2024-04-18
Owner Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
Inventor
  • Benea, Licinius-Pompiliu
  • Pebay-Peyroula, Florian
  • Carmona, Mikael
  • Wacquez, Romain

Abstract

The present description concerns a random number generation circuit (2) of correlated sampling ring oscillator type comprising: two identical ring oscillators (RO1, R02) implemented in CMOS-on-FDSOI technology; a circuit (104) sampling and storing an output (O1) of one of the two oscillators (RO1) at a frequency of the other one of the two oscillators (R02) and delivering a corresponding binary signal (Beat); and a circuit (200) controlling back gates of PMOS and NMOS transistors of at least one delay element of at least one of the two oscillators (RO1, R02) based on a period difference between the two oscillators (RO1, R02).

IPC Classes  ?

  • H03K 3/84 - Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
  • H03K 5/134 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices with field-effect transistors

75.

GERMANIUM-BASED PLANAR PHOTODIODE WITH A COMPRESSED LATERAL PERIPHERAL ZONE

      
Application Number 18483594
Status Pending
Filing Date 2023-10-10
First Publication Date 2024-04-18
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Aliane, Abdelkader
  • Kaya, Hacile
  • Mehrez, Zouhir

Abstract

The invention relates to a planar photodiode 1 including a detection portion 10 made of a germanium-based material M0, and a peripheral lateral portion 3 including several materials stacked on top of one another, including a material M1 having a coefficient of thermal expansion lower than that of the material M0, and a material M2 having a coefficient of thermal expansion higher than or equal to that of the material M0. The intermediate region 13 includes a portion P1 surrounded by the material M1 and having tensile stresses. It also includes a portion P2 surrounded by the material M2 and having compressive stresses. This portion P2 surrounds a n doped box 12.

IPC Classes  ?

  • H01L 31/105 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

76.

DEVICE FOR ACQUIRING A 2D IMAGE AND A DEPTH IMAGE OF A SCENE

      
Application Number 18485181
Status Pending
Filing Date 2023-10-11
First Publication Date 2024-04-18
Owner Commissariat à I'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Deneuville, François
  • Jamin, Clémence

Abstract

A device for acquiring a 2D image and a depth image, including: a first sensor formed in and on a first semiconductor substrate and including regions of a material distinct from that of the substrate located in an interconnect stack in line with 2D image pixels of the first r sensor; and adjoining the first sensor, a second sensor formed in and on a second semiconductor substrate and including a plurality of depth pixels located opposite the regions of the first sensor, wherein each region includes a first portion having, in top view, a smaller surface area than that of a second portion, the material of the regions having an optical index greater than or equal to that of the material of the substrate.

IPC Classes  ?

77.

SIP-TYPE ELECTRONIC DEVICE AND METHOD FOR MAKING SUCH A DEVICE

      
Application Number 18486467
Status Pending
Filing Date 2023-10-13
First Publication Date 2024-04-18
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Coudrain, Perceval
  • Garnier, Arnaud
  • Pignol, Jeanne

Abstract

A SiP-type electronic device, including an electronic chip provided with an electrical interconnection face; a redistribution layer electrically coupled to the electrical interconnection face of the chip; electrical connection elements electrically coupled to the chip by the redistribution layer which is arranged between the chip and the connection elements; a first metal layer arranged on the side of a second face of the chip and secured to this second face; an encapsulation material arranged around the chip, between the redistribution layer and the first metal layer; a second metal layer including a first face secured by direct bonding to the first metal layer; a substrate arranged against a second face of the second metal layer.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
  • H01L 23/552 - Protection against radiation, e.g. light

78.

SYSTEM FOR POSITIONING AND MAINTAINING THE POSITION OF A REFERENCE SENSOR AROUND A MAGNETOENCEPHALOGRAPHY HELMET

      
Application Number 18547735
Status Pending
Filing Date 2022-02-17
First Publication Date 2024-04-18
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Labyt, Etienne
  • Fourcault, William
  • Paquin-Honore, Ilea
  • Laffont, Guilhem

Abstract

A system for positioning and maintaining a position of a reference sensor around a magnetoencephalography helmet. The system includes an arch comprising at least one fixing branch for fixing the arch to an MEG helmet, a support plate on which the branch is fixed, a sensor support post fixed to the support plate of the arch; and a locking component for fixing the reference sensor to the post in at least one position defining the position with respect to an MEG helmet.

IPC Classes  ?

  • A61B 5/245 - Detecting biomagnetic fields, e.g. magnetic fields produced by bioelectric currents specially adapted for magnetoencephalographic [MEG] signals
  • A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
  • A61B 90/00 - Instruments, implements or accessories specially adapted for surgery or diagnosis and not covered by any of the groups , e.g. for luxation treatment or for protecting wound edges

79.

OPTICAL FILTER FOR MULTISPECTRAL SENSOR

      
Application Number 18191550
Status Pending
Filing Date 2023-03-28
First Publication Date 2024-04-18
Owner
  • STMicroelectronics (Crolles 2) SAS (France)
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Abadie, Quentin
  • Villenave, Sandrine

Abstract

The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, a resonant cavity comprising a first transparent layer, interposed between second and third mirror layers, and a diffraction grating formed in the first layer, wherein at least one of the cavities has a different thickness than another cavity.

IPC Classes  ?

80.

THERMOSET MATERIALS OBTAINED FROM SPECIFIC PHTHALONITRILE RESINS FOR HIGH-TEMPERATURE APPLICATIONS

      
Application Number 18256503
Status Pending
Filing Date 2021-12-08
First Publication Date 2024-04-18
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Brandt, Damien
  • Chaussoy, Nathanaël
  • Gerard, Jean-Francois

Abstract

A thermoset material obtained from a curing by heat treatment of a resin that can be obtained by polycondensation, in basic medium, of at least one phthalonitrile compound bearing on its benzene ring at least one hydroxyl group.

IPC Classes  ?

81.

METHOD FOR PRODUCING AN INDIVIDUALIZATION ZONE OF AN INTEGRATED CIRCUIT

      
Application Number 18318023
Status Pending
Filing Date 2023-05-16
First Publication Date 2024-04-18
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Landis, Stefan
  • Exbrayat, Yorrick

Abstract

A method for producing an individualization zone of a microelectronic chip having a first and a second electrical track level and an interconnection level having vias includes providing the first level and a dielectric layer, randomly depositing particles on the dielectric layer, depositing an etching mask on the dielectric layer and the particles, and planarizing, so as to obtain a composite layer including the particles. The method also includes forming a lithographic layer having opening patterns, etching the composite layer through the opening patterns to form mask openings, then etching the dielectric layer through the mask openings, so as to obtain functional via openings and degraded via openings, and filling the via openings so as to form the vias of the interconnection level, said vias including functional vias at the functional openings and malfunctional vias at the degraded openings.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/311 - Etching the insulating layers

82.

METHOD FOR MANUFACTURING A THERMOELECTRIC STRUCTURE

      
Application Number 18485424
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-04-18
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Savelli, Guillaume
  • Baudry, Maxime
  • Roux, Guilhem

Abstract

A method for manufacturing a thermoelectric structure including the following steps: a) providing a substrate made from a first material, b) depositing a thermoelectric element made from a second material on the substrate, by additive manufacturing, preferably by SLS or PBF, c) thinning and cutting the substrate until a film made from the first material is obtained, by means of which a thermoelectric structure comprising a film and the thermoelectric element is obtained.

IPC Classes  ?

83.

METHOD FOR METALLISING A THERMOELECTRIC STRUCTURE

      
Application Number 18485471
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-04-18
Owner COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
Inventor
  • Savelli, Guillaume
  • Baudry, Maxime
  • Roux, Guilhem

Abstract

A method for manufacturing a thermoelectric structure including the following steps: a) providing a substrate, covered with a metal layer, b) forming a thermoelectric element on the metal layer, by additive manufacturing, preferably by SLS or PBF, and c) optionally removing the substrate, by means of which a thermoelectric structure, which comprises the metal layer and the thermoelectric element, is obtained.

IPC Classes  ?

84.

SYSTEM FOR FASTENING OPTICALLY PUMPED MAGNETOMETERS (OPM), AND ELASTOMER MATRIX WHICH INCORPORATES A SYSTEM PART INTENDED TO BE FIXED TO A MAGNETOENCEPHALOGRAPHY DEVICE

      
Application Number 18547740
Status Pending
Filing Date 2022-02-17
First Publication Date 2024-04-18
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Labyt, Etienne
  • Fourcault, William
  • Paquin-Honore, Llea
  • Laffont, Guilhem

Abstract

An OPM sensor fastening system includes a support socket for positioning the sensor, the support socket having a base and a housing for accommodating a portion of the OPM sensor, and a locking part for locking the sensor in the support socket, the locking part having an open base suitable for accommodating the base of the socket, a housing for accommodating a portion of the OPM sensor, and a removable partition suitable for letting the OPM sensor pass. The locking part is configured to press-fittingly cooperate with the support socket so as to blockingly wedge the OPM sensor in the longitudinal position relative to the socket.

IPC Classes  ?

  • A61B 5/245 - Detecting biomagnetic fields, e.g. magnetic fields produced by bioelectric currents specially adapted for magnetoencephalographic [MEG] signals
  • A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons

85.

SIMPLIFIED TANDEM STRUCTURE FOR SOLAR CELLS WITH TWO TERMINALS

      
Application Number 18257718
Status Pending
Filing Date 2021-12-13
First Publication Date 2024-04-11
Owner
  • COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
  • 3SUN S.R.L. (Italy)
Inventor
  • Puaud, Apolline
  • Matheron, Muriel
  • Munoz, Maria-Delfina

Abstract

A tandem photovoltaic structure including, from the rear face to the front face: a first solar cell—with a silicon heterojunction: a first layer of a first conductivity type made of amorphous silicon and a substrate of doped crystalline silicon disposed between two layers of intrinsic amorphous silicon, a recombination zone comprising a layer of nanocrystalline or monocrystalline silicon of the second conductivity type, a second solar cell comprising an active layer made of a perovskite material and a second layer of a second conductivity type. The recombination zone further includes a layer of the first conductivity type in contact with the active layer of the second cell or a layer of nanocrystalline or monocrystalline silicon of the first conductivity type in contact with the active layer of the second solar cell.

IPC Classes  ?

  • H10K 30/57 - Photovoltaic [PV] devices comprising multiple junctions, e.g. tandem PV cells

86.

METHOD FOR EVALUATING A TRANSMISSION LINE THROUGH AUTOMATIC ANALYSIS OF A REFLECTOGRAM

      
Application Number 18376097
Status Pending
Filing Date 2023-10-03
First Publication Date 2024-04-11
Owner COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Ravot, Nicolas
  • Naline, Baudouin
  • Blanchart, Pierre
  • Gregis, Nicolas

Abstract

A novel method for automatically analyzing reflectograms in order to classify impedance discontinuities detected via their temporal or spectral signatures into various categories relating to potential faults or other physical elements present on the cable. A method for detecting the mutual influence of neighboring pulses in a reflectogram in order to separate them so as to isolate them and characterize each pulse accurately.

IPC Classes  ?

  • G01R 31/08 - Locating faults in cables, transmission lines, or networks
  • G01R 31/11 - Locating faults in cables, transmission lines, or networks using pulse-reflection methods

87.

ANALOG-TO-TIME CONVERTER

      
Application Number 18473220
Status Pending
Filing Date 2023-09-23
First Publication Date 2024-04-11
Owner Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
Inventor
  • Mostafa, Ali
  • Badets, Franck
  • Hardy, Emmanuel

Abstract

The present disclosure relates to a converter (1) converting a voltage (Vin) into time. The converter comprises a direct path (100) including a first injection-locked oscillator (104) and a first circuit (106). The first circuit is configured for receiving an output signal (Φsens) of the first oscillator and a reference signal (Φ0), and for providing at least a first pulse signal (out) determined by a phase shift between the output signal (Φsens) of the first oscillator and the reference signal (Φ0). The converter further comprises a feedback loop (102) comprising a second circuit (108) configured for integrating said at least one first pulse signal (out).

IPC Classes  ?

  • G04F 10/10 - Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time

88.

SWITCH BASED ON A PHASE CHANGE MATERIAL

      
Application Number 18478778
Status Pending
Filing Date 2023-09-29
First Publication Date 2024-04-11
Owner Commissariat à l'Énergie Atomique et aux Énergies Altermatives (France)
Inventor
  • Clemente, Antonio
  • Charbonnier, Benoît
  • Dupre, Cécilia
  • Reig, Bruno

Abstract

A switch based on a phase change material including: a region in said phase change material that couples the first and second conductive electrodes of the switch; and a waveguide including a first end in line with a face of the region in said phase change material and a second end, opposed to the first end, designed to be illuminated by a laser source.

IPC Classes  ?

  • H10N 70/20 - Multistable switching devices, e.g. memristors
  • G02F 1/29 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the position or the direction of light beams, i.e. deflection
  • H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching

89.

MICRO-ELECTRO-MECHANICAL DEVICE

      
Application Number 18481509
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-04-11
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Joet, Loïc
  • Rey, Patrice

Abstract

A micro-electromechanical device includes a frame; a proof mass connected to the frame through a first mechanical link which allows pivoting of the proof mass to relative to the frame about a first axis of rotation parallel to a mean plane of the frame; and a lever for detecting pivoting of the mass, connected to the proof mass through a second mechanical link allowing rotation of the lever relative to the proof mass about a second axis. The second link includes two walls connecting perpendicularly to each other, one to the lever and the other to the proof mass, one of the walls being parallel to the second axis of rotation.

IPC Classes  ?

  • G01C 19/5747 - Structural details or topology the devices having two sensing masses in anti-phase motion each sensing mass being connected to a driving mass, e.g. driving frames

90.

OPTO-MECHANICAL STRUCTURE AND ASSOCIATED MANUFACTURING METHODS

      
Application Number 18481751
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-04-11
Owner COMMISSARIAT À L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Furcatte, Thomas
  • Sansa Perna, Marc
  • Hentz, Sébastien
  • Kazar Mendes, Munique

Abstract

An opto-mechanical structure includes a substrate extending along a plane; a support element arranged on the substrate; a conductive element adapted to create an electric field oriented perpendicularly to the plane of the substrate; and an opto-mechanical resonator. The opto-mechanical resonator includes a mechanically movable element made of a piezoelectric material and arranged on the support element, the piezoelectric material being chosen so that the electric field created by the conductive element when the same is subjected to an electric potential causes a displacement of the movable element; an optical resonator coupled to the movable element. The conductive element is located above or below the movable element, at a non-zero distance from the movable element, the conductive element and the movable element having a surface facing each other.

IPC Classes  ?

  • G02B 26/00 - Optical devices or arrangements for the control of light using movable or deformable optical elements
  • B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
  • H10N 30/20 - Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators

91.

PROCESS FOR MANUFACTURING A PHASE CHANGE MATERIAL

      
Application Number 18308147
Status Pending
Filing Date 2023-04-27
First Publication Date 2024-04-04
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Terebenec, Damien
  • Noe, Pierre-Olivier

Abstract

A method for manufacturing a phase change stack having a crystallographic structure made of layers separated by van der Waals pseudo-gaps, may include: providing a substrate; forming the stack on the substrate, including (i) forming the first layer, and (ii) forming the second layer on the first layer. Advantageously, after formation of the stack, at least one curing annealing is carried out. The curing annealing may be such that the stack has, after annealing, a nominal defect rate less than at least 50% of an initial defect rate of the stack.

IPC Classes  ?

  • H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
  • C30B 29/68 - Crystals with laminate structure, e.g. "superlattices"
  • C30B 33/02 - Heat treatment
  • H10N 70/20 - Multistable switching devices, e.g. memristors

92.

METHOD FOR PRODUCING AN INDIVIDUALIZATION ZONE OF AN INTEGRATED CIRCUIT

      
Application Number 18318044
Status Pending
Filing Date 2023-05-16
First Publication Date 2024-04-04
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Landis, Stefan
  • Exbrayat, Yorrick

Abstract

A method for producing an individualization zone of a microelectronic chip having a first and a second electrical track level and an interconnection level including vias, includes providing the first level and a dielectric layer, forming an etching mask on the dielectric layer, randomly depositing particles on the etching mask, and forming a lithographic layer having opening patterns. The mask layer is etched through opening patterns to form mask openings, then the dielectric layer is etched through the mask openings, so as to obtain functional via openings and degraded via openings. The via openings are filled so as to form the vias of the interconnection level, the vias including functional vias at the functional openings and malfunctional vias at the degraded openings.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

93.

DATA LOGIC PROCESSING CIRCUIT INTEGRATED IN A DATA STORAGE CIRCUIT

      
Application Number 18373231
Status Pending
Filing Date 2023-09-26
First Publication Date 2024-04-04
Owner COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Billoint, Olivier
  • Grenouillet, Laurent

Abstract

A data storage circuit includes an array of memory cells; a logic processing circuit configured to carry out a logic operation having N binary data as operands stored in N input memory cells, with N≥2, the second input/output nodes of the input memory cells being linked by a common bit line, the logic processing circuit comprising: a transimpedance amplifier stage configured to supply an analogue read signal from the voltage of the common bit line; a comparator intended to compare the analogue read signal with a first adjustable reference voltage in order to generate a digital output signal corresponding to the result of the logic operation; a control unit configured to adjust the reference voltage to an amplitude selected from among N distinct predetermined amplitudes, depending on the type of logic operation.

IPC Classes  ?

  • G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

94.

Device for locating stored objects via RFID detection

      
Application Number 18375467
Status Pending
Filing Date 2023-09-30
First Publication Date 2024-04-04
Owner COMMISSARIAT A L’ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Descharles, Mélanie
  • Thomas, Thierry
  • Frassati, François

Abstract

A device for locating objects stored in a storage unit includes a plurality of storage spaces, each object being equipped with an RFID tag, the object-locating device comprising: a plurality of inhibitor circuits each intended to be placed in an associated storage space and configured to prevent the RFID tag of the object from being read by an RFID reader, a control unit configured to control activation of the inhibitor circuits in a predetermined activation sequence; a locating unit configured to control the RFID reader, and to receive, in each step of the activation sequence, a list of identifiers of the objects stored in the storage unit, the list being supplied by the RFID reader, and configured to identify the storage space of each object based on the lists of identifiers and on the activation sequence.

IPC Classes  ?

  • G06K 7/10 - Methods or arrangements for sensing record carriers by corpuscular radiation
  • G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinations; Position-fixing by co-ordinating two or more distance determinations using radio waves
  • G06Q 10/087 - Inventory or stock management, e.g. order filling, procurement or balancing against orders

95.

METHOD FOR DETERMINING THE OPERATING STATE OF A LIGHT-EMITTING IMPLANT

      
Application Number 18476487
Status Pending
Filing Date 2023-09-28
First Publication Date 2024-04-04
Owner
  • Commissariat à l'Energie Atomique et aux Energies Alternatives (France)
  • CENTRE HOSPITALIER UNIVERSITAIRE GRENOBLE ALPES (France)
  • UNIVERSITE GRENOBLE ALPES (France)
Inventor
  • Bleuet, Pierre
  • Chabrol, Claude
  • Moro, Cécile
  • Chabardes, Stephan
  • Benabid, Alim Louis

Abstract

A method for determining the operating state of a light-emitting implant implanted in the brain of a living being, the light-emitting implant including a light source responsible for emitting light into the brain of the living being, the method using a diagnosing device that includes a receiver of a light signal transmitted through a first eye of the living being and a device for determining the operating state of the light-emitting implant based on the received transmitted light signal.

IPC Classes  ?

96.

SUPERCAPACITORS, AND METHODS OF THEIR MANUFACTURE

      
Application Number 18532419
Status Pending
Filing Date 2023-12-07
First Publication Date 2024-04-04
Owner
  • Murata Manufacturing Co., Ltd. (Japan)
  • Commissariat A L'Energie Atomique Et Aux Energies Alternatives (France)
Inventor
  • Oukassi, Sami
  • Sallaz, Valentin
  • Voiron, Frédéric

Abstract

A supercapacitor that includes: a first electrode; a second electrode; and a composite solid electrolyte disposed between the first electrode and the second electrode. The composite solid electrolyte includes a dielectric matrix and an ionic conductor disposed in channels/pores in the dielectric matrix. Methods of fabricating such supercapacitors are also disclosed.

IPC Classes  ?

  • H01G 11/56 - Solid electrolytes, e.g. gels; Additives therein
  • H01G 11/06 - Hybrid capacitors with one of the electrodes allowing ions to be reversibly doped thereinto, e.g. lithium ion capacitors [LIC]
  • H01G 11/50 - Electrodes characterised by their material specially adapted for lithium-ion capacitors, e.g. for lithium-doping or for intercalation
  • H01G 11/84 - Processes for the manufacture of hybrid or EDL capacitors, or components thereof

97.

DETECTING BETA-LACTAMASE ENZYME ACTIVITY

      
Application Number 18262523
Status Pending
Filing Date 2022-01-25
First Publication Date 2024-04-04
Owner
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
  • UNIVERSITE PARIS-SACLAY (France)
Inventor
  • Volland, Herve
  • Moguet, Christian
  • Naas, Thierry

Abstract

It is essential to have efficient, simple, quick and transportable tools for reliably identifying bacteria that are multiresistant to antibiotics, more specifically extended spectrum β-lactamase (ESBL)-producing Enterobacteriaceae, which are the most widespread among Enterobacteriaceae. The present invention meets this requirement through its ease of use and its speed. The invention is based on detecting the enzyme activity of β-lactam hydrolysis using an antibody capable of discriminating between the intact form of the β-lactam ring of a β-lactam and its hydrolysis product. This antibody can be used in kits and methods enabling for rapidly detecting (in less than one hour), without using expensive equipment (a small strip visible to the naked eye), the presence of bacteria producing penicillin-type, plasmid-mediated or hyper-produced AmpC enzymes, of ESBL or carbapenemase from colonies or in a sample.

IPC Classes  ?

  • C12Q 1/34 - Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions involving hydrolase
  • C12Q 1/18 - Testing for antimicrobial activity of a material

98.

ARCHITECTURE FOR InGaAs/GaAsSb SUPERLATTICES ON AN InP SUBSTRATE

      
Application Number 18265654
Status Pending
Filing Date 2021-11-26
First Publication Date 2024-04-04
Owner
  • LYNRED (France)
  • COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Evirgen, Axel
  • Reverchon, Jean-Luc

Abstract

A device for detecting infrared radiation includes at least one pixel comprising: a first superlattice composed of the repetition of an elementary group comprising: a first layer having a first bandgap and a first conduction-band minimum; at least a second layer having a second bandgap and a second conduction-band minimum strictly lower than the first conduction-band minimum; a third layer having a third bandgap narrower than the first and second bandgaps and a third conduction-band minimum strictly lower than the second conduction-band minimum. The elementary group is produced in a first stacking configuration in the following order: the second layer, the third layer, the second layer, then the first layer; or in a second stacking configuration such that the third layer is confined between the first and second layers.

IPC Classes  ?

  • H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
  • H01L 27/146 - Imager structures
  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/09 - Devices sensitive to infrared, visible or ultra- violet radiation

99.

ELECTRONIC CHIP WITH UBM-TYPE METALLIZATION

      
Application Number 18477544
Status Pending
Filing Date 2023-09-28
First Publication Date 2024-04-04
Owner Commissariat à l'Énergie Atomique et aux Énergies Alternatives (France)
Inventor
  • Lobre, Clément
  • Serres, Eva
  • Dupre, Ludovic

Abstract

An electronic chip including a substrate and, on the side of one face of the substrate, a metal pad intended to receive a soldering material, the pad including, in order from said face of the substrate, a first metal layer, an electrically conductive barrier layer, and a second metal layer, wherein an electrically insulating barrier layer is arranged on, and in contact with, the sidewall of the first metal layer over the entire periphery of the metal pad.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

100.

MULTISPECTRAL REFLECTION IMAGING SYSTEM

      
Application Number 18478303
Status Pending
Filing Date 2023-09-29
First Publication Date 2024-04-04
Owner COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (France)
Inventor
  • Le Perchec, Jérôme
  • Dupoy, Mathieu

Abstract

An imaging device (100) configured to image a sample (102), comprising: a light source (104) emitting a light; a light deflection device configured to deflect the light emitted by the light source towards the sample, comprising a material portion (106) provided with a first main face (108) arranged opposite the sample (102), a second main face (110), and a first lateral face (112) towards which the light is emitted by the light source; an imager (118) having a detection face (122) arranged opposite the second main face and intended to receive the light backscattered by the sample; An imaging device (100) configured to image a sample (102), comprising: a light source (104) emitting a light; a light deflection device configured to deflect the light emitted by the light source towards the sample, comprising a material portion (106) provided with a first main face (108) arranged opposite the sample (102), a second main face (110), and a first lateral face (112) towards which the light is emitted by the light source; an imager (118) having a detection face (122) arranged opposite the second main face and intended to receive the light backscattered by the sample; wherein one amongst the main faces is provided with oblique portions (114) each configured to deflect a portion of the received light towards the sample (102), and with planar portions (116) configured to let the light backscattered by the sample pass, and wherein each pixel (120) of the imager (118) is arranged opposite one of the planar portions (116) of said one amongst the first and second main faces (108, 110).

IPC Classes  ?

  • G01N 21/47 - Scattering, i.e. diffuse reflection
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