Western Digital Technologies, Inc.

United States of America

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G06F 3/06 - Digital input from, or digital output to, record carriers 257
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1.

Read Sensor With Ordered Heusler Alloy Free Layer and Semiconductor Barrier Layer

      
Application Number 18227537
Status Pending
Filing Date 2023-07-28
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Zheng, Yuankai
  • Okamura, Susumu
  • York, Brian R.
  • Diao, Zhitao
  • Freitag, James Mac

Abstract

Embodiments of the present disclosure generally relate to a read sensor utilized in a read head. The read sensor comprises an amorphous break layer disposed on a shield, a seed layer disposed on the amorphous break layer, a first ferromagnetic layer disposed on the seed layer, a barrier layer disposed on the first ferromagnetic layer, and a second ferromagnetic layer disposed on the barrier layer. The amorphous break layer comprises CoFeBTa, the seed layer comprises RuAl, and the barrier layer comprises a semiconductor material, such as ZnSe, ZnTe, ZnO, CuSe, or CuInGaSe. The semiconductor barrier layer reduces the resistance-area product of the read sensor. The amorphous break layer breaks the texture between the shield, which has a FCC texture, and the seed layer, which has a BCC texture. The BCC texture of the seed layer is then inherited by the remaining layers disposed over the seed layer.

IPC Classes  ?

  • G11B 5/31 - Structure or manufacture of heads, e.g. inductive using thin film
  • G11B 5/39 - Structure or manufacture of flux-sensitive heads using magneto-resistive devices

2.

MEMORY DEVICE AND METHOD OF ASSEMBLING SAME

      
Application Number 18356838
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Wong, Chee Seng
  • Chin, Yoong Tatt
  • Teng, Wei Chiat

Abstract

Technology for a memory device having memory dies flip-chip bonded to one or more interposers that are mounted to a system board is disclosed. The memory device may be an SSD and the system board may be an M.2 board. A memory controller die may be bonded to one of the interposer boards. In one aspect, the memory controller die is flip-chip bonded to the interposer board. In one aspect, a heat sink is attached to a top surface of the flip-chip bonded controller die and to top surfaces of a group of the memory dies. Neither the memory dies nor the interposers are covered with a mold compound. Performance of the memory device is improved by, for example, lower inductance and improved heat dissipation.

IPC Classes  ?

  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

3.

RAISEABLE PROFILE-BASED ACCESS FOR MEDIA CONTENT

      
Application Number 18446442
Status Pending
Filing Date 2023-08-08
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Shukla, Arun Kumar
  • Muthiah, Ramanathan

Abstract

A media playback device is configured to control access to a plurality of files. The media playback device includes memory configured to store a plurality of files, the plurality of files including at least a first set of files and a second set of files, the second set of files having a higher security level the first set of files. The media playback device also includes control circuitry that can be configured to receive a first login from a user, determine that the first login is associated with a user profile associated with the first set of files and the second set of files, provide access to the first set of files in response to validating the first login while keeping the second set of files locked, receive a second login, and provide access to the second set of files in response to validating the second login.

IPC Classes  ?

  • G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
  • G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules

4.

ERROR CORRECTION SYSTEMS AND METHODS FOR DNA STORAGE

      
Application Number 18356104
Status Pending
Filing Date 2023-07-20
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Avraham, David
  • Zamir, Ran
  • Bazarsky, Alexander

Abstract

A DNA-based storage system includes an error correction system operable to: (a) identify a DNA codeword from a DNA sequencing operation; (b) calculate an initial syndrome weight; (c) determine that the initial syndrome weight is greater than a predetermined threshold; (d) perform an alignment alteration in the information segment by: (i) selecting a skew point within the information segment; (ii) performing an indel operation on the information segment at the skew point; (iii) calculating a modified syndrome weight; (iv) comparing the initial syndrome weight with the modified syndrome weight; and (v) incorporating the indel operation into the information segment when the comparing indicates an improvement in the modified syndrome weight; (e) decode the modified codeword; and (f) transmit the contents of the output file to a computing device, the output file representing user data stored within the DNA molecule.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G16B 30/00 - ICT specially adapted for sequence analysis involving nucleotides or amino acids
  • G16B 50/30 - Data warehousing; Computing architectures

5.

DE-FRAGMENTATION ACCELERATION USING OVERLAP TABLE

      
Application Number 18355097
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Segev, Amir
  • Benisty, Shay

Abstract

The present disclosure generally relates to improved fragment processing while command fetching is on-going. Rather than stopping command fetching, the controller uses a short fragment list, while command fetching can continue, to add a fragment. The controller first adds new fragments to the short list with the fragment information. The information is then checked for size. If the fragment information is smaller than the short fragment list, then the fragment list is updated during command fetching. As a command arrives, the controller does a binary search of a sorted fragment list. The results are stored and later scanned by the controller for matches with the short fragment list. If there are no matches in the short list, then the controller uses the stored results to update the search result. If there is a match in the short list then the controller uses the new results to update the search list.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

6.

DATA STORAGE DEVICE BACKUP

      
Application Number 18365017
Status Pending
Filing Date 2023-08-03
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Nayak, Dattatreya
  • Shukla, Arun

Abstract

This disclosure relates to systems, methods, and data storage devices, such as a data storage device comprising a data path and a controller. The data path comprises a data port to transmit data between a host computer system and the data storage device. The data storage device registers with the host computer system as a block data storage device. A non-volatile storage medium stores encrypted user content data. A cryptography engine is connected between the data port and the storage medium and uses cryptographic key data to encrypt and decrypt user content data. The controller is configured to send the encrypted user content data for back-up storage external to the data storage device as encrypted by the cryptographic key data, and communicate with a user device over a communication channel that is different from the data path, to send the cryptographic key data for decryption of the encrypted user content external to the data storage device.

IPC Classes  ?

7.

SEGREGATING LARGE DATA BLOCKS FOR DATA STORAGE SYSTEM

      
Application Number 18449428
Status Pending
Filing Date 2023-08-14
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Yang, Niles
  • Linnen, Daniel J.
  • Hahn, Judah Gamliel

Abstract

Methods and apparatus for efficiently handling large data files and their updates in NAND memory. In one example, provided is a data-storage system configured to reduce the frequency of data relocations by segregating a large data file into a plurality of subfiles. The size of such subfiles is appropriately selected to reduce the probability of occurrence for host-relocation conflicts and the magnitude of write amplification, thereby enabling the data-storage system to provide better quality of service while substantially maintaining acceptable levels of other pertinent performance characteristics. In some examples, a sequence of host read-modify-write commands is handled by generating a copy of implicated subfiles in a data buffer, applying subfile updates to the copy in the data buffer in accordance with the sequence, and relocating the implicated subfiles in the NAND memory using the updated versions thereof from the data buffer.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

8.

SYSTEMS AND METHODS FOR IMPROVING FIND LAST GOOD PAGE PROCESSING IN MEMORY DEVICES

      
Application Number 18356693
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Gueta, Asaf
  • Star, Arie
  • Fainzilber, Omer
  • Sharon, Eran

Abstract

A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also determines an initial last good page based on the coarse inspection and performs a fine inspection of at least one page based on a second number of bytes greater than the first number of bytes. The fine inspection validates the initial last good page and identifies the initial last good page as an actual last good page of the dirty block.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

9.

MEMORY PREFETCH BASED ON MACHINE LEARNING

      
Application Number 18231730
Status Pending
Filing Date 2023-08-08
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Sun, Chao
  • Wang, Qingbo
  • Qin, Minghai
  • Hofmann, Jaco
  • Kulkarni, Anand
  • Vucinic, Dejan
  • Bandic, Zvonimir

Abstract

A memory device includes a first memory and a second memory that caches data stored in the first memory. At least one controller of the memory device receives page fault information from a host. The page fault information results from a request for data by the host that is stored in the first memory but is not cached in the second memory when requested by the host. The memory device uses the received page fault information for one or more inputs into a prefetch model trained by Machine Learning (ML) to generate at least one inference. Based at least in part on the at least one inference, prefetch data is cached in the second memory. In one aspect, the page fault information is used to train the prefetch model. In another aspect, the page fault information includes at least one virtual address used by the host for the requested data.

IPC Classes  ?

  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06N 20/00 - Machine learning

10.

STORAGE OF CONTROL DATA INFORMATION

      
Application Number 18447774
Status Pending
Filing Date 2023-08-10
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Swami, Maharudra Nagnath
  • Divya, G K
  • Menezes, Naveen
  • Jain, Nitin

Abstract

Methods for storing control information for memory operations within spare physical blocks. During formatting of a data storage device, spare memory blocks may be identified within memory dies and placed into a spare block pool. Upon initiation of a block exchange event for a control block, a controller determines whether a spare block is available in the spare block pool. When a spare block is available, data from the control block is copied to the spare block to generate a debug block. The control block may be a MasterIndexPage block. When a spare block is not available, the controller may erase information stored in an oldest debug memory block and copy data from the control block to the oldest debug memory block.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

11.

VALLEY SEARCH SCAN BIT LINE SELECTION METHOD TO ADDRESS MEMORY HOLE AND STRING PROCESS VARIATION

      
Application Number 18219456
Status Pending
Filing Date 2023-07-07
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Chen, Chin-Yi
  • Kumar, Ravi
  • Dutta, Deepanshu

Abstract

A memory apparatus and operating method are provided. The apparatus includes memory cells connected to one of a plurality of word lines and disposed in memory holes coupled to bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the bit lines and for a group of the memory cells divided into a plurality of subsets, is configured to determine whether comparatively fewer read errors of the memory cells arise while pre-charging ones of the bit lines associated with each of the plurality of subsets. The control means is also configured to pre-charge ones of the bit lines associated with one the plurality of subsets with comparatively fewer read errors and read the memory cells associated therewith during a scan operation.

IPC Classes  ?

  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

12.

PIVOT-TO-ENCLOSURE FASTENING FOR REDUCING TORSIONAL VIBRATION OF ACTUATOR COIL IN HARD DISK DRIVE

      
Application Number 18128862
Status Pending
Filing Date 2023-03-30
First Publication Date 2024-06-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Takabayashi, Ko
  • Eguchi, Hajime
  • Sumiya, Takeji

Abstract

A hard disk drive includes a rotary actuator installed about a pivot having a hollow pivot shaft having a pivot shaft length, a base having a pivot boss shaft including an internal threaded portion and disposed within the pivot shaft, and a screw coupled with the threaded portion of the pivot boss shaft through a cover, where the screw has a fastening depth at which center threads of the threaded portion of the pivot boss shaft are coupled with screw threads at 66% or more of the pivot shaft length. Thus, the thermal expansion of the pivot boss shaft at high temperatures is inhibited and the corresponding axial fastening force of the screw is maintained, thereby inhibiting increasing coil torsion mode gain and lowering of the actuator main resonance frequency and consequent closer coupling with the coil torsion mode at high temperatures.

IPC Classes  ?

  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 25/04 - Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing using flat record carriers, e.g. disc, card

13.

DATA STORAGE DEVICE AND METHOD FOR SWAP DEFRAGMENTATION

      
Application Number US2023076019
Publication Number 2024/118256
Status In Force
Filing Date 2023-10-04
Publication Date 2024-06-06
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Linnen, Daniel J.
  • Muthiah, Ramanathan
  • Hahn, Judah Gamliel

Abstract

A data storage device stores files in its memory. The files may be logically fragmented in that various parts of a given file may be located in non-continuous logical addresses, which can be disadvantageous. The host can send a request to the data storage device to reduce such logical fragmentation. For example, the host can send a swap command to the data storage device, in response to which the data storage device swaps the logical addresses of data fragments of two different files. This results in the logical address of one or both of the data fragments being continuous with the logical address of another data fragment of the same file. This logical address swap can take place without physically moving the data in the memory.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

14.

DATA STORAGE DEVICE WITH MAPPING AND MITIGATION OF LASER MODE HOP EFFECTS IN HEAT-ASSISTED MAGNETIC RECORDING (HAMR)

      
Application Number US2023076022
Publication Number 2024/118257
Status In Force
Filing Date 2023-10-04
Publication Date 2024-06-06
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Knigge, Bernhard E.
  • Haralson, Phillip S.
  • Ito, Naoto
  • Burton, Derrick

Abstract

Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position a selected head among one or more heads proximate to a corresponding disk surface among the one or more disks; and one or more processing devices. The one or more processing devices are configured to generate a map of laser mode hop effects across the corresponding disk surface, for the selected head. The one or more processing devices are further configured to apply a laser mode hop mitigation in operating the selected head, based on the map of laser mode hop effects.

IPC Classes  ?

  • G11B 7/1263 - Power control during transducing, e.g. by monitoring
  • G11B 5/588 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on tapes by controlling the position of the rotating heads
  • G11B 5/73 - Base layers
  • G11B 5/55 - Track change, selection, or acquisition by displacement of the head
  • G11B 7/127 - Lasers; Multiple laser arrays

15.

QoS OPTIMIZATION BY USING DATA TRACKING MODULE

      
Application Number US2023076016
Publication Number 2024/112457
Status In Force
Filing Date 2023-10-04
Publication Date 2024-05-30
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Ionin, Michael
  • Bazarsky, Alexander
  • Hahn, Judah Gamliel

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. When data received by the controller, from a host device or from a non-volatile memory of the data storage device, the controller maintains table tracking the location of the data. The table may include a current location of the data in a volatile memory of the controller or the data storage device as well as the current location of the data a latch of the non-volatile memory. The table may further associate the location with a logical block address, such that when the host device requests the data not yet programmed to the non-volatile memory or data that is part of a data relocation operation, the controller may utilize the table to locate the relevant data and provide the data to the host device.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

16.

HEAT-ASSISTED MAGNETIC RECORDING (HAMR) HEAD WITH MAIN POLE HAVING NARROW POLE TIP WITH PLASMONIC LAYER

      
Application Number US2023025561
Publication Number 2024/107243
Status In Force
Filing Date 2023-06-16
Publication Date 2024-05-23
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Matsumoto, Takuya

Abstract

A heat-assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) with an output tip at the GBS and a main magnetic pole with a pole tip at the GBS. The pole tip has a narrow cross-track width that can be substantially the same as the cross-track width of the NFT output tip. A plasmonic layer is located between the main pole and the NFT and has a tip at the GBS between the main pole tip and the NFT output tip. The plasmonic layer may also be located on the cross-track sides of the main pole and the main pole tip.

IPC Classes  ?

  • G11B 5/73 - Base layers
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers

17.

PREHEATING LASER DIODES WITH REVERSE BIAS FOR HAMR DISK DRIVES

      
Application Number US2023076012
Publication Number 2024/107498
Status In Force
Filing Date 2023-10-04
Publication Date 2024-05-23
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Schreck, Erhard
  • Rajauria, Sukumar
  • Smith, Robert
  • Poss, Joey M.

Abstract

A data storage device may include one or more disks, an actuator arm assembly comprising one or more disk heads, at least one laser diode positioned inside a corresponding laser diode cavity, a preamplifier, and one or more processing devices. The one or more processing devices are configured to: generate a reverse bias; apply, using the preamplifier, the reverse bias to the at least one laser diode to preheat a corresponding laser diode cavity to a target temperature prior to a write operation; control transition of the preamplifier from applying the reverse bias to applying a forward bias to the at least one laser diode; and activate the at least one laser diode to begin the write operation.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

18.

HIBERNATE EXIT TIME FOR UFS DEVICES

      
Application Number US2023075884
Publication Number 2024/102532
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-16
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Ganon, Doron
  • Lerner, Eitan

Abstract

Rather than waiting on a squelch to detect the difference in the state from steady to floating, this disclosure suggests using the time from when a reference clock is turned on to begin the process to exit the hibernation state. The reference clock is turned off while a data storage device is in the hibernation state to save power. Once the host is ready for the device to exit the hibernation state, the reference clock is turned on. The reference clock is monitored for the change. Once the reference clock is on, the data storage device returns to a steady state. In the ready state, the data storage device has a shortened ready time. Once the ready time is complete, the data storage device may now exit the hibernation state without waiting on squelch detection or a hibernation exit request from the host.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

19.

ZONE-BASED GARBAGE COLLECTION IN ZNS SSDS

      
Application Number US2023075885
Publication Number 2024/102533
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-16
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Deora, Aakar
  • Kochar, Navin
  • Raja Murthy, Sampath Kumar
  • Kashyap, Gursimran

Abstract

Aspects of a storage device are provided including zone-based GC in a ZNS. The storage device includes a NVM and a controller. The NVM includes first blocks, second blocks, and third blocks. The controller creates a first superblock including the first blocks, a second superblock including the second blocks, and a third superblock including the third blocks. The controller allocates a first sub-drive including the first superblock for storing data overwrites and a second sub-drive including the second and third superblocks for storing sequential data in the NVM. During GC for superblocks respectively including data for a specific zone, the controller relocates written data for this zone from the first and third superblocks to the second superblock while refraining from relocating data associated with other zones from the first superblock to the second superblock. As a result, storage device cost, overprovisioning, and WAF may be reduced.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 3/06 - Digital input from, or digital output to, record carriers

20.

FAST EXECUTION OF BARRIER COMMAND

      
Application Number US2023075881
Publication Number 2024/097492
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-10
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Segev, Amir
  • Benisty, Shay
  • Sela, Rotem

Abstract

The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

21.

WRITE BUFFER LINKING FOR EASY CACHE READS

      
Application Number US2023075882
Publication Number 2024/097493
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-10
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Hahn, Judah Gamliel

Abstract

The present disclosure generally relates to improved optimization of a cache lookup operation by structuring the write cache buffers differently using a link-list. Rather than executing a read command first and then executing a write command only after the read command is executed, this disclosure suggests reordering the command executions. A device waits before executing the read command giving the opportunity to obtain the overlap write command. The device then reorders the command execution and executes first the write command and then executes the read command by accessing the write cache instead of the NAND. When two write commands need to be executed consecutively, the link-list operation is used. The controller finds the relevant buffer in the cache that is needed and overwrites the buffer with the new data. The new data is then written to the cache without accessing the cache multiple times.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

22.

STORAGE SYSTEM AND METHOD FOR CIRCUIT-BOUNDED-ARRAY-BASED TIME AND TEMPERATURE TAG MANAGEMENT AND INFERENCE OF READ THRESHOLDS

      
Application Number US2023075883
Publication Number 2024/097494
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-10
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Bazarsky, Alexander
  • Navon, Ariel
  • Sharon, Eran
  • Avraham, David
  • Yanuka, Nika
  • Alrod, Idan

Abstract

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

23.

HOST INDEPENDENT FORMATTING OF STORAGE DEVICES

      
Application Number US2023075297
Publication Number 2024/091761
Status In Force
Filing Date 2023-09-28
Publication Date 2024-05-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Puthamparambil Jayaraj, Prajual

Abstract

A data storage device is enabled to independently self-format, without requiring a connected host device during the active formatting process. The storage device includes a data interface configured to receive power from the host device or a wall charger, non-volatile storage media, and control circuitry. The control circuitry is configured to receive first power from the host device, receive instructions from the host device to perform a format operation, save the instructions to perform the format operation, and cease receiving the first power from the host device. The control circuitry is further configured to receive second power from the wall charger and, in response to retrieving the saved instructions, initiate the format operation on the non-volatile storage media.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

24.

USING CONTROL BUS COMMUNICATION TO ACCELERATE LINK NEGOTIATION

      
Application Number US2023075298
Publication Number 2024/091762
Status In Force
Filing Date 2023-09-28
Publication Date 2024-05-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Moshe, Eran
  • Shmaya, Shuli
  • Edwards, Barrett

Abstract

Systems and methods for devices connected by a control bus to share configuration data for accelerating physical link negotiation for a peripheral interface are described. Computer devices, such as data storage devices, may include a peripheral interface configured to connect to a host system and a control bus interface to connect to a control bus. Other devices on the same control bus may establish peer communication through the control bus interface to share configuration data, such as coefficients for physical link negotiation of the peripheral interface. To accelerate reestablishing communication through the peripheral interface, the device may receive previously stored configuration data from another device over the control bus.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

25.

NAND DIE WITH WIRE-BOND INDUCTIVE COMPENSATION FOR ALTERED BOND WIRE BANDWIDTH IN MEMORY DEVICES

      
Application Number US2023075300
Publication Number 2024/091763
Status In Force
Filing Date 2023-09-28
Publication Date 2024-05-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Contreras, John
  • Vodrahalli, Nagesh
  • Mobin, Md. Sayed

Abstract

A storage device includes a substrate of a memory package that includes a first pin pad, a controller mounted on the substrate and electrically connected to the first pin pad, the controller being configured to manage data communications on a data channel, and a first memory die. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

26.

DATA STORAGE DEVICE AND METHOD FOR REDUCING FLUSH LATENCY

      
Application Number US2023075301
Publication Number 2024/091764
Status In Force
Filing Date 2023-09-28
Publication Date 2024-05-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Sela, Rotem
  • Soffer, Meytal
  • Druck, Asher

Abstract

A data storage device has a cache and a non-volatile memory. Instead of flushing the entire cache to the non-volatile memory in response to a command from a host, the data storage device flushes only the cached data that is associated with an identifier provided by the host. This allows the cached data associated with the identifier to be flushed more quickly. The data storage device can also prioritize queued commands that are associated with the identifier.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

27.

ADVANCED ULTRA LOW POWER ERROR CORRECTING CODE ENCODERS AND DECODERS

      
Application Number US2023075174
Publication Number 2024/086433
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-25
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Pele, Ofir
  • Achtenberg, Stella
  • Zamir, Ran
  • Fainzilber, Omer

Abstract

Advanced ultra-low power error correcting codes are generated using soft quantization and lattice interpolation based on clock and Syndrome Weight. Reinforcement learning may be used to generate threshold values for flipping bits for low density parity check Ultra-Low Power error correction codes. The threshold values can be generated offline and downloaded to a storage device or generated while the storage device is in use.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

28.

SENSITIVITY AMPLIFICATION TECHNIQUES FOR MAGNETOCHEMICAL SENSORS

      
Application Number US2023075171
Publication Number 2024/081506
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-18
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Bedau, Daniel
  • Elias, Alexander

Abstract

A device may include a fluid region. A device may also include a magnetochemical sensor for detecting magnetic particles in the fluid region, wherein the magnetochemical sensor comprises: a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer situated between and coupled to the first ferromagnetic layer and the second ferromagnetic layer. A device may further include a current-carrying structure for drawing the magnetic particles in the fluid region toward the magnetochemical sensor, wherein: the current-carrying structure consists of a single, undivided structure, and the current-carrying structure is configured to carry a current in at least one direction that is substantially parallel to an in-plane axis or a longitudinal axis of the magnetochemical sensor. The magnetochemical sensor may be one of a plurality of magnetochemical sensors in a sensor array.

IPC Classes  ?

  • G01N 27/74 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables of fluids
  • G01R 33/12 - Measuring magnetic properties of articles or specimens of solids or fluids

29.

READ COLLISION AVOIDANCE IN SEQUENTIAL MIXED WORKLOADS

      
Application Number US2023075170
Publication Number 2024/076853
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Hutchison, Neil
  • Liu, Haining
  • Lo, Jerry
  • Gorobets, Sergey Anatolievich

Abstract

A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern. The sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies. The sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, thereby reducing read collisions.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

30.

AROMATIC AND AROMATIC-LIKE CONTAINING MEDIA LUBRICANTS FOR DATA STORAGE DEVICES

      
Application Number US2023075880
Publication Number 2024/077021
Status In Force
Filing Date 2023-10-03
Publication Date 2024-04-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • He, Xingliang
  • Wen, Jianming
  • Lee, Charles Cheng-Hsing

Abstract

mfpqff 222n2mfpqq.

IPC Classes  ?

  • C10M 105/54 - Lubricating compositions characterised by the base-material being a non-macromolecular organic compound containing halogen containing carbon, hydrogen, halogen and oxygen
  • G11B 5/725 - Protective coatings, e.g. anti-static containing a lubricant
  • C10N 40/18 - Electric or magnetic purposes in connection with recordings on magnetic tape or disc

31.

HOLD-UP CAPACITOR FAILURE HANDLING IN DATA STORAGE DEVICES

      
Application Number US2023075149
Publication Number 2024/076850
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Chodem, Nagi Reddy
  • Gorobets, Sergey Anatolievich
  • Vazaios, Evangelos

Abstract

A data storage device includes a plurality of hold-up capacitors configured to provide back-up power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed hold-up capacitors of the plurality of hold-up capacitors; and in response to detecting the one or more failed hold-up capacitors: perform one or more quiesce operations and determine a count of the one or more failed hold-up capacitors. Based on the count of the one or more failed hold-up capacitors, the controller is configured to reallocate the write buffers of the write cache for use in one or more subsequent write operations.

IPC Classes  ?

  • G11C 16/30 - Power supply circuits
  • G11C 5/14 - Power supply arrangements
  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters

32.

FINDING AND RELEASING TRAPPED MEMORY IN ULAYER

      
Application Number US2023025432
Publication Number 2024/072499
Status In Force
Filing Date 2023-06-15
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Frid, Marina
  • Genshaft, Igor

Abstract

The present disclosure generally relates to improving memory management. When valid mSets are relocated via mBlock compaction, the uLayer will have some updates for the mSet and consolidation of the mSet will write the mSet to mBlock once more. The disclosure herein reduces the impact of the problem that the same more frequently updated mSets uRegions are consolidated many times and written to flash where the less updated mSets uRegions become trapped uRegions in the uLayer reducing the uLayer capacity and efficacy. The disclosure provides guidance on how to synchronize the uLayer consolidations efficiently and preventing trapping of unused uRegions in the uLayer that reduces the uLayer capacity and efficiency. The synchronizing is between the uLayer consolidation to the mLayer and the mBlock compaction process such that the smaller uLayer efficacy will not be reduced due to trapped uRegions that are less frequently updated.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

33.

COBALT-BORON (CoB) LAYER FOR MAGNETIC RECORDING DEVICES, MEMORY DEVICES, AND STORAGE DEVICES

      
Application Number US2023025639
Publication Number 2024/072505
Status In Force
Filing Date 2023-06-17
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Okamura, Susumu
  • Le, Quang
  • York, Brian R.
  • Hwang, Cherngye
  • Simmons, Randy G.
  • Ho, Kuok San
  • Takano, Hisashi

Abstract

Embodiments of the present disclosure relate to a cobalt-boron (CoB) layer for magnetic recording devices, memory devices, and storage devices. In one or more embodiments, the CoB layer is part of a spin-orbit torque (SOT) device. In one or more embodiments, the SOT device is part of an SOT based sensor, an SOT based writer, a memory device (such as a magnetoresistive random-access memory (MRAM) device), and/or a storage device (such as a hard disk drive (HDD) or a tape drive). In one embodiment, an SOT device includes a seed layer, and a cap layer spaced from the seed layer. The SOT device includes a spin-orbit torque (SOT) layer, and a nano layer (NL) between the seed layer and the cap layer. The SOT device includes a cobalt-boron (CoB) layer between the seed layer and the cap layer, and the CoB layer is ferromagnetic.

IPC Classes  ?

34.

GLASS SHEET FOR FABRICATING MAGNETIC RECORDING MEDIA AND METHOD OF FABRICATING MAGNETIC RECORDING MEDIA

      
Application Number US2023025392
Publication Number 2024/072498
Status In Force
Filing Date 2023-06-15
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Suzuki, Shoji
  • Shieh, Mary Grace

Abstract

A glass sheet configured to be cut into glass substrates for magnetic recording disks is described. The glass sheet includes a first surface. For surface features of the first surface with a feature wavelength of 60 to 500 micrometers (μm), a root mean square of a surface topography of the surface features determined using a surface analysis on the first surface with incident and reflected light is given as a microwaviness. A maximum value of the microwaviness of any arbitrary region of the first surface may be between 1.2 nanometers (nm) and 2.8 nm, inclusive of 1.2 nm and 2.8 nm. After the surface analysis, the glass sheet may be cut into the glass substrates in response to determining that the maximum value of the microwaviness is in the noted range. Further, a method of fabricating glass substrates from a glass sheet is described.

IPC Classes  ?

  • G11B 5/73 - Base layers
  • G11B 5/84 - Processes or apparatus specially adapted for manufacturing record carriers

35.

HMB MULTI-SEGMENT OPTIMAL SELECTION

      
Application Number US2023025514
Publication Number 2024/072500
Status In Force
Filing Date 2023-06-16
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Benisty, Shay

Abstract

The present disclosure generally relates to improved host memory buffer (HMB) segment selection at the initialization phase. Rather than selecting an HMB segment strictly on one parameter, the selection process will consider multiple factors of the HMB segments. Instead of just selecting a HMB segments based on the size of the HMB segment, the data storage device will perform some basic performance measurements on the provided HMB segments before selecting HMB segments. The selection will be based also on the performance results from the various experiments. The experiments are performed in the initialization phase so the performance of the solid state drive (SSD) will not be impacted. The basic experiments include read, write, and mixed operations toward the HMB segments while measuring the performance and QoS.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

36.

CONTROL TABLE SET MANAGEMENT IN STORAGE DEVICES

      
Application Number US2023025524
Publication Number 2024/072501
Status In Force
Filing Date 2023-06-16
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Thacker, Nikita
  • Suresh, Ruthvick

Abstract

Various devices, such as storage devices or systems are configured to efficiently process and update logical maps within control table sets. Control table sets are often groupings of logical map corresponding to the logical locations of data requested by a host-computing device and the physical locations of the data within the memory array. As data is written and erased, these maps must be updated within the control table set. Received changes to these maps are typically stored and updated in two locations: a cache memory and a control table update list. By tracking and marking various control table sets as dirty or having undergone multiple changes, additional received updates can be stored and updated in only the cache memory, bypassing the second control table change list. By only utilizing one method of updating control table sets, processing overhead is reduced and various read or write activities are more efficiently done.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

37.

DYNAMIC TD-PPM STATE AND DIE MAPPING IN MULTI-NAND CHANNELS

      
Application Number US2023025165
Publication Number 2024/063820
Status In Force
Filing Date 2023-06-13
Publication Date 2024-03-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Benisty, Shay

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller and the memory device communicate using a plurality of flash channels, where each channel is mapped to one or more dies of the memory device. Each of the one or more dies of the memory device are associated with one or more strobes of a strobe cycle of a respective flash channel, where a die is provided power during a respective strobe. The controller is configured to, using a time division peak power management (TD-PPM) operation, change an association of a strobe from a first channel to a strobe of a second channel, which may adjust an amount of power provided to each of the channels and improve performance and latency of the data storage device.

IPC Classes  ?

  • G06F 1/3234 - Power saving characterised by the action undertaken
  • G06F 1/3225 - Monitoring of peripheral devices of memory devices
  • G06F 1/3228 - Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands

38.

CENTER STRUCTURE HAVING ATTACHMENT SUPPORT FOR AN ACTUATOR IN A MULTI-ACTUATOR HARD DISK DRIVE

      
Application Number 18226584
Status Pending
Filing Date 2023-07-26
First Publication Date 2024-03-28
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Park, Jung-Seo
  • Hitchner, Thomas J.
  • Mcnab, Robert
  • Sakhalkar, Siddhesh Vivek

Abstract

A multi-actuator hard disk drive includes a lower actuator with a corresponding voice coil motor assembly (VCMA), a coaxial upper actuator with a corresponding VCMA, and a central support plate positioned between the upper and lower VCMAs and to which the upper VCMA is fastened. Use of a central support plate enables some control over the direct and coupled plant transfer functions, while effectively providing a base support structure for the upper VCMA and enabling use of conventionally-sized fasteners.

IPC Classes  ?

  • G11B 5/55 - Track change, selection, or acquisition by displacement of the head
  • G11B 33/02 - Cabinets; Cases; Stands; Disposition of apparatus therein or thereon

39.

DC AND SYNCHRONIZED ENERGY ASSISTED PERPENDICULAR MAGNETIC RECORDING (EPMR) DRIVER CIRCUIT FOR HARD DISK DRIVE (HDD)

      
Application Number 18467045
Status Pending
Filing Date 2023-09-14
First Publication Date 2024-03-28
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Poss, Joey M.
  • Ding, Yunfei
  • Contreras, John T.

Abstract

Various illustrative aspects are directed to a data storage device comprising a storage medium and a head configured to access the storage medium. The head comprises a first write assist element and a second write assist element. Control circuitry for driving the head is configured to apply a first write assist current Im that is synchronized to a write data current Iw to the first write assist element; and to apply a second DC write assist current Imdc to the second write assist element.

IPC Classes  ?

  • G11B 5/02 - Recording, reproducing or erasing methods; Read, write or erase circuits therefor

40.

DYNAMIC AND SHARED CMB AND HMB ALLOCATION

      
Application Number US2023025256
Publication Number 2024/063821
Status In Force
Filing Date 2023-06-14
Publication Date 2024-03-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Benisty, Shay

Abstract

A data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to associate both the CMB and a host memory buffer (HMB) of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate either a CMB buffer or a HMB buffer based on a tradeoff between latency and performance between using the CMB or using the HMB to store data. By leveraging the benefits of both the CMB and the HMB to store data, the overall performance of the data storage device may be improved.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 12/10 - Address translation
  • G06F 3/06 - Digital input from, or digital output to, record carriers

41.

PARTIAL SPEED CHANGES TO IMPROVE IN-ORDER TRANSFER

      
Application Number US2023025260
Publication Number 2024/063822
Status In Force
Filing Date 2023-06-14
Publication Date 2024-03-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Navon, Ariel
  • Bazarsky, Alexander
  • Avraham, David

Abstract

The present disclosure generally relates partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
  • G06F 3/06 - Digital input from, or digital output to, record carriers

42.

AUTOMATED FAST PATH PROCESSING

      
Application Number US2023025264
Publication Number 2024/063823
Status In Force
Filing Date 2023-06-14
Publication Date 2024-03-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Sivasankaran, Vijay
  • Agarwal, Dinesh
  • Palityka, Mikhail

Abstract

Processing commands received from a host computing device by a storage device can require a large amount of processing overhead. This demand for ever greater processing power increases as the size of storage devices increase. Traditional methods have added an increasing number of processors or CPUs to handle these requirements. However, by utilizing a fast path accelerated processing pipeline, additional processors may not be necessary. An accelerated processing pipeline can be configured to bypass one or more steps that are required by non-priority processing pipelines. Each received command can be parsed to determine if it is suitable for accelerated processing. The command can be required to access data in a limited region of the memory device, or to have any data necessary to process the command already in a cache memory. Upon completion of verifications, commands can be placed in a priority queue that is processed before a non-priority queue.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

43.

SSD USE OF HOST MEMORY BUFFER FOR IMPROVED PERFORMANCE

      
Application Number US2023025130
Publication Number 2024/058840
Status In Force
Filing Date 2023-06-13
Publication Date 2024-03-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Gorrle, Dhanunjaya Rao
  • Karki, Aajna
  • Xie, Hongmei

Abstract

Aspects of a storage device are provided that requests L2P address translation data from an HMB for execution of an associated host command using a dynamically determined HMB transfer size. The storage device includes a volatile memory and a controller. The controller allocates, in the volatile memory, multiple memory locations for L2P address translation data from an HMB. The controller receives a command indicating a host data length, and transmits a request for a portion of the L2P address translation data stored in the HMB for the command. The HMB transfer size associated with the request may be based on the host data length of the associated host command, a quantity of free and contiguous memory locations available in the HMB read buffer, or a minimum between a size of the portion and a total size of the free and contiguous memory locations. Thus, HMB transfer latency may be reduced.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 12/10 - Address translation

44.

BLOCK LAYER PERSISTENT MEMORY BUFFER

      
Application Number US2023025156
Publication Number 2024/058842
Status In Force
Filing Date 2023-06-13
Publication Date 2024-03-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Segev, Amir
  • Hahn, Judah Gamliel

Abstract

The present disclosure generally relates to improved access to the DRAM using namespace mapping. The PMR address range is mapped to LBA address space. Mapping the PMR address range in LBA address space allows the host to access the PMR indirectly using NVMe commands. The host device may hold in the namespace the most frequently accessed data and obtain highest performance and low latency. Implementation of the Power Loss Protection (PLP) feature over the PMR makes the system prefer storing the data in PMR rather in host memory. All internal SRAMs (e.g. Transfer RAMs, XOR RAMs, etc.) may be mapped in the LBA address space so the host device can access mainly for debug purposes. Some internal flops that hold important data are mapped in the LBA address space as well.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

45.

EFFICIENT L2P DRAM FOR HIGH-CAPACITY DRIVES

      
Application Number US2023025131
Publication Number 2024/058841
Status In Force
Filing Date 2023-06-13
Publication Date 2024-03-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Benisty, Shay

Abstract

The present disclosure generally relates to improving space efficiency when storing logical to physical (L2P) entries. Rather than writing a physical block address (PBA) spanning multiple entries, the PBA is split between a first portion stored in the buffer with the remaining bits of the PBA added to the metadata buffer. The metadata buffer is sub-optimal due to the small size of the metadata relative to the entry and therefore, adding extra bits to the metadata buffer will make the metadata buffer more optimal. In this scheme, the alignment is preserved, the system becomes more optimal in terms of DRAM access, and the metadata buffer can be easily optimized and adapted.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 11/08 - Error detection or correction by redundancy in data representation, e.g. by using checking codes

46.

METADATA MANAGEMENT IN KEY VALUE DATA STORAGE DEVICE

      
Application Number US2023025020
Publication Number 2024/054273
Status In Force
Filing Date 2023-06-12
Publication Date 2024-03-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Muthiah, Ramanathan

Abstract

A data storage device includes a memory device and a controller to the memory device. The controller is configured to receive key value (KV) pair data having a key and a value from a host device and generate a mapping in a key-to-physical (K2P) table corresponding to the received KV pair data. The mapping includes a first slot for storing a physical address corresponding to the value and a second slot for storing a physical address corresponding to metadata associated with the KV pair data. When the associated metadata is sent to the data storage device, which may be non-concurrent to transferring the KV pair data, the mapping of the associated metadata is linked to a same key as the mapping of the KV pair data. Thus, using the mapping, the key of the KV pair data is associated with the KV pair data and the associated metadata.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 3/06 - Digital input from, or digital output to, record carriers

47.

ASYMMETRIC TIME DIVISION PEAK POWER MANAGEMENT (TD-PPM) TIMING WINDOWS

      
Application Number US2023025023
Publication Number 2024/054274
Status In Force
Filing Date 2023-06-12
Publication Date 2024-03-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Hassan, Yossi Yoseph

Abstract

A data storage device includes a memory device and a controller. The controller is configured to assert a strobe cycle having a plurality of strobes to the memory device, where a die of the memory device may be associated with one or more strobes of the plurality of strobes. The controller is further configured to determine whether the die of the memory device requires additional power and adjust a strobe length of time of the corresponding strobe when the die of the memory device requires additional power. The controller is further configured to decrease a strobe length of time of one or more strobes that do not require additional power. By utilizing a time division peak power management (TD-PPM) feature by dynamically changing a strobe length of time of each strobe of the plurality of strobes, performance and latency of the data storage device may be improved.

IPC Classes  ?

  • G06F 1/3234 - Power saving characterised by the action undertaken
  • G06F 1/3228 - Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
  • G06F 1/329 - Power saving characterised by the action undertaken by task scheduling

48.

OPTIMIZATION OF NON-ALIGNED HOST WRITES

      
Application Number US2023025028
Publication Number 2024/054275
Status In Force
Filing Date 2023-06-12
Publication Date 2024-03-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Bazarsky, Alexander
  • Hahn, Judah Gamliel
  • Ionin, Michael

Abstract

The present disclosure generally relates to aligning non-aligned data for more efficient data reading. Data for write commands does not always perfectly align, yet the data is written in order of write command receipt. In such cases, aligned chunks of data may be split into two word lines (WLs) due to the presence of previously received smaller chunks of data. Rather than writing the data in order, the smaller chunks of data, which are non-aligned, are held in a buffer and written later to ensure that any aligned chunks of data remain aligned when written to the memory device. Once sufficient smaller chunks or data have accumulated to be aligned, or upon a need to write the smaller chunks upon reaching a threshold, the smaller chunks are written together in a single WL so as to not cause non-alignment of aligned data.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

49.

ADAPTIVE TUNING OF MEMORY DEVICE CLOCK RATES BASED ON DYNAMIC PARAMETERS

      
Application Number US2023025410
Publication Number 2024/054280
Status In Force
Filing Date 2023-06-15
Publication Date 2024-03-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Navon, Ariel
  • Bazarsky, Alexander
  • Avraham, David

Abstract

The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.

IPC Classes  ?

  • G11C 16/32 - Timing circuits
  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G06F 3/06 - Digital input from, or digital output to, record carriers

50.

ACCELERATOR QUEUE IN DATA STORAGE DEVICE

      
Application Number US2023025119
Publication Number 2024/054278
Status In Force
Filing Date 2023-06-13
Publication Date 2024-03-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Muthiah, Ramanathan

Abstract

Disclosed are systems and methods for accelerating commands from accelerators in data storage devices using accelerator queues. A data storage device includes accelerator interfaces, each accelerator interface couples a controller to a respective accelerator. The device also includes a device memory comprising one or more memories and one or more sets of queues. Each set of queues corresponds to a respective memory, at least one queue is configured to queue one or more tasks associated with an accelerator, and each queue is associated with a respective priority level of a plurality of priority levels. A controller is configured to: receive an accelerator command, identify a first memory corresponding to a task for the accelerator command; and enqueue the task to a first queue corresponding to the first memory, the first queue configured to queue one or more tasks associated with the first accelerator corresponding to the first accelerator interface.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

51.

DATA RECOVERY FOR ZONED NAMESPACE DEVICES

      
Application Number US2023068569
Publication Number 2024/054700
Status In Force
Filing Date 2023-06-16
Publication Date 2024-03-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Sivasankaran, Vijay
  • Kragel, Oleg

Abstract

Zone Write Groups (ZWGs) to assist data storage devices and host devices with data recovery. In one embodiment, a data storage device includes a memory storing a Zoned NameSpace (ZNS). The ZNS includes a ZWG including host zones and parity zones. An interface connects the data storage device with a host device. The data storage device includes a data storage device controller including an electronic processor and a memory. The data storage device controller populates the ZWG with buffers received from the host device. The data storage device controller detects corrupted data associated with the ZNS and requests one or more buffers stored in the ZWG. Once the data storage device controller receives the one or more buffers from the ZWG, the data storage device controller performs a recovery event with the one or more buffers.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

52.

SYSTEM AND METHOD FOR RETRIMMING REMOVABLE STORAGE DEVICES

      
Application Number US2023024938
Publication Number 2024/049525
Status In Force
Filing Date 2023-06-09
Publication Date 2024-03-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Erez, Eran
  • Meza, Joseph R.
  • Fairchild, Dylan B.

Abstract

A data storage device includes a host interface for coupling the data storage device to a host system. The data storage device also includes a device memory and a controller. The controller is configured to determine if a retrim is needed for the data storage device. In accordance with a determination that the retrim is needed, the controller is configured to identify a time to initiate a new trim on the data storage device, and cause the new trim on the data storage device at the time identified.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

53.

HANDLING WRITE DATA BURST FOR IMPROVED PERFORMANCE AND RESOURCE USAGE

      
Application Number US2023024945
Publication Number 2024/049526
Status In Force
Filing Date 2023-06-09
Publication Date 2024-03-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Erez, Eran
  • Meza, Joseph R.
  • Thomas, Nicholas J.

Abstract

Disclosed are systems and methods for large write planning for performance consistency and resource usage efficiency. A method is implemented using one or more controllers for one or more storage devices. The method includes receiving, via a host interface, a notification of a write data burst. The method also includes computing available spaces in a plurality of memories and a write ratio, to handle the write data burst to the plurality of memories, based on the notification. The method also includes receiving, via the host interface, the write data burst. The method also includes, in response to receiving the write data burst, toggling writes between the plurality of memories, based on the available spaces and the write ratio.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

54.

HEAT-ASSISTED MAGNETIC RECORDING (HAMR) HEAD WITH MAIN POLE HAVING NARROW PLASMONIC RECESS

      
Application Number US2023024648
Publication Number 2024/043967
Status In Force
Filing Date 2023-06-07
Publication Date 2024-02-29
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Matsumoto, Takuya

Abstract

A heat‑assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) with an output tip at the GBS and a main magnetic pole that has a recess in the NFT-facing surface that contains plasmonic material. The plasmonic recess has a front edge at the GBS that has a cross-track width equal to or less than the cross-track width of the widest portion of the NFT output tip, and a back edge recessed from the GBS. A thermal shunt is located between the NFT and the main pole to allow heat to be transferred away from the optical spot generated by the NFT output tip, and is in contact with a region of the plasmonic recess near the back edge.

IPC Classes  ?

  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 5/73 - Base layers
  • G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor

55.

BIFACIAL SEMICONDUCTOR WAFER

      
Application Number US2023024565
Publication Number 2024/039432
Status In Force
Filing Date 2023-06-06
Publication Date 2024-02-22
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Shi, Sara
  • Zhang, Cong
  • Chiu, Hope

Abstract

A semiconductor device having one or more bifacial semiconductor wafers. The bifacial semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar surface that is opposite the first planar surface. The first array of semiconductor dies are electrically coupled via a first redistribution layer and the second array of semiconductor dies are electrically coupled via a second redistribution layer. One or more through silicon vias electrically couple the first array of semiconductor dies with the second array of semiconductor dies.

IPC Classes  ?

  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

56.

NVMe BOOT PARTITION ERROR CORRECTION CODE ENHANCEMENT

      
Application Number US2023024532
Publication Number 2024/039430
Status In Force
Filing Date 2023-06-06
Publication Date 2024-02-22
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Bazarsky, Alexander
  • Hahn, Judah Gamliel
  • Benisty, Shay
  • Navon, Ariel

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to compare a first copy of a boot partition to a second copy of the boot partition. The first copy of the boot partition and the second copy of the boot partition each comprises a same number of a plurality of boot chunks. The boot partition corresponds to data of a boot operation of a host device. The controller is further configured to mark one or more of the compared boot chunks that equals or exceeds a similarity threshold and update a reliability index based on the marking. Based on the marking and the reliability index, the controller may increase or decrease an amount of error correction needed for the boot data.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

57.

CHEMISORBED LUBRICANTS FOR DATA STORAGE DEVICES

      
Application Number US2023025637
Publication Number 2024/039440
Status In Force
Filing Date 2023-06-17
Publication Date 2024-02-22
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • He, Xingliang
  • Xu, Huaming
  • Wen, Jianming
  • Lee, Charles Cheng-Hsing

Abstract

1f1f22222n2222n22322222mn2222n11 is the functional group. A lubricant is formed from a multiple ether segments according to formula: Re1-Rb1-Ri-Rc-Ri-Rb2-Re2; where Rc includes perfluoroalkyl ether, Rb1and Rb2are, independently, a sidechain segment including a perfluoroalkyl ether, optional Ri independently is a divalent linking segment including a functional group including elements from periodic table Group 13–17, and of Re1and Re2 are phosphonic acid, silanol or carboxylic acid. Lubricant synthesis includes reacting a perfluorinated polyether with a halogenated functional group, selected from phosphonic acid, silanol or carboxylic acid.

IPC Classes  ?

  • C10M 107/38 - Lubricating compositions characterised by the base-material being a macromolecular compound containing halogen
  • C10M 107/50 - Lubricating compositions characterised by the base-material being a macromolecular compound containing silicon
  • C10M 107/48 - Lubricating compositions characterised by the base-material being a macromolecular compound containing phosphorus
  • G11B 5/725 - Protective coatings, e.g. anti-static containing a lubricant
  • C10N 40/18 - Electric or magnetic purposes in connection with recordings on magnetic tape or disc

58.

WRITE COALESCING VIA HMB TO OPTIMIZE WRITE PERFORMANCE

      
Application Number US2023024417
Publication Number 2024/035475
Status In Force
Filing Date 2023-06-05
Publication Date 2024-02-15
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Bazarsky, Alexander
  • Hahn, Judah Gamliel
  • Navon, Ariel

Abstract

The present disclosure generally relates to improved handling of write commands. The host memory buffer (HMB) or other storage space can be utilized to delay execution of host write commands which will improve write performance in different use cases and will also allow having more concurrent streams than open blocks without impacting write or read performance. Generally, once a write command is received, the write command is revised as a new write command that is logically equivalent to the original write command. The revised write command is moved to the HMB along with the data. In so doing, the write command is coalesced and write command handling is improved.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

59.

FAST SEARCH FOR LEAKY WORD LINE

      
Application Number US2023024716
Publication Number 2024/035480
Status In Force
Filing Date 2023-06-07
Publication Date 2024-02-15
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Zhou, Xingyan
  • Li, Liang
  • Qin, Zhen
  • Mak, William
  • Li, Yan

Abstract

Technology is disclosed herein for detecting leaky word lines in a non-volatile storage system. The exact leaky word line may be located very rapidly using a divide and conquer approach. Fist a determination may be made whether at least one word line in a group such as any of the word lines in a block is leaky. This initial determination can be made very quickly. If no word line in the group is leaky, the search can end. However, responsive to a determination that at least one word line in the group is leaky, a divide and conquer search may be performed in which the group of the word lines is repeatedly divided into smaller sub-groups with selected smaller sub-groups tested for a short circuit until the leaky word line is located.

IPC Classes  ?

  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

60.

STRESS TEST FOR GROWN BAD BLOCKS

      
Application Number US2023024724
Publication Number 2024/035482
Status In Force
Filing Date 2023-06-07
Publication Date 2024-02-15
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Puthenthermadam, Sarath
  • Liu, Longju
  • Amin, Parth
  • Islam, Sujjatul
  • Yuan, Jiahui

Abstract

Technology is disclosed herein for detecting grown bad blocks in a non-volatile storage system. A stress test may accelerate stressful conditions on the memory cells and thereby provide for early detection of grown bad blocks. The stress test may include applying a program voltage to a selected word line and a stress voltage that is less than a nominal boosting voltage to a word line adjacent one side of the selected word line. The combination of the program voltage and the stress voltage may generate an e-field that is stronger than an e-field that would be generated in a normal program operation, thereby accelerating the stress on the memory cells. The stress test mat further include programming all of the memory cells to a relatively high threshold voltage, which may create additional stress on the memory cells.

IPC Classes  ?

  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 8/14 - Word line organisation; Word line lay-out
  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

61.

FLEXIBLE PRINTED CIRCUIT FINGER LAYOUT FOR LOW CROSSTALK

      
Application Number 18379587
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-02-01
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Kishimoto, Masahiro
  • Contreras, John
  • Nagaoka, Kazuhiro
  • Nakamura, Satoshi

Abstract

A flexible printed circuit (FPC) for a hard disk drive includes a plurality of electrical traces, whereby aggressor traces are isolated from victim traces to avoid crosstalk that could degrade signals. Aggressor traces may be positioned together at one of the edges of each of the top wiring layer and the bottom wiring layer, physically isolated from victim traces. Aggressor traces may be grouped together at either the top wiring layer or the bottom wiring layer, with the victim traces positioned on the layer opposing the aggressor traces. With aggressor and victim traces routed on the same wiring layer, aggressor traces may be routed away from the victim traces with multi-layer routing, by way of vias.

IPC Classes  ?

62.

CONTENT-RICH ERROR NOTIFICATION

      
Application Number US2023024259
Publication Number 2024/025656
Status In Force
Filing Date 2023-06-02
Publication Date 2024-02-01
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Vui, Kan Lip
  • Hahn, Judah Gamliel
  • Benisty, Shay

Abstract

A data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine a quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is either greater than or less than a threshold quality, and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality. The sideband is a different communication channel than the PCIe link. The error notification includes additional information regarding events occurring in the data storage device resulting in the quality of the PCIe link.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation

63.

STORAGE SYSTEM AND METHOD FOR OPTIMIZING HOST-ACTIVATED DEFRAGMENTATION AND PROACTIVE GARBAGE COLLECTION PROCESSES

      
Application Number US2023024409
Publication Number 2024/025660
Status In Force
Filing Date 2023-06-05
Publication Date 2024-02-01
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Zilberstein, Einav
  • Sober, Nadav
  • Katz, Omer

Abstract

A storage system is provided that performs a defragmentation operation or proactive garbage collection in its memory based on a command from a host. The command specifies which blocks in the memory should take part in the defragmentation operation by specifying a maximum amount of valid data that a block can have to qualify for defragmentation. That way, the storage system only performs defragmentation on those blocks that meet the validity criteria provided by the host. This can help improve performance of the storage system while reducing the degree of negative tradeoffs that may come with defragmentation or proactive garbage collection.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

64.

BUFFER LAYERS, INTERLAYERS, AND BARRIER LAYERS COMPRISING HEUSLER ALLOYS FOR SOT BASED SENSOR, MEMORY, AND STORAGE DEVICES

      
Application Number US2023025602
Publication Number 2024/025682
Status In Force
Filing Date 2023-06-16
Publication Date 2024-02-01
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Le, Quang
  • York, Brian, R.
  • Hwang, Cherngye
  • Liu, Xiaoyong
  • Okamura, Susumu
  • Gribelyuk, Michael, A.
  • Xu, Xiaoyu
  • Simmons, Randy, G.
  • Ho, Kuok San
  • Takano, Hisashi

Abstract

The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprises a nonmagnetic buffer layer, a nonmagnetic interlayer, a ferromagnetic layer, and a nonmagnetic barrier layer. One or more of the barrier layer, interlayer, and buffer layer comprise a polycrystalline non-Heusler alloy material, or a Heusler alloy and a material selected from the group consisting of: Cu, Ag, Ge, Mn, Ni, Co, Mo, W, Sn, B, and In. The Heusler alloy is a full Heusler alloy comprising X2YZ or a half Heusler alloy comprising XYZ, where X is one of: Mn, Fe, Co, Ni, Cu, Ru, Rh, Pd, Ag, Ir, Pt, and Au, Y is one of: Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Nb, Mo, Hf, and W, and Z is one of: B, Al, Si, Ga, Ge, As, In, Sn, Sb, and Bi.

IPC Classes  ?

  • H10N 52/85 - Magnetic active materials
  • H10N 52/00 - Hall-effect devices
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

65.

ACCELERATED ENCRYPTION DURING POWER LOSS

      
Application Number US2023024250
Publication Number 2024/019826
Status In Force
Filing Date 2023-06-02
Publication Date 2024-01-25
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Segev, Amir
  • Benisty, Shay

Abstract

The present disclosure generally relates to a XTS cache operation during a power down event. Upon detection of power loss, data that is waiting to be encrypted needs to be flushed to the memory device. For any unaligned data or data less than a flash management unit (FMU) size, the data is grouped together and, if necessary, padded to reach the FMU size and then encrypted, merged with other data FMUs, and written to the memory device. Grouping the unaligned data reduces the amount of padding necessary to reach FMU size and also reduces the amount of data to be encrypted. As such, data flushing can be accomplished using the limited amount of remaining power during the power loss event.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

66.

SHARED VIAS FOR DIFFERENTIAL PAIR TRACE ROUTING

      
Application Number US2023024094
Publication Number 2024/015160
Status In Force
Filing Date 2023-06-01
Publication Date 2024-01-18
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Rasalingam, Uthayarajan A/l
  • Khaw, Hock Boon

Abstract

Multi-signal vias for use with differential pair signals in electronic devices. The electronic devices include a printed circuit board having a first side and a second side opposite the first side, a first conductive trace on the first side of the substrate and a second conductive trace on the first side of the substrate. The printed circuit board also includes a shared via, which includes a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are separated by a non-conductive portion. The first conducive trace is coupled to the first conductive portion of the shared via and the second conductive trace is coupled to the second conductive portion of the shared via.

IPC Classes  ?

  • H05K 1/02 - Printed circuits - Details
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • G06F 3/06 - Digital input from, or digital output to, record carriers

67.

MANAGEMENT OF HOST FILE-SYSTEM DEFRAGMENTATION IN A DATA STORAGE DEVICE

      
Application Number US2023024105
Publication Number 2024/015161
Status In Force
Filing Date 2023-06-01
Publication Date 2024-01-18
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Hahn, Judah Gamliel
  • Muthiah, Ramanathan
  • Narala, Bala Siva Kumar
  • Chinnaanangur Ravimohan, Narendhiran

Abstract

A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that avoids, reduces, and/or optimizes physical data movement in flash memory. In an example embodiment, the memory controller maintains in a volatile memory thereof a lookaside table that supplants pertinent portions of the logical-to-physical table. Entries of the lookaside table are configured to track source and destination addresses of the host defragmentation requests and are logically linked to the corresponding entries of the logical-to-physical table such that end-to-end data protection including the use of logical-address tags to the user data can be supported by logical means and without physical data rearrangement in the flash memory. In some embodiments, physical data rearrangement corresponding to the file-system defragmentation is performed in the flash memory in response to certain trigger events, which can improve the input/output performance of the data-storage device.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/1027 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

68.

LOGICAL-TO-PHYSICAL MAPPING FOR DEFRAGMENTATION OF HOST FILE SYSTEM IN A DATA STORAGE DEVICE

      
Application Number US2023024268
Publication Number 2024/015164
Status In Force
Filing Date 2023-06-02
Publication Date 2024-01-18
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Hahn, Judah Gamliel
  • Muthiah, Ramanathan
  • Narala, Bala Siva Kumar
  • Chinnaanangur Ravimohan, Narendhiran

Abstract

A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that substantially avoids physical data movement in a flash memory. In an example embodiment, a memory controller operates to update a logical-to-physical table thereof to change association of physical addresses of sections of user data from being associated with source logical addresses to being associated with destination logical addresses of the host defragmentation requests without moving the user data in the flash memory. Such updates can reduce the number of instances in which the host addresses a non-contiguous logical-address range, which results in a beneficial reduction of the number of input/output commands sent to the data storage device and of the associated processing overhead.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 3/06 - Digital input from, or digital output to, record carriers

69.

STORAGE SYSTEM AND METHOD FOR PROACTIVE DIE RETIREMENT BY FATAL WORDLINE LEAKAGE DETECTION

      
Application Number US2023023662
Publication Number 2024/006010
Status In Force
Filing Date 2023-05-26
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Tian, Xuan
  • Li, Liang
  • Yi, Dandan
  • Xing, Jojo
  • Yin, Vincent
  • Sun, Yongke
  • Bennett, Alan

Abstract

In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.

IPC Classes  ?

  • G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters

70.

DETECTION AND ISOLATION OF FAULTY HOLDUP CAPACITORS USING HARDWARE CIRCUIT IN DATA STORAGE DEVICES

      
Application Number US2023020997
Publication Number 2024/005916
Status In Force
Filing Date 2023-05-04
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Chodem, Nagi Reddy
  • Gorobets, Sergey Anatolievich

Abstract

Disclosed are systems and methods detecting and isolating faulty hold-up capacitors and performing corrective actions for a data storage device. A hardware circuit is coupled to a micro-controller and non-volatile memory dies. The method includes, at the hardware circuit: providing a back-up power for the non-volatile memory dies and the micro-controller; and detecting whether a hold-up capacitor of the hardware circuit is faulty and isolating the hold-up capacitor in accordance with a detection that the hold-up capacitor is faulty. The method also includes, at the micro-controller: obtaining a status of an interface coupled to the hardware circuit; determining a status of the hardware circuit based on the status of the interface; and performing a corrective action for the data storage device in accordance with a determination that the status of hardware circuit corresponds to one or more faulty hold-up capacitors.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

71.

KEY-TO-PHYSICAL TABLE OPTIMIZATION FOR KEY VALUE DATA STORAGE DEVICES

      
Application Number US2023021272
Publication Number 2024/005922
Status In Force
Filing Date 2023-05-06
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Zamir, Ran
  • Bazarsky, Alexander
  • Avraham, David

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to segment a key to physical (K2P) table into two or more segments, wherein each segment of the two or more segments corresponds to a caching priority of key value (KV) pair data, organize the K2P table by storing and relocating one or more K2P table entries into a respective segment of the two or more segments, wherein the storing and relocating comprises moving a K2P table entry based on the caching priority of the KV pair data into the respective segment having the caching priority, and utilize the K2P table to manage KV pair data stored in the memory device, wherein utilizing the K2P table comprises applying a same management operation, such as prefetching, to each K2P table entry of a same segment.

IPC Classes  ?

  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 3/06 - Digital input from, or digital output to, record carriers

72.

PERFORMANCE INDICATOR ON A DATA STORAGE DEVICE

      
Application Number US2023021353
Publication Number 2024/005924
Status In Force
Filing Date 2023-05-08
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Muthiah, Ramanathan

Abstract

A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a display system, and a controller. The controller is configured to receive and execute one or more commands from the host computer system to cause a data transfer between the host computer system and the storage medium of the data storage device. The controller generates performance data representing the performance of the data storage device, wherein the performance data includes an efficiency ratio value representing a relative utilization of an operational capability of the data storage device in conducting the data transfer. The controller generates one or more control signals to cause the display system to visually indicate at least the efficiency ratio value of the performance data.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 3/14 - Digital output to display device

73.

POWER MANAGEMENT FOR WIRELESS DEVICE LOSS PREVENTION AND DISCOVERY

      
Application Number US2023021494
Publication Number 2024/005928
Status In Force
Filing Date 2023-05-09
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Klapman, Matthew Harris
  • Ross, David

Abstract

A data storage device comprises a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a beacon component, and a power manager configured to provide electrical energy to the beacon component. The beacon component is configured to wirelessly transmit a signal in accordance with a beacon configuration, and, in response to determining a power availability level associated with the power manager, adjust the beacon configuration to change a rate of consumption of electrical energy by the beacon component.

IPC Classes  ?

  • H04W 52/02 - Power saving arrangements
  • H02J 50/40 - Circuit arrangements or systems for wireless supply or distribution of electric power using two or more transmitting or receiving devices

74.

AUDIO SENSORS FOR CONTROLLING SURVEILLANCE VIDEO DATA CAPTURE

      
Application Number US2023021510
Publication Number 2024/005929
Status In Force
Filing Date 2023-05-09
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Muthiah, Ramanathan
  • Yadav, Akhilesh

Abstract

Systems, video cameras, and methods for using audio sensors to control surveillance video capture are described. A video camera and audio sensor are deployed so that the audio sensor has an audio field that is at least partially outside the field of view of the video camera. The audio sensor collects audio data from the audio field and a controller for the video camera uses audio events from the audio data for modifying the video capture operations of the video camera. Video data is then captured based on the modified video capture operations, such as initiating video capture, changing the video capture rate, or changing the camera position.

IPC Classes  ?

  • H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
  • H04N 23/58 - Means for changing the camera field of view without moving the camera body, e.g. nutating or panning of optics or image sensors
  • H04N 23/69 - Control of means for changing angle of the field of view, e.g. optical zoom objectives or electronic zooming
  • H04N 23/695 - Control of camera direction for changing a field of view, e.g. pan, tilt or based on tracking of objects
  • G10L 25/57 - Speech or voice analysis techniques not restricted to a single one of groups specially adapted for particular use for comparison or discrimination for processing of video signals
  • G10L 25/27 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the analysis technique

75.

PEER RAID CONTROL AMONG PEER DATA STORAGE DEVICES

      
Application Number US2023021523
Publication Number 2024/005930
Status In Force
Filing Date 2023-05-09
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Hahn, Judah Gamliel
  • Muthiah, Ramanathan

Abstract

Example storage systems, data storage devices, and methods provide redundant array of independent disk (RAID) control among peer storage devices. A master storage device among peer storage devices receives host commands and determines, based on a peer RAID configuration, data blocks for redundantly storing the host data unit among the peer storage devices. The master storage device allocates the data blocks among the peer storage devices and sends them to the peer storage devices using a peer communication channel.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

76.

SECURITY INDICATOR ON A DATA STORAGE DEVICE

      
Application Number US2023021570
Publication Number 2024/005933
Status In Force
Filing Date 2023-05-09
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Muthiah, Ramanathan

Abstract

A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a data security indicator, and a controller. The controller is configured to selectively control access of the host computer system to the user data based on security configuration data of the data storage device. The controller is further configured to respond to the occurrence of one or more operations, the operations being any of: (i) a data access operation requested or performed, by the host computer system, on the data storage device to access the storage medium via the data port; and (ii) a security control operation requested or performed, by an external device, on the data storage device to store, retrieve or update the security configuration data of the data storage device. The response of the controller includes generating an indicator control signal to cause the data security indicator to indicate one or more security parameters associated with the one or more operations.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 3/14 - Digital output to display device

77.

HIGHLY TEXTURED 001 BISB AND MATERIALS FOR MAKING SAME

      
Application Number US2023021323
Publication Number 2024/005923
Status In Force
Filing Date 2023-05-08
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Le, Quang
  • York, Brian, R.
  • Hwang, Cherngye
  • Liu, Xiaoyong
  • Gribelyuk, Michael, A.
  • Xu, Xiaoyu
  • Simmons, Randy, G.
  • Ho, Kuok San
  • Takano, Hisashi

Abstract

The present disclosure generally relates to spin-orbit torque (SOT) device comprising a first bismuth antimony (BiSb) layer having a (001) orientation. The SOT device comprises a first BiSb layer having a (001) orientation and a second BiSb layer having a (012) orientation. The first BiSb layer having a (001) orientation is formed by depositing an amorphous material selected from the group consisting of: B, Al, Si, SiN, Mg, Ti, Sc, V, Cr, Mn, Y, Zr, Nb, AlN, C, Ge, and combinations thereof, on a substrate, exposing the amorphous material to form an amorphous oxide surface on the amorphous material, and depositing the first BiSb layer on the amorphous oxide surface. By utilizing a first BiSb layer having a (001) orientation and a second BiSb having a (012) orientation, the signal through the SOT device is balanced and optimized to match through both the first and second BiSb layers.

IPC Classes  ?

  • G11B 5/39 - Structure or manufacture of flux-sensitive heads using magneto-resistive devices
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • H10N 50/80 - Constructional details

78.

DATA STORAGE DEVICE MANAGEMENT SYSTEM

      
Application Number US2023021458
Publication Number 2024/005925
Status In Force
Filing Date 2023-05-09
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Muthiah, Ramanathan
  • Venkataramanan, Balaji Thraksha

Abstract

Devices and techniques are disclosed wherein an end user can remotely trigger direct data management activities of a data storage device (DSD), such as creating a data snapshot, resetting a snapshot, and setting permissions at the DSD via a remote mobile device app interface.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

79.

WIRELESS DEVICE LOSS PREVENTION AND DISCOVERY

      
Application Number US2023021465
Publication Number 2024/005926
Status In Force
Filing Date 2023-05-09
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Klapman, Matthew Harris
  • Ross, David

Abstract

A data storage device comprises a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, an energy harvesting component configured to produce electrical energy from an ambient energy source, and a beacon component, configured to wirelessly transmit a signal. The beacon component is configured to consume the electrical energy to wirelessly transmit the signal. The data storage device may further comprise an energy store configured to store the electrical energy produced by the energy harvesting component as stored energy.

IPC Classes  ?

  • G06F 13/14 - Handling requests for interconnection or transfer
  • G06F 13/38 - Information transfer, e.g. on bus
  • H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
  • H01L 31/042 - PV modules or arrays of single PV cells
  • H04B 17/318 - Received signal strength

80.

DATA STORAGE DEVICE WITH FLEXIBLE LOGICAL TRACKS AND RADIUS-INDEPENDENT DATA RATE

      
Application Number US2023021487
Publication Number 2024/005927
Status In Force
Filing Date 2023-05-09
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Hall, David R.

Abstract

Various illustrative aspects are directed to a data storage device, comprising one or more disks; at least one actuator mechanism configured to position at least a first head proximate to a first disk surface and a second head proximate to a second disk surface; and one or more processing devices. The one or more processing devices are configured to: assign logical tracks to physical tracks of the disk surfaces such that a respective logical track comprises: at least a portion of sectors of a primary physical track, the primary physical track being on the first disk surface; and at least a portion of sectors of a donor physical track, the donor physical track being on the second disk surface. The one or more processing devices are configured to perform, using the first head and the second head, a data access operation with at least one of the logical tracks.

IPC Classes  ?

  • G11B 19/14 - Control of operating function, e.g. switching from recording to reproducing by sensing movement or position of head, e.g. means moving in correspondence with head movements
  • G11B 25/04 - Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing using flat record carriers, e.g. disc, card
  • G11B 19/20 - Driving; Starting; Stopping; Control thereof

81.

DOPED BISB (012) OR UNDOPED BISB (001) TOPOLOGICAL INSULATOR WITH GENIFE BUFFER LAYER AND/OR INTERLAYER FOR SOT BASED SENSOR, MEMORY, AND STORAGE DEVICES

      
Application Number US2023021552
Publication Number 2024/005932
Status In Force
Filing Date 2023-05-09
Publication Date 2024-01-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Le, Quang
  • York, Brian R.
  • Hwang, Cherngye
  • Liu, Xiaoyong
  • Gribelyuk, Mr. Michael A.
  • Xu, Xiaoyu
  • Okamura, Susumu
  • Ho, Kuok San
  • Takano, Mr. Hisashi
  • Simmons, Randy G.

Abstract

XXXXXXXNiFe layer allows the crystal orientation of the BiSb layer to be selected.

IPC Classes  ?

  • G11B 5/39 - Structure or manufacture of flux-sensitive heads using magneto-resistive devices
  • H10N 50/80 - Constructional details
  • H10N 52/80 - Constructional details

82.

SPIN TORQUE OSCILLATOR WITH MULTILAYER SEED FOR IMPROVED PERFORMANCE AND RELIABILITY

      
Application Number US2023020992
Publication Number 2023/249704
Status In Force
Filing Date 2023-05-04
Publication Date 2023-12-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Freitag, James Mac
  • Ahn, Yongchul
  • Okamura, Susumu
  • Kaiser, Mr. Christian

Abstract

The present disclosure generally relates to a magnetic recording device having a magnetic recording head comprising a spintronic device. The spintronic device is disposed between a main pole and a trailing shield at a media facing surface. The spintronic device comprises a spin torque layer (STL) and a multilayer seed layer disposed in contact with the STL. The spintronic device may further comprise a field generation layer disposed between the trailing shield and the STL. The multilayer seed layer comprises an optional high etch rate layer, a heat dissipation layer comprising Ru disposed in contact with the optional high etch rate layer, and a cooling layer comprising Cr disposed in contact with the heat dissipation layer and the main pole. The high etch rate layer comprises Cu and has a high etch rate to improve the shape of the spintronic device during the manufacturing process.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 1/20 - Cooling means

83.

SPIN TORQUE OSCILLATOR WITH ENHANCED SPIN POLARIZER

      
Application Number US2023020945
Publication Number 2023/249703
Status In Force
Filing Date 2023-05-04
Publication Date 2023-12-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Freitag, James Mac
  • Okamura, Susumu
  • Kaiser, Mr. Christian

Abstract

The present disclosure generally relates to a magnetic recording head comprising a spintronic device. The spintronic device is disposed between a main pole and a trailing shield of the magnetic recording head. The spintronic device comprises a multilayer spacer layer comprising a Cu layer in contact with a spin torque layer and a spin transparent texture layer disposed on the Cu layer, the spin transparent texture layer comprising AgSn or AgZn. A multilayer notch comprising a CoFe layer is disposed over the spin transparent texture layer of the multilayer spacer layer and a Heusler alloy layer is disposed on the CoFe layer, the Heusler alloy layer comprising CoMnGe, CoFeGe, or CoFeMnGe. The multilayer spacer layer and the multilayer notch result in the spintronic device having a high spin polarization and a reduced critical current.

IPC Classes  ?

  • G11B 5/31 - Structure or manufacture of heads, e.g. inductive using thin film
  • G11B 5/127 - Structure or manufacture of heads, e.g. inductive
  • G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor

84.

PROACTIVE HARDENING OF DATA STORAGE SYSTEM

      
Application Number US2023021271
Publication Number 2023/249713
Status In Force
Filing Date 2023-05-06
Publication Date 2023-12-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Kommuri, Chakradhar

Abstract

Disclosed are systems and methods for proactively recovering files stored in flash storage devices. The method may be performed at a flash file system. The method may include receiving a write command targeting a first file in a flash memory. The method may also include generating a reference hash corresponding to the first file, and storing the reference hash in the flash memory. The method may also include receiving a read command targeting the first file. In response to receiving the read command, the method may also include: providing a request for a logical block address corresponding to the first file to the flash manager, and receiving a response for the read command. The method may also include, in accordance with a determination that one or more hashes do not map to the first file, performing a file recovery operation for a second file based on the one or more hashes.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

85.

RATE LEVELLING AMONG PEER DATA STORAGE DEVICES

      
Application Number US2023021538
Publication Number 2023/249720
Status In Force
Filing Date 2023-05-09
Publication Date 2023-12-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Muthiah, Ramanathan
  • Hahn, Judah Gamliel

Abstract

Example storage systems, data storage devices, and methods provide rate levelling among peer storage devices. A master storage device among peer storage devices receives host commands, determines the workload states of the peer storage devices, divides the data units in the host commands into data blocks for data striping, allocates the data blocks among the peer storage devices, and sends the data blocks to the peer storage devices using a peer communication channel.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

86.

ACTIVE TIME-BASED COMMAND PRIORITIZATION IN DATA STORAGE DEVICES

      
Application Number US2023021279
Publication Number 2023/244342
Status In Force
Filing Date 2023-05-07
Publication Date 2023-12-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Muthiah, Ramanathan
  • Hahn, Judah Gamliel
  • Sela, Rotem

Abstract

Disclosed are systems and methods providing active time-based prioritization in host-managed stream devices. The method includes receiving a plurality of host commands from a host system. The method also includes computing active times of open memory regions. The method also includes determining one or more regions that have remained open for more than a threshold time period, based on the active times. The method also includes prioritizing one or more host commands from amongst the plurality of host commands for completion, the one or more host commands having corresponding logical addresses belonging to the one or more regions, thereby (i) minimizing risk to data and (ii) releasing resources corresponding to the one or more regions.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

87.

DATA STORAGE DEVICE WITH SPLIT BURST SERVO PATTERN

      
Application Number US2023021398
Publication Number 2023/244349
Status In Force
Filing Date 2023-05-08
Publication Date 2023-12-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Yasuna, Kei
  • Guo, Guoxiao
  • Yokokawa, Ichiro

Abstract

Various illustrative aspects are directed to a data storage device, comprising: one or more disks; an actuating mechanism comprising one or more heads, and configured to position the one or more heads proximate to disk surfaces of the one or more disks; and one or more processing devices. The one or more processing devices are configured to: determine a first burst value based on an averaged value of a first set of one or more bursts; determine a second burst value based on an averaged value of a second set of one or more bursts; generate a position error signal (PES) based on the determined first burst value and the determined second burst value; and control a position of at least one head among the one or more heads based on the PES.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

88.

DATA STORAGE DEVICE WITH DYNAMIC MAPPING OF LOW-DENSITY PARITY CHECK (LDPC) ENGINES

      
Application Number US2023021080
Publication Number 2023/244334
Status In Force
Filing Date 2023-05-04
Publication Date 2023-12-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Nayak, Dattatreya B
  • N E, Karthik
  • Mohamed A A, Noor
  • Rashid, Yunas

Abstract

The devices, methods, and apparatuses of the present disclosure address a lack of parallelism in a typical approach by eliminating the static mapping of the two or more low-density parity check (LDPC) engines to a plurality of flash controllers. The devices, methods, and apparatuses of the present disclosure include a dynamic LDPC mapping to the plurality of flash controllers.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

89.

STORAGE SYSTEM AND METHOD FOR INFERENCE OF READ THRESHOLDS BASED ON MEMORY PARAMETERS AND CONDITIONS

      
Application Number US2023021081
Publication Number 2023/244335
Status In Force
Filing Date 2023-05-04
Publication Date 2023-12-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Sharon, Eran
  • Navon, Ariel
  • Bazarsky, Alexander
  • Avraham, David
  • Yanuka, Nika
  • Alrod, Idan
  • Rozenfeld, Tsiko Shohat
  • Zamir, Ran

Abstract

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

90.

DATA STORAGE DEVICE AND METHOD FOR ENABLING METADATA-BASED SEEK POINTS FOR MEDIA ACCESS

      
Application Number US2023021273
Publication Number 2023/244339
Status In Force
Filing Date 2023-05-06
Publication Date 2023-12-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Ramamurthy, Ramkumar
  • Muthiah, Ramanathan

Abstract

A data storage device and method for enabling metadata-based seek points for media access are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to identify a plurality of frames in video data that differ from surrounding frames by more than a threshold amount; store identifiers of the plurality of frames in the memory; and send the identifiers to the host to enable quick playback of the video data by the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

IPC Classes  ?

  • H04N 21/472 - End-user interface for requesting content, additional data or services; End-user interface for interacting with content, e.g. for content reservation or setting reminders, for requesting event notification or for manipulating displayed content
  • H04N 21/433 - Content storage operation, e.g. storage operation in response to a pause request or caching operations
  • H04N 21/432 - Content retrieval operation from a local storage medium, e.g. hard-disk
  • H04N 21/845 - Structuring of content, e.g. decomposing content into time segments

91.

SEMICONDUCTOR WAFER THINNED BY HORIZONTAL STEALTH LASING

      
Application Number US2023021274
Publication Number 2023/244340
Status In Force
Filing Date 2023-05-06
Publication Date 2023-12-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Wu, Yi
  • Yan, Junrong
  • Qian, Zhonghua
  • Zhou, Keming
  • Zhang, Kailei

Abstract

A method includes the step of thinning a semiconductor wafer by a horizontal stealth lasing process, and semiconductor wafers, dies and devices formed thereby. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by supporting an active surface of the wafer on a rotating chuck, and focusing a horizontally-oriented laser in multiple cycles at different radii within the rotating wafer. Upon completion of the multiple cycles, a portion of the wafer substrate may be removed, leaving the wafer thinned to its final thickenss. Thereafter, a vertical stealth lasing process may be performed to cut individual semicondcutor dies from the thinned wafer.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

92.

KEY VALUE DATA STORAGE DEVICE WITH TIERS

      
Application Number US2023021277
Publication Number 2023/244341
Status In Force
Filing Date 2023-05-07
Publication Date 2023-12-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Avraham, David
  • Bazarsky, Alexander
  • Zamir, Ran

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, determine whether the KV pair data corresponds to a first tier or a second tier, where the second tier has a lower performance requirement than the first tier, and program the value of the KV pair data as padding data when the KV pair data corresponds to the second tier. The determining is based on a received hint of the KV pair data, a relative performance of the KV pair data, and a length of the KV pair data. The controller is configured reclassify the KV pair data based on a read frequency of the KV pair data.

IPC Classes  ?

  • G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
  • G06F 3/06 - Digital input from, or digital output to, record carriers

93.

PRESERVATION OF VOLATILE DATA IN DISTRESS MODE

      
Application Number US2023021280
Publication Number 2023/244343
Status In Force
Filing Date 2023-05-07
Publication Date 2023-12-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Muthiah, Ramanathan
  • Vlaiko, Julian
  • Hahn, Judah Gamliel

Abstract

A data storage device having improved protections for in-flight data during a safety event, such as an autonomous-driving-vehicle collision. In an example embodiment, in response to a distress-mode indication signal, the device controller operates to prioritize more-recent data with respect to older counterparts of the same data stream for flushing from the volatile-memory buffers to the non-volatile memory. In addition, the device controller may operate to positively bias the flushed data towards better survivability and/or more-reliable routing.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

94.

FLASH TRANSLATION LAYER MAPPING FOR LARGE CAPACITY DATA STORAGE DEVICES

      
Application Number US2023021400
Publication Number 2023/244350
Status In Force
Filing Date 2023-05-08
Publication Date 2023-12-21
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Kelner, Vered
  • Frid, Marina
  • Genshaft, Igor

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

95.

DATA STORAGE DEVICE AND METHOD FOR HOST BUFFER MANAGEMENT

      
Application Number US2023021373
Publication Number 2023/239508
Status In Force
Filing Date 2023-05-08
Publication Date 2023-12-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Segev, Amir
  • Benisty, Shay

Abstract

A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

96.

DATA MIGRATION VIA DATA STORAGE DEVICE PEER CHANNEL

      
Application Number US2023021377
Publication Number 2023/239509
Status In Force
Filing Date 2023-05-08
Publication Date 2023-12-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Rozen, Amir
  • Segev, Amir

Abstract

Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

97.

LASER CUTTING WITH ELECTRON REMOVAL

      
Application Number US2023021394
Publication Number 2023/239510
Status In Force
Filing Date 2023-05-08
Publication Date 2023-12-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Zhang, Cong
  • Chiu, Hope
  • Huang, Yiqin
  • Zhong, Guocheng
  • Jiang, Weiting
  • Xue, Dongpeng

Abstract

The present disclosure generally relates to ensuring a plasma plume or cloud that forms during a laser cutting process does not lead to undesired re-deposition of material onto the substrate. At least one electrode is biased to draw the electrons of the plasma plume or cloud towards the electrode and away from the substrate. A vacuum port and/or a blower may be strategically located to ensure proper gas flow away from the substrate and hence, directing of the electrons away from the substrate. In so doing, material re-deposition is less likely to occur.

IPC Classes  ?

  • B23K 26/38 - Removing material by boring or cutting
  • B23K 26/354 - Working by laser beam, e.g. welding, cutting or boring for surface treatment by melting
  • B23K 26/142 - Working by laser beam, e.g. welding, cutting or boring using a fluid stream, e.g. a jet of gas, in conjunction with the laser beam; Nozzles therefor for the removal of by-products
  • B23K 26/402 - Removing material taking account of the properties of the material involved involving non-metallic material, e.g. isolators
  • B23K 26/70 - Auxiliary operations or equipment

98.

STORAGE SYSTEM AND METHOD FOR EARLY COMMAND CANCELATION

      
Application Number US2023020941
Publication Number 2023/235101
Status In Force
Filing Date 2023-05-04
Publication Date 2023-12-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Segev, Amir
  • Benisty, Shay

Abstract

A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

99.

WORKLOAD TRIGGERED DYNAMIC CAPTURE IN SURVEILLANCE SYSTEMS

      
Application Number US2023021358
Publication Number 2023/235112
Status In Force
Filing Date 2023-05-08
Publication Date 2023-12-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Muthiah, Ramanathan

Abstract

Systems and methods for managing write stream workload of video surveillance systems through playback workload triggered dynamic capture are described. A video camera may include a video image sensor for receiving video data. The video data may be written to a storage device. A request for access to the video data may then be received. An impact on a standard data write stream may be determined based on the time window determined for the access to the video data. At least one mitigation option may be initiated at the video image sensor as a result.

IPC Classes  ?

  • H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
  • H04N 21/274 - Storing end-user specific content or additional data in response to end-user request
  • H04N 5/77 - Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
  • H04N 5/92 - Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
  • H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils

100.

SYSTEMS AND METHODS OF IMPROVED MODULAR INVERSION WITH DIGITAL SIGNATURES

      
Application Number US2023020810
Publication Number 2023/235096
Status In Force
Filing Date 2023-05-03
Publication Date 2023-12-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Ilani, Ishai

Abstract

A method includes receiving a message and a digital signature associated with a signing party and the message, verifying authenticity of the digital signature using elliptic curve cryptography (ECC), and authenticating use of the message based, at least in part, on the confirmed authenticity of the digital signature. The verifying includes one or more computations involving computing modular inverses. Computing modular inverses includes identifying first and second integer of a modular inverse operation, performing a first iterative process that, at each iteration: (i) initializes a third integer with a pre-defined number of most significant bits of the first integer and a fourth integer with the pre-defined number of most significant bits of the second integer and (ii) computes a quotient and a remainder, determining a resultant inverse value using the quotient; and confirming the authenticity of the digital signature based, at least in part, on the resultant inverse value.

IPC Classes  ?

  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
  • H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
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