A method of manufacturing a semiconductor device, includes; preparing an insulated circuit substrate including a circuit layer having a main surface and a side surface inclined to a normal direction of the main surface; irradiating the side surface of the circuit layer with a laser beam so as to roughen at least a part of the side surface of the circuit layer and provide an oxide film on the roughened side surface of the circuit layer; and bonding a semiconductor chip to the main surface of the circuit layer via a solder layer.
Provided is a semiconductor device including a drift region of a first conductivity type which is provided in a semiconductor substrate, a buffer region of the first conductivity type which is provided in a back surface side of the semiconductor substrate relative to the drift region and which includes a first peak of a doping concentration and a second peak of the doping concentration which is provided in a front surface side of the semiconductor substrate relative to the first peak, and a first lifetime control region provided between the first peak and the second peak in a depth direction of the semiconductor substrate. An integrated concentration obtained from an upper end of the drift region to the second peak may be a critical integrated concentration or more in the depth direction of the semiconductor substrate.
A first conductive pattern includes a first input region overlapping a first semiconductor device and a second input region overlapping a second semiconductor device. An output electrode of the first semiconductor device and an output electrode of the second semiconductor device are connected with each other by a first wiring member. The output electrode of the second semiconductor device and a second conductive pattern are connected with each other by a second wiring member. A ratio of a current flowing from the second input region to the second conductive pattern via the second semiconductor device, relative to a current flowing from the first input region to the second conductive pattern via the first semiconductor device, is equal to or greater than 0.90 and equal to or less than 1.10.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a sintered metal such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups
A superjunction semiconductor device has: a semiconductor substrate of a first conductivity type; a buffer layer of the first conductivity type, provided on a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate; a drift layer of the first conductivity type, provided on the buffer layer and having an impurity concentration lower than that of the buffer layer; and a parallel pn structure having first column regions of the first conductivity type and second column regions of a second conductivity type repeatedly alternating one another in a direction parallel to the front surface. A subset of the first and second column regions are located in a termination structure portion and have depths that become shallower stepwise towards an end of the semiconductor substrate, where the second column regions are provided with bottoms thereof in the drift layer.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
This beverage supply device comprises an extractor 30, which introduces ground coffee beans and hot water into a cylinder 341 and extracts coffee, the device supplying the coffee extracted from the extractor 30 to a cup C, wherein the extractor 30 is provided with a cylindrical passage constituting member 35, which is disposed in a mode in which the inside of the extractor communicates with an upper surface opening of the cylinder 341, thereby constituting a passage 351 through which ground coffee beans and hot water pass, and which is elastically deformed by an external force and can thereby close the passage 351.
A47J 31/42 - Beverage-making apparatus with incorporated grinding or roasting means for coffee
A47J 31/36 - Coffee-making apparatus in which hot water is passed through the filter under pressure with hot water under liquid pressure with mechanical pressure-producing means
G07F 13/06 - Coin-freed apparatus for controlling dispensing of fluids, semiliquids or granular material from reservoirs with selective dispensing of different fluids or materials or mixtures thereof
There is provided a semiconductor device that includes a transistor portion and a diode portion, the semiconductor device including a drift region, a base region, an emitter region, and a plurality of trench portions, in which the transistor portion has a boundary region provided to be adjacent to the diode portion, a lifetime control region is provided from the diode portion, across the boundary region, to the transistor portion provided with the emitter region, in an array direction of the plurality of trench portions, the boundary region has a plug region of a second conductivity type which is provided to extend in an extension direction of the plurality of trench portions and which has a doping concentration higher than that of the base region, and a contact region and the base region are alternately arranged in the extension direction, at a front surface in the boundary region.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
A switching control circuit for a power supply circuit that includes an inductor configured to receive a rectified voltage corresponding to an alternating current (AC) voltage, and a transistor configured to control a current flowing through the inductor, the power supply circuit generating an output voltage from the AC voltage, the switching control circuit being configured to switch the transistor. The switching control circuit comprises: a signal output circuit configured to output a signal to turn on the transistor, after lapse of a first time period since the inductor current reaches a first predetermined value after the transistor is turned off, the first time period corresponding to a conduction period during which a parasitic diode of the transistor conducts; and a driver circuit configured to turn on the transistor based on the signal, and turn off the transistor, based on a feedback voltage corresponding to the output voltage.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
10.
WIRING STRUCTURE, SEMICONDUCTOR MODULE, AND VEHICLE
A conductive member constituting a wiring structure includes a first bonding section bonded to an electronic component, a second bonding section bonded to a connection target for the electronic component, and a raised section that protrudes upward from the first bonding section and is connected to the second bonding section. The conductive member has a wire member passage through which a wire member passes, and which is provided in at least a part of the raised section. The wire member passage enables the wire member to be disposed along the raised section from the first bonding section to the second bonding section such that the wire member intersects a surface of the raised section.
A semiconductor device, including first and second conductive patterns, a plurality of first semiconductor chips each having a switching device, a plurality of second semiconductor chips each having a diode device, a plurality of first wires, respectively coupling low-potential electrodes of the switching devices and the second conductive pattern, and a plurality of second wires, respectively coupling anode electrodes of the diode devices and the second conductive pattern. Lengths of the first and second wires are substantially equal. The first semiconductor chips and the second semiconductor chips are arranged on the first conductive pattern in two rows, each row being in a first direction and including at least one first semiconductor chip and at least one second semiconductor chip, the first direction being parallel to a predetermined side of the first conductive pattern. The first and second wires are each in a second direction orthogonal to the first direction.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H02M 7/537 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
Provided is a semiconductor device including: a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; and a buffer region provided between the drift region and the lower surface and having a higher doping concentration than the drift region. The buffer region has M doping concentration peaks provided at different positions in a depth direction of the semiconductor substrate, and a charge carrier coefficient α represented by Expression (1) is 2000 or more and 50000 or less in at least one integer i (i is an integer of 1 or more and M−1 or less).
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
13.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
Provided is a semiconductor device comprising: a first conductive drift region provided in a semiconductor substrate having a front surface and a back surface; and a first conductive buffer region provided closer to the back surface of the semiconductor substrate than the drift region in the depth direction of the semiconductor substrate, wherein the buffer region has a concentration peak group including one or more concentration peaks of doping concentration, the concentration peak group includes a first concentration peak provided closest to the back surface of the semiconductor substrate among the one or more concentration peaks in the depth direction of the semiconductor substrate, and the semiconductor substrate includes a first hydrogen peak, which is the atomic density peak of hydrogen, provided at the same depth as the depth position of the first concentration peak, or closer to the back surface of the semiconductor substrate than the depth position of the first concentration peak in the depth direction of the semiconductor substrate.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Provided is a semiconductor device that comprises: a base region of a second conductivity type that is disposed between a drift region and an upper surface of a semiconductor substrate; a first lifetime region that is disposed in a drift region further on a lower-surface side of the semiconductor substrate than the base region; and a second lifetime region that is disposed so as to be sandwiched by the first lifetime region in a first direction that is parallel to the upper surface of the semiconductor substrate and has a longer carrier lifetime than the first lifetime region. The width of the second lifetime region in the first direction is at least 0.2 times the thickness of the first lifetime region in a second direction that is perpendicular to the upper surface of the semiconductor substrate.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
The power conversion device includes: a DC-DC converter unit including a transformer having a coil substrate where a primary side coil is formed and a bus bar forming a secondary side coil, and converting a voltage of DC power input from a DC power supply into a different voltage; and a cooling portion where a cooling flow path through which a cooling liquid flows is provided and the DC-DC converter unit is disposed. The bus bar of the transformer has a cooling portion side fixed portion fixed to the cooling portion provided with the cooling flow path.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
H02M 3/00 - Conversion of dc power input into dc power output
H02M 7/00 - Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 7/537 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
A drift layer has a SJ structure with a parallel pn layer; an n+-type buffer layer is between the parallel pn layer and an n++-type drain layer. An impurity concentration of the n+-type buffer layer is adjusted to be at least equal to that of n-type column regions of the parallel pn layer, to be relatively low in a portion facing the parallel pn layer and approach the impurity concentration of the n-type column regions, and to increase closer to the n++-type drain layer. The impurity concentration of the n+-type buffer layer is adjusted so that an impurity concentration difference between the n+-type buffer layer and the n++-type drain layer near the border between the n+-type buffer layer and the n++-type drain layer is as small as possible. An impurity concentration distribution of the n+-type buffer layer is formed by stacking n+-type buffer layers in descending order of impurity concentration from the n++-type drain layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A laser gas analyzer includes a light emitting unit including a laser element configured to emit laser light having a target wavelength band including a wavelength of an absorption line spectrum of the target gas, and a modulated light generation unit configured to supply a drive current to the laser element so that the laser element sweeps and modulates the laser light to have the target wavelength band, and a light receiving unit including a light receiving element configured to receive the laser light passing through the target space and output a detection signal, and a light reception signal processing unit configured to analyze the target gas according to the detection signal from the light receiving element. The light emitting unit and the light receiving unit communicate with each other using the laser light.
G01N 21/39 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using tunable lasers
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
18.
SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE AND VEHICLE
A semiconductor module includes: a wiring board including a ceramic substrate and conductor patterns on a first surface of the ceramic substrate; a semiconductor element arranged on at least one of the conductor patterns on the first surface of the ceramic substrate; a sealing insulator that seals the wiring board and the semiconductor element; and an insulating member disposed on the first surface of the ceramic substrate in a gap between the conductor patterns that are adjacent to each other, the insulating member extending in an extending direction of the gap and dividing an area in the gap where the sealing insulator fills the gap so that the insulating member is separate from respective edges of the conductor patterns adjacent to each other.
C02F 5/00 - Softening water; Preventing scale; Adding scale preventatives or scale removers to water, e.g. adding sequestering agents
C02F 5/08 - Treatment of water with complexing chemicals or other solubilising agents for softening, scale prevention or scale removal, e.g. adding sequestering agents
C02F 5/10 - Treatment of water with complexing chemicals or other solubilising agents for softening, scale prevention or scale removal, e.g. adding sequestering agents using organic substances
A semiconductor device including a semiconductor substrate; a first parallel pn layer in which first first-conductivity-type column regions and first second-conductivity-type column regions repeatedly alternate with one another in an active region; a second parallel pn layer in which second first-conductivity-type column regions and second second-conductivity-type column regions repeatedly alternate with one another, in a termination region; a device structure provided between the first main surface of the semiconductor substrate and the first parallel pn layer; a first electrode provided at the first main surface and electrically connected to the device structure; and a second electrode provided at the second main surface of the semiconductor substrate. The plurality of second first-conductivity-type column regions and the plurality of second second-conductivity-type column regions are disposed in concentric shapes surrounding a perimeter of the first parallel pn layer in a plan view.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
When a semiconductor unit is heated, a heater having a flat heating surface is used for performing heating in a state in which a lower surface of an insulated circuit board is placed on the heating surface. When the semiconductor unit is cooled, a cooler having a cooling surface including a pair of support portions is used for performing cooling in which a lower surface of a pair of outer regions of the insulated circuit board are respectively placed to be contact with the pair of support portions, and in which a central region between the pair of outer regions of the insulated circuit board is pressed downward so as to be downward convex.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
A semiconductor device, including a semiconductor substrate, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a fourth semiconductor region, a plurality of trenches provided in the semiconductor substrate, a plurality of first electrodes respectively provided in the plurality of trenches, an interlayer insulating film, a second electrode, and a third electrode. The trenches are disposed at equal intervals, so as to have a plurality of mesa portions formed therebetween. The trenches include a plurality of gate trenches and a plurality of dummy trenches. The first electrodes include a plurality of gate electrodes and a plurality of dummy electrodes. The plurality of mesa portions includes a plurality of first mesa portions, each first mesa portion being adjacent to one of the gate trenches at least at one sidewall thereof, and including one of the second semiconductor regions that has a floating potential.
A semiconductor device including a semiconductor unit that has a first arm part, which includes: first and second semiconductor chips having first and second control electrodes on their front surfaces, a first circuit pattern where the first and second semiconductor chips are disposed, a second circuit pattern to which the first and second control electrodes are connected, and a first control wire electrically connecting the first and second control electrodes and the second circuit pattern sequentially in a direction; and a second arm part, which includes third and fourth semiconductor chips having third and fourth control electrodes on their front surfaces, a third circuit pattern where the third and fourth semiconductor chips are disposed, a fourth circuit pattern to which the third and fourth control electrodes are connected, and a second control wire electrically connecting the third and fourth control electrodes and the fourth circuit pattern sequentially in the direction.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A semiconductor module, including a first main wiring line connecting portion and a second main wiring line connecting portion, and a main output wiring line connecting portion is provided. The circuit board includes a circuit region in which the first circuit and the second circuit are arranged alongside each other in the first direction, and a first connecting region and a second connecting region arranged sandwiching the circuit region in a second direction orthogonal to the first direction. The first main wiring line connecting portion and the second main wiring line connecting portion are provided in the first connecting region, and the main output wiring line connecting portion is provided in the second connecting region.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
Provided is a semiconductor device including: a semiconductor substrate; gate trench portions; an emitter electrode; a mesa portion; an emitter region of a first conductivity type provided on an upper surface of the mesa portion and in contact with the gate trench portions; a contact region of a second conductivity type provided on the upper surface of the mesa portion; a base region of a second conductivity type provided below the emitter region and the contact region, in contact with the gate trench portions, and having a lower doping concentration than the contact region; a drift region of a first conductivity type provided below the base region and having a lower doping concentration than the emitter region; and a high resistance portion provided between the emitter electrode and the base region in a depth direction of the semiconductor substrate and having a higher resistance than the emitter region.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
26.
SENSOR SYSTEM AND METHOD FOR MEASURING GAS LIQUID RATIO
A sensor system for measuring a gas liquid ratio of a two-phase fluid that flows through a pipe is provided. The sensor system includes a transmitter configured to transmit a radio wave into the pipe. The sensor system includes a receiver configured to receive the radio wave through the pipe. The sensor system includes a controller configured to calculate the gas liquid ratio based on both the radio wave received by the receiver and a decay time taken for attenuation of the radio wave after the transmitter terminates the transmission of the radio wave.
G01N 22/00 - Investigating or analysing materials by the use of microwaves or radio waves, i.e. electromagnetic waves with a wavelength of one millimetre or more
G01F 5/00 - Measuring a proportion of the volume flow
A semiconductor device includes a semiconductor chip that has a first main electrode on a rear surface thereof and a second main electrode on a front surface thereof, and a wiring layer electrically connected to at least one of the first main electrode or the second main electrode. The wiring layer includes a conductive member that is disposed on a front surface of the wiring layer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
The present invention provides a joining that suppresses ion migration and also has excellent corrosion resistance, high bonding strength, and high reliability at the joining, and a semiconductor device. The present invention provides semiconductor joinings comprising: at least two semiconductor constituent members; and silver-containing bonding material layers that bond the semiconductor constituent members, in which a corrosion inhibitor coating layer is provided in contact with the silver-containing bonding material layers, and a semiconductor device including the same.
An n+-type SiC substrate constituting an n+-type drain region contains a concentration of nitrogen, which is a donor, within a predetermined range (predetermined impurity concentration of the n+-type drain region) and, as impurities other than the nitrogen, contains boron, aluminum, and titanium such that a sum of respective concentrations of the boron, aluminum, and titanium is an amount that does not affect the n-type impurity concentration of the n+-type SiC substrate (impurity concentration of the n+-type drain region). The boron, aluminum, and titanium in the n+-type SiC substrate function as a lifetime killer of majority carriers. The boron concentration of the n+-type SiC substrate is in a range of 5×1016/cm3 to 1×1017/cm3. The aluminum concentration and the concentration of the titanium concentration of the n+-type SiC substrate are each within a range of 1×1016/cm3 to 5×1016/cm3.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A semiconductor device includes an elongated cooler through which a refrigerant flows; a plurality of semiconductor modules, each including one or more semiconductor elements; and a passive element configured to drive the plurality of semiconductor modules, the cooler includes a first cooling surface; and a second cooling surface opposing the first cooling surface, the plurality of semiconductor modules is arrayed in a longitudinal direction of the cooler and is coupled to, or is in contact with, the first cooling surface, and the passive element is coupled to, or is in contact with, the second cooling surface.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
A semiconductor device including a semiconductor substrate, a parallel pn layer and a device structure provided in the semiconductor substrate, first and second electrodes respectively provided at two main surfaces of the semiconductor substrate, the first electrode being electrically connected to the device structure. The parallel pn layer includes first-conductivity-type column regions and second-conductivity-type column regions that are adjacently disposed and repeatedly alternate with one another in a first direction parallel to the first main surface, that each extend in a second direction parallel to the first main surface and orthogonal to the first direction, and that are of a same impurity concentration. A portion of the second-conductivity-type column regions is shorter than the rest thereof. The parallel pn layer has a first portion and a second portion respectively closer to the first and second main surfaces, the first portion being more p-rich, and less n-rich, than the second portion.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor device having a load. The semiconductor device including: an output element configure to connect to the load, the output element being switchable to operate the load; a drive circuit which outputs a drive signal for driving the output element to switch; a detection circuit which compares a state signal, indicative of an operating state of the output element, with a detection threshold, to thereby detect an abnormal level of the operating state; an abnormal level notification circuit which informs an outside of the detected abnormal level; an external terminal configured to receive an external signal for adjusting the detection threshold; and a detection threshold adjustment circuit which adjusts the detection threshold on a basis of the received external signal.
A transformer includes a primary winding, a feedback winding, and a non-feedback winding having substantially equal winding widths in an axial direction of a bobbin.
H01F 27/32 - Insulating of coils, windings, or parts thereof
H01F 27/30 - Fastening or clamping coils, windings, or parts thereof together; Fastening or mounting coils or windings on core, casing, or other support
34.
SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
Provided is a semiconductor device including an active section having a transistor section and a diode section, and an edge termination structure section provided to an outer circumference of the active section, in which the transistor section has a drift region of a first conductivity type which is provided in a semiconductor substrate, a base region of a second conductivity type which is provided above the drift region, a trench portion extending from a front surface of the semiconductor substrate to the drift region, and a trench bottom portion of the second conductivity type which is provided in a lower end of the trench portion, and the diode section is provided between a transistor section in proximity to the edge termination structure section, and the edge termination structure section in a top view.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a semiconductor chip with an electrode, an insulated circuit board including an insulating board and a circuit pattern formed thereon. The circuit pattern has the semiconductor chip on a front surface thereof. The semiconductor device further includes a plurality of conductive posts, each having a lower end bonded to at least one of the front surface of the circuit pattern or the electrode of the semiconductor chip, and each extending vertically upward with respect to a front surface of the insulated circuit board, a printed circuit board bonded to an upper end side of each conductive post, a spacer disposed between the printed circuit board and the insulated circuit board such that a front surface of the printed circuit board faces the insulated circuit board, and a pressing member disposed above the spacer having the printed circuit board therebetween.
H05K 1/14 - Structural association of two or more printed circuits
H05K 3/36 - Assembling printed circuits with other printed circuits
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY (Japan)
Inventor
Tawara, Takeshi
Harada, Shinsuke
Kato, Masashi
Fukui, Takuya
Abstract
This silicon carbide semiconductor substrate comprises: a first-conductive type silicon carbide semiconductor substrate (1); a first-conductive type first semiconductor layer (2) having an impurity concentration lower than that of the silicon carbide semiconductor substrate (1); a second-conductive type second semiconductor layer (3); a first-conductive type first semiconductor region (7); a trench (16); a first base region (4); a second-conductive type second base region (5); and co-doped regions (26, 26') doped with aluminum and nitrogen, as a region of the first semiconductor layer (2) between first base region (4) and the second base region (5), and a region of the first semiconductor layer (2) closer to the silicon carbide semiconductor substrate (1) than the first base region (4) and the second base region (5). The carrier lifetime of the co-doped regions (26, 26') is 0.01 μs or less.
A transmitter circuit coupled to a receiver circuit through wiring. The transmitter circuit transmits, as an input signal, either a first signal of a rectangular waveform having a logic level that changes according to first data, or a second signal having a slope that changes corresponding to second data. The receiver circuit includes an analog-to-digital (AD) converter receiving the input signal through the wiring, and a processing circuit configured to process an output of the AD converter, to thereby determine whether the input signal is the first signal or the second signal, and upon determining that the input signal is the first signal or a second signal, acquire the first data or the second data based on the logic level of the first signal or the slope of the second signal, as the case may be.
A semiconductor device includes: a first transistor having a first electrode, a second electrode, and a third electrode coupled to a load; a second semiconductor having a first electrode, a second electrode, and a third electrode configured to output a second current corresponding to a first current that flows through the load; and a third transistor coupled in series with the second transistor, to thereby receive the second current; an output circuit configured to output a second voltage by amplifying a difference between a first voltage at the third electrode of the first transistor and a reference voltage, and a fourth voltage by amplifying a difference between a third voltage at the third electrode of the second transistor and the reference voltage; and an operational amplifier configured to control the third transistor, based on the second and fourth voltages such that the first voltage and the third voltage match.
An integrated circuit includes: a power supply line configured to receive a power supply voltage; a constant current source electrically coupled to the power supply line;
An integrated circuit includes: a power supply line configured to receive a power supply voltage; a constant current source electrically coupled to the power supply line;
a reference voltage circuit electrically coupled to the constant current source; and a first resistor having two ends, one end thereof being electrically coupled to the constant current source, and the other end thereof being electrically coupled to the reference voltage circuit. The reference voltage circuit is a bandgap circuit including a plurality pf bipolar devices. The first resistor is configured to decrease a leakage current in the bipolar devices when a temperature thereof rises.
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
A device includes a substrate, a drift region in the substrate, a base region above the drift region; a first high concentration region selectively formed in a part on a surface side of the base region and having a concentration higher than the drift region; a trench portion formed in a front surface of the substrate and including extending portions; and mesa portions between the extending portions. The mesa portions includes first mesa portions having the first high concentration region and second mesa portions not having the first high concentration region, the trench portion includes a first trench portion having an first conductive portion (a gate conductive potion) and adjacent to the first mesa portion, a second trench portion having the first conductive portion and adjacent to the second mesa portion, and a third trench portion having an second conductive portion and adjacent to the first or second mesa portion.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Provided is a semiconductor device comprising: a first conductivity type drift region provided on a semiconductor substrate having a front surface and a reverse surface; and a first conductivity type or second conductivity type reverse-surface-side region that is provided further to the reverse surface side of the semiconductor substrate than the drift region in the semiconductor substrate and has a higher atomic density than the drift region. The distribution of the atomic density in the rear-surface-side region includes: a gentle gradient region in which the atomic density of a dopant increases from the reverse surface side toward the front surface side of the semiconductor substrate in the depth direction of the semiconductor substrate; a steep gradient region that is provided further to the front surface side than the gentle gradient region and in which the atomic density of the dopant increases by a greater gradient of the atomic density than in the gentle gradient region; a peak region that is provided further to the front surface side than the steep gradient region and includes a peak in the distribution of the atomic density of the dopant; and a decreasing region that is provided between the peak region and the drift region and in which the atomic density of the dopant decreases toward the drift region in the depth direction of the semiconductor substrate.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
The present invention provides a simplified configuration at a lower cost, and makes assembly work and installation work easier. A semiconductor module (1) is provided with: a metal base plate (11) having an upper surface on which a semiconductor unit (2) including a semiconductor element (6) is mounted; and a case (3) that is bonded to the upper surface of the metal base plate and surrounds the semiconductor unit. The case comprises: a projecting part (34) protruding toward the metal base plate; and a through hole (35) formed so as to at least partially overlap the projecting part in plan view. The metal base plate comprises a through hole (11b) with which the projecting part can be engaged.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
Provided is a semiconductor device including: a buffer region having one or more doping concentration peaks having a higher doping concentration than a drift region; and a lifetime control portion provided at a position overlapping a shallowest concentration peak closest to a lower surface of a semiconductor substrate among the doping concentration peaks provided in the buffer region, and in which a carrier lifetime shows a local minimum value, in which the semiconductor substrate has a critical depth position at which an integrated value, which is obtained by integrating doping concentrations from an upper end of the drift region toward the lower surface, reaches a critical integrated concentration of the semiconductor substrate, and a depth position at which the carrier lifetime shows the local minimum value in the lifetime control portion is arranged closer to the lower surface than the critical depth position.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
A semiconductor device includes case resin having frame part defining space in which semiconductor chip is disposed and bottom part located under the frame portion; external connection terminal having external terminal partially embedded in the frame part, and internal terminal disposed on the bottom part to extend from the external terminal into the space; wire electrically connecting the semiconductor chip and the internal terminal; and sealing resin formed in the space to cover the semiconductor chip, the wire, and the internal terminal. The internal terminal has rectangular connecting portion, and step portions disposed at opposite ends of the connecting portion, respective portions of the upper surfaces of the step portions facing each other are covered with vibration controlling portions implemented by the case resin, and the sealing resin is filled in first grooves exposing other portions of the upper surfaces of the step portions.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Provided is a semiconductor device provided with a transistor section, the semiconductor device including a drift region of a first conductivity type which is provided in a semiconductor substrate, a plurality of trench portions extending from a front surface of the semiconductor substrate to the drift region, an emitter region of the first conductivity type which has a doping concentration higher than a doping concentration of the drift region and which is provided to extend from a trench portion to an adjacent trench portion among the plurality of trench portions on the front surface of the semiconductor substrate, and a trench bottom portion of a second conductivity type which is provided to a lower end of the trench portion, in which the transistor section has an electron passage region in which the trench bottom portion is not provided in a top view.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Provided is a semiconductor device including a semiconductor substrate. The semiconductor substrate has: an active portion; and a plurality of gate trench portions provided in the active portion on an upper surface of the semiconductor substrate and extending along an extending direction. The semiconductor device further includes: a gate runner provided between the active portion and an end side of the semiconductor substrate; and a plurality of gate polysilicon disposed apart from each other along the end side and respectively connecting the plurality of gate trench portions to the gate runner.
Provided is a semiconductor device including: a first trench contact portion provided to an inside of a contact region; a second trench contact portion provided to an inside of an emitter region; a first plug portion of a second conductivity type, which is provided in contact with a lower end of the first trench contact portion and has a higher concentration than a base region; and a second plug portion of a second conductivity type, which is provided in contact with a lower end of the second trench contact portion, is provided to a position closer to a lower surface than the first plug portion, and has a higher concentration than the base region.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Provided is a semiconductor device in which one mesa portion of two mesa portions in contact with a gate trench portion is an active mesa portion in which an emitter region of a first conductivity type having a doping concentration higher than that of a drift region is arranged in contact with the gate trench portion, the other mesa portion of two mesa portions in contact with the gate trench portion is a dummy mesa portion having no emitter region, and a dummy contact resistance which is a resistance of the dummy mesa portion and an emitter electrode is 1000 times or more as high as an active contact resistance which is a resistance of the active mesa portion and the emitter electrode.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A semiconductor device includes: a semiconductor substrate; a plurality of trenches provided on a top surface side of the semiconductor substrate; am insulated gate electrode structure buried inside the respective trenches; an interlayer insulating film deposited on top surfaces of the semiconductor substrate and the insulated gate electrode structure; and a silicide layer deposited at a bottom of a contact hole penetrating the interlayer insulating film so as to be in contact with the top surface of the semiconductor substrate interposed between the trenches adjacent to each other, wherein at least a part of a bottom surface of the silicide layer is located at a higher position than a bottom surface of the interlayer insulating film.
Provided is a processing circuit for data of multiple bits including a first bit, a second bit, and a third bit, the processing circuit including a memory unit for storing a bit value of each bit, a first memory code, and a second memory code, a code generation unit for generating a first generation code indicating whether bit values of the first bit and the second bit stored by the memory unit are identical, and a second generation code indicating whether bit values of the second bit stored and the third bit stored by the memory unit are identical, and a determination unit for determining whether, based on a comparison result of between the first memory code and the first generation code and a comparison result between the second memory code and the second generation code, an error has occurred in the bit value of the second bit.
A semiconductor apparatus includes a substrate, a semiconductor device arranged on an upper surface of the substrate, a lead frame bonded to an upper surface of the semiconductor device via a bonding material, the lead frame having a first recess on an upper surface thereof, a wire connected to the first recess, and a resin that seals the substrate, the semiconductor device, the lead frame, and the wire.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/049 - Containers; Seals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
H01L 23/373 - Cooling facilitated by selection of materials for the device
A semiconductor device includes a semiconductor module that includes: an insulating circuit board, a semiconductor chip provided on a main surface of the insulating circuit board, and an external connection terminals provided on the main surface of the insulating circuit board; an external printed circuit board provided so as to face a main surface of the semiconductor module, the external printed circuit board having a through hole into which the external connection terminal is inserted; and an elastic member provided between the main surface of the semiconductor module and the external printed circuit board so as to apply a pressing force to the main surface of the semiconductor module.
A semiconductor device has: a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the first conductivity type; a trench; a gate insulating film; a gate electrode; a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type. The third semiconductor region is provided between the gate insulating film on a sidewall of the trench and the first semiconductor region. The fourth semiconductor region is provided between the first semiconductor region and the third semiconductor region, and has an impurity concentration higher than that of the first semiconductor region.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
55.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
A silicon carbide semiconductor device, including a semiconductor substrate, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a plurality of trenches, a plurality of gate electrodes respectively provided in the trenches, a first conductive film, a first electrode, a second electrode, a plurality of first high-concentration regions, a plurality of second high-concentration regions, and a second conductive film. The first semiconductor region has a first portion and a plurality of second portions respectively at positions facing the plurality of second high-concentration regions in a depth direction. The second conductive film forms a Schottky contact with the plurality of second portions of the first semiconductor region, such that each junction surface between the second conductive film and the first semiconductor region forms a Schottky barrier of a Schottky barrier diode.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
According to the present invention, a p-type impurity concentration profile (41) in the depth direction of a p-type base region is controlled by means of ion implantation into the p-type base region in two or more stages. The ion implantation into the p-type base region in two or more stages are performed at different accelerating voltages, while setting the dose amount such that the higher the accelerating voltage is, the lower the dose amount is. With respect to the p-type impurity concentration profile (41) in the depth direction of the p-type base region, the impurity concentration asymmetrically decreases from a depth position (D1), at which the impurity concentration is highest, toward the n+type source region side and toward the n+type drain region side. With respect to the p-type impurity concentration profile (41), the impurity concentration decreases in stages at one or more different depth positions on the n+ type drain region side from the depth position (D1). Consequently, the present invention is able to ameliorate the trade-off relationship between increase of a gate threshold voltage and decrease of an on-resistance.
A cooler has a cooling main body portion that includes: a cooling wall in the Y direction including a first face with a heat generator thereon, and a second face opposite thereto; first and second flow path extending in the Y direction, the first flow path allowing refrigerant to flow in, and the second flow path allowing the refrigerant to flow out; cooling flow paths with a part of a wall surface comprising the second face; a partition spaced from the cooling wall in the Z direction, separating the first and the second flow paths from the cooling flow paths; and a first narrowing portion at a communication portion between a cooling flow path and the first flow path. The cooling flow paths are positioned between the first and flow paths and the cooling wall, and cause the first and the second flow path to communicate in the X direction.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
An integrated circuit for a power supply circuit of a resonant type, the power supply circuit including a resonant circuit including a coil and a capacitor coupled in series, and a switching device controlling a resonant current flowing through the resonant circuit. The integrated circuit is configured to drive the switching device, and includes: a terminal configured to receive a voltage corresponding to the resonant current; a first voltage output circuit configured to output a first voltage obtained by multiplying the voltage at the terminal by a first factor; a second voltage output circuit configured to output a second voltage obtained by multiplying the voltage at the terminal by a second factor smaller than the first factor; and a driver circuit configured to drive the switching device, based on the first and second voltages, and a feedback voltage corresponding to an output voltage of the power supply circuit.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/00 - Conversion of dc power input into dc power output
A switching control circuit for a power supply circuit including a first coil, a second coil configured to generate a voltage corresponding to a current flowing through the first coil, and a switching device configured to control the current flowing through the first coil. The switching control circuit controls switching of the switching device, and includes: a drive signal generator circuit configured to generate a driving signal, based on a feedback voltage corresponding to the output voltage; a driver circuit configured to switch the switching device, in response to the driving signal; a regulator configured to generate a power supply voltage of a target level to operate the driver circuit, and a drive current of the driver circuit; and a control circuit configured to control the regulator to decrease the drive current in response to the drive current reaching a predetermined value.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
60.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device, including a semiconductor chip, a case having an opening formed therein and an inner wall communicating with the opening, and a sealing member. The inner wall surrounds a housing space for accommodating the semiconductor chip. The sealing member fills the housing space to seal the semiconductor chip. The sealing member has a side surface and a sealing surface. The side surface has a contact area contacting the inner wall of the case. The contact area is positioned, in a depth direction of the semiconductor device, closer to the semiconductor chip than is the sealing surface of the sealing member.
H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/08 - Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
A silicon carbide semiconductor device, including a semiconductor substrate having an active region and a termination region that surrounds the active region in a top view, a first parallel pn layer provided in the semiconductor substrate in the active region, a second parallel pn layer provided in the semiconductor substrate in the termination region, a device structure provided in the active region, a first electrode electrically connected to the device structure, a second electrode, a first semiconductor region selectively provided in the termination region, and a second semiconductor region provided between the second parallel pn layer and the first semiconductor region, and in contact with the first semiconductor region. The second parallel pn layer is provided apart from the first semiconductor region, at a position deeper than the first semiconductor region and closer to an end of the semiconductor substrate than an outer end of the first semiconductor region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
62.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
By a first ion-implantation of a p-type impurity, first and second p+-type regions for mitigating electric field of trench bottoms are formed in surface regions of an n−-type epitaxial layer that constitutes an n−-type drift region. Thereafter, a second ion-implantation of an n-type impurity for reverting a portion of each of the first p+-type regions to the n−-type, and a third ion-implantation of an n-type impurity for an entire surface of the n−-type epitaxial layer, are performed. By the second ion-implantation, first current spreading layer (CSL) portions that constituting n-type current spreading regions are formed facing the first p+-type regions in the depth direction. By the third ion-implantation, the first CSL portions have a predetermined n-type impurity concentration, and second CSL portions constituting the n-type current spreading regions are formed between the first and second p+-type regions and are in contact with the first CSL portions.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A silicon carbide semiconductor device, including a semiconductor substrate; a first semiconductor region and a second semiconductor region provided in the semiconductor substrate; a plurality of third semiconductor regions selectively provided in the semiconductor substrate, a plurality of first and second trenches penetrating through the second and third semiconductor regions and reaching the first semiconductor region; a plurality of gate electrodes respectively provided in the first trenches; a plurality of conductive films respectively embedded in the second trenches, junction interfaces between the first semiconductor region and the conductive films forming a plurality of Schottky barriers; a first electrode and a second electrode; and a plurality of Schottky barrier diodes that respectively include the plurality of Schottky barriers. Each conductive film includes first and second metal films, the second metal film being closer to a center of the respective second trench and having a lower electrical resistivity than the first metal film.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
64.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a support, a semiconductor module, a heat transfer medium, and a first frame member. The semiconductor module includes a semiconductor chip and a resin member sealing the semiconductor chip, and is mounted on the support via the heat transfer medium. The first frame member is disposed on the semiconductor module. The first frame member has a first frame portion that covers an edge portion of an upper surface of the semiconductor module, and a first opening portion formed in the first frame portion for exposing the semiconductor module. The first frame member is fixed to the support by screws.
Provided is a semiconductor device in which doping concentration peaks in a buffer region each have an apex at which the doping concentration shows a maximum, a lower tail in which the doping concentration monotonously decreases from the apex toward a lower surface, and an upper tail in which the doping concentration monotonously decreases from the apex toward an upper surface. At least one of the doping concentration peaks in the buffer region is a gradual concentration peak of which a slope ratio calculated by dividing the absolute value of the slope of the upper tail by the absolute value of the slope of the lower tail is 0.1 to 3 inclusive.
Provided is a semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion. The device may include a first conductivity type drift region provided in a semiconductor substrate, a second conductivity type base region provided above the drift region, a first conductivity type emitter region provided above the base region and having a doping concentration higher than that of the drift region, and a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region. The contact region includes a first contact portion provided on a front surface of the substrate, and a second contact portion having a doping concentration different from that of the first contact portion and provided alternately with the first contact portion in a trench extending direction on a side wall of the first trench portion.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A semiconductor device having a connecting region between an active region and an edge region. The semiconductor device including a semiconductor substrate, a first semiconductor layer provided on the semiconductor substrate, a second semiconductor layer provided on the first semiconductor layer, a plurality of first semiconductor regions selectively provided in the second semiconductor layer, a plurality of first and second trenches penetrating through the first semiconductor regions and the second semiconductor layer, a plurality of gate electrodes provided in the first trenches, via a plurality of gate insulating films, respectively, and a plurality of Schottky electrodes respectively provided in the second trenches. The semiconductor substrate, the first and second semiconductor layers, the first semiconductor regions, the first trenches, the gate electrodes and the gate insulating films are provided in the active region. The second trenches and the Schottky electrodes are provided in both the active region and the connecting region.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY (Japan)
Inventor
Kumagai, Naoki
Okada, Masakazu
Harada, Shinsuke
Abstract
A superjunction semiconductor device having a termination structure portion surrounding an active region in a plan view. The device includes: a semiconductor substrate; a first semiconductor layer provided on the semiconductor substrate; and a parallel pn structure and a channel stopper provided in the first semiconductor layer. The channel stopper surrounds the parallel pn structure in the plan view, and contacts the parallel pn structure in the termination structure portion. The parallel pn structure includes a plurality of first columns each having a first width and a plurality of second columns each having a second width that repeatedly alternate one another parallel to the main surface. In a region of the parallel pn structure contacting the channel stopper, a product of the second width and an impurity concentration of the second columns is less than a product of the first width and an impurity concentration of the first columns.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A semiconductor device includes a cooling base board and an insulated circuit substrate. On a front surface of an insulated board on the insulated circuit substrate, a high potential circuit pattern on which a semiconductor chip is mounted, an intermediate potential circuit pattern on which a semiconductor chip is mounted, a low potential circuit pattern, and a control circuit pattern are disposed so as to straddle a center line of the cooling base board. The intermediate potential circuit pattern includes a second chip mounting region, an output wiring connection region and an interconnect wiring region that form a U-shaped portion in which the high potential circuit pattern having a semiconductor chip thereon is disposed. The control circuit pattern is disposed so as to straddle the center line and faces the opening of the U-shaped portion.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
70.
GATE VOLTAGE DETERMINATION APPARATUS, GATE VOLTAGE DETERMINATION METHOD, GATE DRIVING CIRCUIT AND SEMICONDUCTOR CIRCUIT
Provided is a gate voltage determination apparatus of a MOS transistor having a gate electrode, a gate insulating film and a channel region, the gate voltage determination apparatus including: a characteristic acquisition unit configured to acquire current-voltage characteristics showing a relationship between a gate current flowing through the gate electrodes and a gate voltage when the gate voltage applied to the gate electrode is changed from a higher voltage side to a lower voltage side; and a voltage determination unit configured to determine, based on a value of the gate voltage at which the gate current shows a peak waveform in the current-voltage characteristics, an off-gate voltage to be applied to the gate electrode when turning off the MOS transistor.
A semiconductor device, including: a thermistor for temperature detection; a series resistor selection circuit including a series resistor group connected in series with the thermistor, the series resistor selection circuit being configured to select a series resistor from the series resistor group according to a selection signal; an analog/digital (A/D) converter that performs A/D conversion on a divided voltage obtained by dividing an internal power supply voltage between the thermistor and the selected series resistor to generate divided voltage data, and outputs the divided voltage data; and a control circuit. The control circuit, during a period of selecting the series resistor, controls the A/D converter to operate in a low bit count mode, such that the selected series resistor causes the divided voltage data to fall within a predetermined voltage range, and controls the A/D converter to operate in a high bit count mode after selecting the series resistor.
G01K 7/24 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit
Provided is a semiconductor device comprising a semiconductor substrate provided with a drift region of a first conductivity type. The semiconductor substrate has an active part and trench portions provided in the active part in the upper surface of the semiconductor substrate. The active part includes a first region in which trench portions are arrayed at a first trench interval in the array direction and a second region in which trench portions are arrayed at a second trench interval larger than the first trench interval in the array direction. The first region has a second-conductivity type first bottom region extending over the bottoms of at least two of the trench portions, and the second region has a second-conductivity type second bottom region provided at the bottom of one of the trench portions.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
A magnetic field apparatus includes a main magnet that generates a magnetic field with respect to an armature, a member made of a soft magnetic material and disposed adjacent to an end surface of the main magnet on a side opposing the armature, an auxiliary magnet that increases a magnetic flux of a magnetic pole of the main magnet on the side opposing the armature and disposed adjacent to the main magnet and the member in a relative moving direction between the magnetic field apparatus and the armature, and a restricting part that restricts the magnetic flux of the main magnet passing through an end surface of the member along a third direction that is perpendicular to both a first direction in which the main magnet and the armature oppose each other, and a second direction corresponding to the relative moving direction between the magnetic field apparatus and the armature.
A semiconductor device includes a semiconductor chip, a bonding member, and a planar laminated substrate having the semiconductor chip bonded to a front surface thereof via the bonding member. The laminated substrate includes a planar ceramic board, a high-potential metal layer, a low-potential metal layer, an intermediate layer. The planar ceramic board contains a plurality of ceramic particles. The high-potential metal layer contains copper and is bonded to a first main surface of the ceramic board. The low-potential metal layer contains copper, is bonded to a second main surface of the ceramic board, and has a potential lower than a potential of the first main surface of the high-potential metal layer. The intermediate layer is provided between the second main surface and the low-potential metal layer and includes a first oxide that contains at least either magnesium or manganese.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device (100) comprises: a plurality of trenches that are provided farther below a base region (14) from an upper surface of a semiconductor substrate (10), the trenches including a gate trench (G) and a dummy trench (E); a first lower end region (202) of a second conductivity type that is provided in contact with the lower ends of at least two trenches including a gate trench; a well region (11) of the second conductivity type that is disposed at a position different from the first lower end region in top view, that is provided farther below the base region from the top surface of the semiconductor substrate, and that has a higher doping concentration than the base region; and a second lower end region (205) of the second conductivity type that is provided between the first lower end region and the well region so as to be separated from the first lower end region and the well region in top view, and that is provided in contact with the lower end of at least one trench including a gate trench.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
Provided is a semiconductor device (100) comprising: a plurality of trench portions which are provided from an upper surface of a semiconductor substrate (10) to below a base region (14), and include a gate trench portion (G) and a dummy trench portion (E); a first lower end region (202) of a second conductivity type provided in contact with the lower end of two or more trench portions including the gate trench portion; a well region (11) of the second conductivity type which is disposed in a position different from the first lower end region in a top view, provided from the upper surface of the semiconductor substrate to below the base region, and has a higher doping concentration than the base region; and a second lower end region (205) of a second conductivity type which is provided between the first lower end region and the well region in the top view, is separated from the first lower end region and the well region, and is in contact with the lower end of one or more trench portions including the gate trench portion.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
A magnetic field apparatus includes a main magnet that generates a magnetic field with respect to an armature, a member made of a soft magnetic material and disposed adjacent to an end surface of the main magnet on a side opposing the armature, an auxiliary magnet that increases a magnetic flux of a magnetic pole of the main magnet on the side opposing the armature and disposed adjacent to the main magnet and the member in a relative moving direction between the magnetic field apparatus and the armature, and a restricting part that restricts the magnetic flux of the main magnet passing through an end surface of the member along a third direction that is perpendicular to both a first direction in which the main magnet and the armature oppose each other, and a second direction corresponding to the relative moving direction between the magnetic field apparatus and the aLmature.
H01F 7/08 - Electromagnets; Actuators including electromagnets with armatures
H01F 1/12 - Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials
Provided is a semiconductor device including: a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; a first main terminal provided above the upper surface; a second main terminal provided below the lower surface; a control terminal configured to control whether or not to cause a current to flow between the first main terminal and the second main terminal; and a buffer region provided between the drift region and the lower surface and having a higher doping concentration than the drift region. In a C-V characteristic indicating a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal, a region where the power supply voltage is 500 V or more has a peak of the inter-terminal capacitance.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A cooler includes: a cooling wall including a first surface and a second surface; a first path extending in a first direction and having an inlet for a refrigerant; a second path extending in the first direction and having an outlet for the refrigerant; a cooling path causing the first path to communicate with the second path in a second direction intersecting the first direction; a partition spaced from the cooling wall in a third direction perpendicular to the first surface, separating the first and second paths from the cooling paths, and including a third surface constituting a part of a wall surface of the first path, the third surface including a first portion and a second portion differing from the first portion in position in the third direction. The first path includes a first gas retaining space defined by the first and second portions.
A semiconductor apparatus includes: a semiconductor module; a cooler including flow paths through which a refrigerant flows; a casing including a bottom surface; at least one first fixing member fixing the cooler to the bottom surface; and at least one second fixing member fixing the cooler to the bottom surface. The cooler includes: an outer surface directed to the bottom surface of the casing; an inner surface that is a part of wall surfaces of the flow paths on an opposite side to the outer surface; an outer wall to which the at least one first fixing member is connected; and an outer wall that is on an opposite side to the outer wall and to which the at least one second fixing member is connected. The semiconductor module is positioned between the bottom surface of the casing and the outer surface of the cooler, and is pressed by these two surfaces.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
A cooler includes a main body extending in the Y direction. The main body includes: (i) an outer wall including an outer surface on which a semiconductor module is to be arranged, and an inner surface; (ii) an inflow path extending in the Y direction, and having an end into which a refrigerant flows; (iii) an outflow path extending in the Y direction, and having an end from which the refrigerant flows out; and (iv) cooling flow paths having the inner surface as a part of a wall surface. The cooling flow paths are arrayed in the Y direction, extend in the X direction, and are positioned between the inflow and outflow paths and the outer wall in the Z direction. Each of the cooling flow paths causes the inflow path and the outflow path to communicate with each other in the X direction.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
An outer frame (outer wall) of a housing of a semiconductor device has a spacer portion that protrudes beyond a bottom surface of a cooling bottom plate in an opposite direction to a semiconductor chip. When the semiconductor device is placed on an arbitrary placement surface for example, the spacer portion produces a gap between a rear surface of a cooling device (that is, a bottom surface of the cooling bottom plate) and the placement surface. This means that the bottom surface of the cooling bottom plate does not directly touch the placement surface and is less likely to be damaged. Favorable sealing is maintained between pipes, which are attached to the cooling device of the semiconductor device, and an inlet and an outlet on the cooling bottom plate.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/10 - Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
83.
OVERCURRENT DETECTION CIRCUIT, DRIVE CONTROL DEVICE, AND POWER CONVERSION DEVICE
An overcurrent detection circuit including a detection unit for detecting whether a current flowing between main terminals of a main switching device used by a power conversion device is an overcurrent, and a switching unit for switching among thresholds used for determining the overcurrent in the detection unit according to in which phase of the power conversion device the main switching device is used, in which the detection unit includes a plurality of comparison units for comparing a parameter according to the current flowing between main terminals, and thresholds different from each other, and the switching unit is for switching a comparison unit to use for detection of the overcurrent among the plurality of comparison units.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 1/32 - Means for protecting converters other than by automatic disconnection
A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Provided is a semiconductor device including: a transistor portion provided in a semiconductor substrate; and a diode portion provided in the semiconductor substrate, in which an area ratio of the transistor portion to the diode portion on a front surface of the semiconductor substrate is larger than 3.1 and smaller than 4.7. Provided is a semiconductor module including: a semiconductor device including a transistor portion and a diode portion provided in a semiconductor substrate; an external connection terminal electrically connected to the semiconductor device; and a coupling portion for electrically connecting the semiconductor device and the external connection terminal. The coupling portion may be in plane contact with a front surface electrode of the semiconductor device at a predetermined junction surface. An area ratio of the transistor portion to the diode portion may be larger than 2.8 and smaller than 4.7.
A semiconductor apparatus a semiconductor module including a semiconductor device and a resin section covering the periphery of the semiconductor device, and a cooler arranged below the semiconductor device. The cooler includes a top plate that is attached to a lower surface of the resin section. The resin section has a protrusion protruding downward from an outer peripheral edge of the lower surface of the resin section. The protrusion includes a first straight section extending in a predetermined direction in a plan view of the semiconductor apparatus, and a first curved section having a curved shape convex inward the semiconductor module and being connected to the first straight section. The top plate includes a first notch that is engageable with the protrusion, and the resin section and the top plate are bonded to each other with an adhesive interposed therebetween.
A semiconductor device includes: a lower electrode; a first dielectric layer provided on the lower electrode; a first upper electrode provided on the first dielectric layer; a second dielectric layer provided on the first upper electrode; a second upper electrode provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer provided on the second upper electrode; and a third upper electrode provided on the third dielectric layer and electrically connected to the first upper electrode, wherein a first capacitor between the lower electrode and the first upper electrode, a second capacitor between the first upper electrode and the second upper electrode, and a third capacitor between the second upper electrode and the third upper electrode are connected in parallel with each other.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
This uninterruptible power supply device comprises uninterruptible power supply modules each with a power converter housing for accommodating a power converter. The uninterruptible power supply device further comprises a busbar member that is provided outside of the power converter housings of the uninterruptible power supply modules and used for inputting/outputting power to/from the uninterruptible power supply modules. The uninterruptible power supply device further comprises, between the uninterruptible power supply modules and the busbar member, module circuit breakers that electrically disconnect the uninterruptible power supply modules from the busbar member. The uninterruptible power supply device further comprises a bypass circuit unit, which has a switching circuit that switches between conduction and non-conduction, and which supplies AC power from an AC power supply for bypassing to a load without intermediation by the uninterruptible power supply modules.
H02J 9/06 - Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over
A silicon carbide semiconductor device has a termination region, which includes first to fourth semiconductor regions, one provided on the outer side of another. The second semiconductor region has first small regions that are provided in a region having an impurity concentration lower than that of the first semiconductor region, and have the same impurity concentration as first semiconductor region. The third semiconductor region has a lower impurity concentration than the first semiconductor region. The fourth semiconductor region has second small regions that have the same impurity concentration as the third semiconductor region. A width of the first semiconductor region is narrower than a width of the third semiconductor region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A cooling device including a rectangular top plate in a plan view having a front surface on which a semiconductor module is disposed and a rear surface having a sidewall connection region, a flow pass region, and an outer edge region. The flow pass region includes a cooling region and first and second communicating regions that sandwich the cooling region therebetween from a short-side direction of the top plate. The sidewall connection region surrounds an outer periphery of the flow pass region. The outer edge region is outside of the sidewall connection region and closer to an edge of the top plate than is the flow pass region. The cooling region has a first thickness, and the outer edge region has a second thickness that is greater than the first thickness.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
This semiconductor device comprises: a gate trench part provided on a semiconductor substrate; a first trench part provided on the semiconductor substrate and located adjacent to the gate trench part; an emitter region of a first electric conductivity type provided in contact with the gate trench part in a mesa part between the gate trench part and the first trench part; a contact region of a second electric conductivity type provided in contact with the first trench part in the mesa part; a metal layer provided over the semiconductor substrate; and a resistor of the first electric conductivity type provided in contact with the metal layer and the emitter region, said resistor having a lower doping concentration than that of the emitter region.
Provided is a semiconductor device provided with a gate trench portion, and a first trench portion adjacent to the gate trench portion, the semiconductor device comprising: a first conductive-type drift region provided in a semiconductor substrate; a second conductive-type base region provided above the drift region; a first conductive-type emitter region provided above the base region and having a higher doping concentration than the drift region; and a second conductive-type contact region provided above the base region and having a higher doping concentration than the base region. The contact region may have a first contact portion and a second contact portion provided extending from the first trench portion to below the lower end of the emitter region in a mesa portion between the gate trench portion and the first trench portion. The first contact portion may be provided extending from the first trench portion rather than the second contact portion in a trench arrangement direction.
Provided is a semiconductor module comprising: a first switching element provided on one of an upper arm and a lower arm; a second switching element provided on the other of the upper arm and the lower arm; a first diode element provided in parallel with the first switching element; a second diode element provided in parallel with the second switching element; a stacked substrate having two sides extending in a first direction and a second direction and of which the main surface is predetermined; and a gate external terminal and an auxiliary source external terminal provided on a negative side in the first direction relative to the upper arm and the lower arm and arranged in the second direction, wherein the first switching element, the second switching element, the first diode element, and the second diode element are provided on the stacked substrate, and at least one of the first switching element or the first diode element is provided facing at least one of the second switching element or the second diode element in the second direction.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H02M 7/48 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
94.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region; a second conductivity type region provided above the drift region; a plurality of trench portions extending in a predetermined extending direction; and an interlayer dielectric film provided above the semiconductor substrate and includes a first contact hole portion and second contact hole portion, in which the second conductivity type region and the emitter region are provided alternately in the extending direction, the first contact hole portion is provided alternately with the second contact hole portion in the extending direction, and a lower end of the first contact hole portion is provided at a different depth from a lower end of the second contact hole portion.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
To provide a manufacturing method of a semiconductor device including a semiconductor substrate, the manufacturing method of the semiconductor device including a sticking for sticking a protection tape to a first surface of the semiconductor substrate, a first grinding for supporting the protection tape and grinding a second surface of the semiconductor substrate that is a surface on the opposite side of the first surface, a protection tape cutting for supporting the second surface of the semiconductor substrate and flattening the protection tape, and a second grinding for supporting the protection tape and grinding the second surface of the semiconductor substrate. In the second grinding, in order to leave a convex part in an outer circumference of the semiconductor substrate, an inside of the convex part may be ground.
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
96.
SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND VEHICLE
A semiconductor module (1) comprises: a laminated substrate (2) having a first circuit board (22) disposed to a top surface of an insulation plate (20); a semiconductor element (3) disposed to a top surface of the first circuit board; a metal wiring board (4) including a first joint portion (40) joined to a top surface of the semiconductor element with a joining material (S) therebetween; and a sealing resin (5) sealing the laminated substrate, the semiconductor element, and the metal wiring board. The first joint portion includes a plate-shaped portion having a top surface and a bottom surface. The metal wiring board comprises: a first rising portion (43) rising upward from one end of the first joint portion; and a second rising portion (44) rising upward from another end of the first joint portion. The first rising portion constitutes a portion of a wiring path along which a main current flows. The second rising portion constitutes a non-wiring path along which the main current does not flow.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
A semiconductor device manufacturing method, including: a first treatment process for reducing an amount of oxygen and carbon adsorbed to a main surface of the conductive plate to 20 atomic % or less; a first checking process for checking whether the conductive plate has a temperature no higher than a reference temperature; a chip placement process for placing, responsive to the conductive plate having the temperature no higher than the reference temperature, a semiconductor chip on the main surface of the conductive plate via a sinter material; a first bonding process for applying heat and pressure to the sinter material according to a first condition that allows the organic substance to partially remain; a preparatory process for making preparations for further bonding the semiconductor chip; and a second bonding process for further applying heat and pressure to the sinter material according to a second condition that sinters the sinter material.
A semiconductor device includes: a plate-shaped terminal including one main surface and another main surface and having one end electrically connected to a semiconductor chip; a nut arranged on the one main surface side at another end of the terminal; a nut cover provided on the one main surface side at the other end of the terminal and configured to cover the nut; and a case configured to surround the semiconductor chip and integrate the terminal and the nut cover, wherein the nut cover includes a protruding portion protruding from a lower portion of the nut cover to the one end side of the terminal.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/08 - Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
H01R 4/30 - Clamped connections; Spring connections using a screw or nut clamping member
H01R 43/24 - Assembling by moulding on contact members
H01R 43/18 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for manufacturing bases or cases for contact members
A semiconductor resistance device includes a polysilicon resistance region; a first contact region in the resistance region, the first contact region having the same conductivity type as the resistance region and having a higher impurity concentration than the resistance region; a first wiring electrically connected to one end of the resistance region via a plurality of first vias; and a second wiring electrically connected to the other end of the resistance region via a plurality of second vias. At least one of the plurality of first vias and the plurality of second vias is in contact with the first contact region so as to form a low resistance contact structure, and at least another one of the plurality of first vias and the plurality of second vias forms a high resistance contact structure that has a contact resistance higher than a contact resistance of the low resistance contact structure.
H01C 7/06 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material including means to minimise changes in resistance with changes in temperature
H01C 7/04 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having negative temperature coefficient
H01C 7/02 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having positive temperature coefficient
A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
