A power converter includes a semiconductor module with a switching element, a DC terminal, and an AC terminal, and includes a capacitor module with a capacitor terminal coupled to the DC terminal of the semiconductor module. The power converter includes a cooling module. The cooling module has a first cooling surface provided to face the heat dissipation portion, and has a second cooling surface provided to face the DC terminal or the capacitor terminal. The cooling module has a third cooling surface extending in a direction intersecting each of the first cooling surface and the second cooling surface, the third cooling surface being configured to cool the capacitor module.
H02M 7/00 - Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
H02M 7/493 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; and an external connection terminal electrically connected to the semiconductor chip and including an inner-side conductor layer, an outer-side conductor layer provided at a circumference of the inner-side conductor layer, and an insulating layer interposed between the inner-side conductor layer and the outer-side conductor layer.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
A semiconductor device includes: a semiconductor base body of a first conductivity-type; a first well region of a second conductivity-type provided in the semiconductor base body; at least one second well region of the first conductivity-type implementing a part of a high-side circuit provided in the first well region; a buried layer of the second conductivity-type provided at a bottom of the first well region and having a higher impurity concentration than the first well region; a voltage blocking region of the second conductivity-type provided at a circumference of the first well region; and an extraction region of the first conductivity-type provided to have a greater depth than the second well region at least at a part of a circumference of the high-side circuit in the first well region so as to be opposed to the second well region.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
5.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device, including: preparing a semiconductor substrate; forming a first semiconductor layer at a first main surface of the semiconductor substrate; forming and etching an oxide film to form a trench mask; using the trench mask to form a plurality of trenches penetrating through the first semiconductor layer; forming a plurality of gate insulating films along the surface of the first semiconductor layer and bottoms and sidewalls of the plurality of trenches; forming a polycrystalline silicon layer on the plurality of gate insulating films; etching the polycrystalline silicon layer to form a plurality of gate electrodes; selectively forming a plurality of first semiconductor regions in the first semiconductor layer; forming a first electrode at the surface of the first semiconductor layer and on the plurality of first semiconductor regions; and forming a second electrode at a second main surface of the semiconductor substrate.
Provided is a semiconductor device comprising: a plurality of trench portions include a gate trench portion and a dummy trench portion; a first lower end region of a second conductivity type that is provided to be in contact with lower ends of two or more trench portions which include the gate trench portion; a well region of a second conductivity type that is arranged in a different location from the first lower end region in a top view, and a second lower end region of a second conductivity type that is provided between the first lower end region and the well region in a top view being separated from the first lower end region and the well region, and provided to be in contact with lower ends of one or more trench portions including the gate trench portion.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Provided is a semiconductor device in which a doping concentration peak of a buffer region has a local maximum at which a doping concentration shows a local maximum value, a lower tail in which the doping concentration monotonously decreases from the local maximum toward a lower surface, and an upper tail in which the doping concentration monotonously decreases from the local maximum toward an upper surface, and at least one of the doping concentration peaks of the buffer region is a gradual concentration peak in which a slope ratio obtained by dividing an absolute value of a slope of the upper tail by an absolute value of a slope of the lower tail is 0.1 or more and 3 or less.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
A method of manufacturing a semiconductor device comprising a transistor section and a diode section each having a drift region of a first conductivity-type inside a semiconductor substrate, and a base region of a second conductivity-type above the drift region. A particle beam is irradiated from an upper surface of the semiconductor substrate forming a lifetime control region including lifetime killers below the base region from at least a part of the transistor section to the diode section. A threshold value adjusting section is formed for adjusting a threshold value of the transistor section, including a thickened portion Wgi of a gate insulating film in a gate trench section adjacent to the base region, the thickened portion having a dielectric constant less than or equal to 0.9 times a remaining portion of the gate insulating film in the gate trench section.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A semiconductor module 1 includes an IGBT 31z configured to supply a motor 24 with power, a pre-driver 41z configured to drive the IGBT 31z, a protection unit 42z configured to execute first protection operation protecting the IGBT 31z and the pre-driver 41z from operation in an abnormal state, an IGBT 31db configured to adjust the magnitude of voltage input to the IGBT 31z, a pre-driver 41db configured to drive the IGBT 31db, and a protection unit 42db configured to execute second protection operation protecting the IGBT 31db from operation in an abnormal state, and the protection unit 42db executes the second protection operation when the IGBT 31db is operating in an abnormal state and otherwise does not execute the second protection operation regardless of whether or not the protection unit 42z is executing the first protection operation.
Provided is a semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a collector region of a second conductivity type provided on a back surface of the semiconductor substrate; a cathode region of the first conductivity type provided on the back surface of the semiconductor substrate and having a higher doping concentration than the drift region; a plurality of trench portions provided on a front surface of the semiconductor substrate; and a lifetime control portion provided in the semiconductor substrate and containing a lifetime killer, in which the lifetime control portion includes: a main region provided in a diode portion; and a decay region provided to extend from the main region in a direction parallel to the front surface of the semiconductor substrate and having a lifetime killer concentration that has decayed more than a lifetime killer concentration of the main region.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
A power converter includes a capacitor and a substrate on which a plurality of switching elements for power conversion are mounted. The power converter includes a cooler for cooling the plurality of switching elements and a housing that accommodates the capacitor, the substrate, and the cooler. The power converter includes a power connector exposed from the housing and an output connector exposed from the housing. The power converter includes a plurality of lines that include a plurality of power lines each electrically connected to the capacitor, given switching elements, and the power connector. The plurality of lines include a plurality of output lines each electrically connected to given switching elements and the output connector. At least one among the plurality of lines is a line that includes a conductive pattern formed on the substrate.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/32 - Means for protecting converters other than by automatic disconnection
Provided is a semiconductor device, comprising a semiconductor substrate and a first electrode provided above an upper surface of the semiconductor substrate. The semiconductor substrate has a first conductive type drift region. The semiconductor substrate has a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate. The semiconductor substrate has a second conductive type contact region with a higher impurity concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate. The semiconductor substrate has a trench contact that has a conductive material in an interior of a groove portion penetrating the contact region, the conductive material being in contact with at least a part of the semiconductor substrate, and connected to the first electrode.
The present invention prevents deformation of an insulating component that insulates a positive terminal and a negative terminal. This semiconductor module has a terminal structure (15a) that includes: a positive terminal (12a); a negative terminal (13a); and a first insulating component (14a) that is sandwiched between the positive terminal (12a) and the negative terminal (13a) and that includes a protruding part which protrudes from between the positive terminal (12a) and the negative terminal (13a). The semiconductor module further includes: a second insulating component (18) and a third insulating component (19) which sandwich the terminal structure (15a) vertically and cover the front surface and the rear surface of at least a portion of the protruding part; and a case integrally formed with the terminal structure (15a) which is sandwiched between the second insulating component (18) and the third insulating component (19).
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
14.
SEMICONDUCTOR DEVICE AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE
A semiconductor device (100) comprises a semiconductor substrate (10), an emitter electrode (52), and a polyimide protection film (150). The semiconductor substrate has: an active part (120) that has alternating transistor parts (70) and diode parts (80); and a plurality of trench parts (30, 40) that extend in the extension direction of the transistor parts and the diode parts. The emitter electrode is provided above a front surface of the semiconductor substrate, and the protection film is provided on a top surface of the emitter electrode. The diode parts have a lifetime control region (85) that includes a lifetime killer that has been irradiated from the front surface side of the semiconductor substrate. The active part has protected regions (151-1) at which the protection film is provided and unprotected regions (152-2) at which the protection film is not provided. The diode parts are in the unprotected regions, and the protected regions are at the transistor parts.
[Problem] An object of the present invention is to provide a semiconductor module capable of preventing a wire wiring from being broken because of a crack having occurred in sealing resin.
[Problem] An object of the present invention is to provide a semiconductor module capable of preventing a wire wiring from being broken because of a crack having occurred in sealing resin.
[Solution] A semiconductor module 1 includes semiconductor chips 14a to 14d, sealing resin 18 configured to seal the semiconductor chips 14a to 14d, a case 11 including a casting area 117u, first portions 111 and 112, and second portions 113 and 114, wire wirings 101a to 101j and 102a to 102i sealed in the sealing resin 18 while being located closer to the first portion 111 and connected to the semiconductor chips 14a to 14d, and recessed portions 131a, 131b, 132a, and 132b formed on the second portions 113 and 114 between a virtual surface VSu and the first portion 112.
Provided is a semiconductor device comprising a semiconductor substrate provided with a drift region of a first conductivity type, wherein the substrate includes: an active portion; and a trench portion provided in the active portion at an upper surface of the substrate, the active portion includes: a first region in which trench portions including the trench portion are arrayed at a first trench interval in an array direction; and a second region in which trench portions including the trench portion are arrayed at a second trench interval greater than the first trench interval in the array direction, the first region includes a first bottom region of a second conductivity type provided over bottoms of at least two trench portions of the trench portions, and the second region includes a second bottom region of the second conductivity type provided at a bottom of one trench portion of the trench portions.
The present invention prevents progress of peeling on an interface between a lead bonded to an electrode on a semiconductor element by a bonding material and a sealing material. A semiconductor module (2) includes: a circuit board (5) on which a semiconductor element (510) is mounted; a lead (7) that is bonded to an electrode on an upper surface of the semiconductor element by a bonding material; and a sealing material (9) that seals the semiconductor element and the lead. The lead has a plurality of recessed sections (720) on an upper surface (710) that is the opposite side from a lower surface facing the electrode, on a bonding section (701) bonded to the electrode, the recessed sections each having a polygonal shape in which a bottom surface in a plan view has a side extending in a direction that is not orthogonal to any of the sides of the bonding section. Each of the plurality of recessed sections has return parts (727) protruding from wall surfaces (721, 722, 723).
Provided is a semiconductor device comprising: a plurality of trench portions; a first lower end region of a second conductivity type that is provided to be in contact with lower ends of two or more trench portions which include the gate trench portion; a well region of the second conductivity type that is arranged in a different location from the first lower end region in a top view, and a second lower end region of the second conductivity type that is provided between the first lower end region and the well region in a top view being separated from the first lower end region and the well region, and provided to be in contact with lower ends of one or more trench portions including the gate trench portion.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
19.
SENSOR SYSTEM AND METHOD FOR MEASURING GAS-LIQUID RATIO
A sensor system according to the present invention measures the gas-liquid ratio of a two-phase fluid flowing through the interior of a pipe, the system comprising: a transmission unit that transmits a radio wave to the interior of the pipe; a reception unit that receives the radio wave from the interior of the pipe; a flow pattern acquisition unit that acquires a flow pattern in the interior of the pipe; and a control unit that calculates the gas-liquid ratio on the basis of the flow pattern and the radio wave intensity of the radio wave received by the reception unit.
G01N 22/00 - Investigating or analysing materials by the use of microwaves or radio waves, i.e. electromagnetic waves with a wavelength of one millimetre or more
Provided is a method for producing a vertical silicon carbide semiconductor device that comprises electrodes on both main surfaces of a semiconductor chip (30) in which an epitaxial layer (2) and a n-type low-concentration buffer layer (20) have been epitaxially grown on a silicon carbide substrate (1). A defect that has extended from the silicon carbide substrate (1) to the epitaxial layer (2) and a defect that has occurred in the epitaxial layer (2) during epitaxial growth are detected with a PL image of the n- type low-concentration buffer layer (20). A defect that has occurred in the epitaxial layer (2) during epitaxial growth is detected with a PL image of the epitaxial layer (2). A defect that has extended from the silicon carbide substrate (1) to the epitaxial layer (2) is detected from the difference in detection results. A semiconductor chip (30) which does not have a defect that has extended from the silicon carbide substrate (1) to the epitaxial layer (2) is selected.
An integrated circuit for a power supply circuit that generates an output voltage, and that includes: a transformer including primary and secondary coils, first and second transistors controlling a current of the primary coil, and a resonant circuit including the primary coil and a first capacitor. The integrated circuit controls the first and second transistors. The integrated circuit includes: a voltage generator circuit supplying a first current to a second capacitor, and to generate a first voltage at the second capacitor; a driving signal output circuit outputting a driving signal for driving the first and second transistors, based on the first voltage and a feedback voltage corresponding to the output voltage; and a control circuit controlling the voltage generator circuit such that, when the output voltage drops and a derivative of the feedback voltage at a time point is greater than a predetermined value, the first current increases and then decreases.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/00 - Conversion of dc power input into dc power output
22.
SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND VEHICLE
A semiconductor module includes: a stacked substrate; a semiconductor element arranged on an upper surface of the first circuit board; a metal wiring board including a first bonding portion bonded to an upper surface of the semiconductor element with a bonding material; and a sealing resin that seals the stacked substrate, the semiconductor element, and the metal wiring board. The first bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The metal wiring board has a first standing portion standing up from one end of the first bonding portion, and a second standing portion standing up from the other end of the first bonding portion. The first standing portion constitutes a part of a wiring path through which a main current flows. The second standing portion constitutes a non-wiring path through which the main current does not flow.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
In an example, use of a solder joint may include a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface of the joined body in contact with the solder joint layer. The Ni—P—Cu plating layer may contain Ni as a main component and may contain 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, and the Ni—P—Cu plating layer may have a microcrystalline layer at an interface with the solder joint layer.
B23K 35/26 - Selection of soldering or welding materials proper with the principal constituent melting at less than 400°C
B23K 1/00 - Soldering, e.g. brazing, or unsoldering
B23K 35/30 - Selection of soldering or welding materials proper with the principal constituent melting at less than 1550°C
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, i.e. electroless plating
C23C 18/32 - Coating with one of iron, cobalt or nickel; Coating with mixtures of phosphorus or boron with one of these metals
24.
GEOTHERMAL POWER GENERATION SYSTEM AND SILICA SCALE DEPOSITION CONTROL METHOD
Provided is a geothermal power generation system with which it is possible to control silica scale deposition. This geothermal power generation system comprises: a production well; a steam-water separator which separates a geothermal fluid obtained from the production well into steam and hot water; a turbine which rotates by means of the steam separated in the steam-water separator; a reinjection well which returns the geothermal fluid which has passed through the steam-water separator and/or the turbine; a pH measurement system which measures the pH of an extracted portion of the hot water separated in the steam-water separator, and a first thermometer which measures the temperature of the extracted portion of hot water; an injection device which injects an alkaline agent into the geothermal fluid; a second thermometer which measures the temperature of the geothermal fluid at a pH estimation point selected from among an injection part for the alkaline agent, an outlet of the steam-water separator, and a reinjection well inlet; and a control device which controls the injection of the alkaline agent by the injection device on the basis of the measurement results from the pH measurement system, the first thermometer, and the second thermometer.
A fuel cell power generator comprising a plurality of fuel cell units and a controller that controls the plurality of fuel cell units, wherein the plurality of fuel cell units include respective fuel cells connected to shared output lines and the controller increases or reduces the output power of each of the plurality of fuel cells while keeping an outward supply power through the output lines approximately constant.
Provided is a clock generating apparatus including a voltage control oscillator that outputs a clock corresponding to a control voltage which is input, a control voltage generator that generates the control voltage corresponding to a difference between a frequency of the clock and a target frequency, a starting voltage generator that generates a starting voltage which is supplied to the voltage control oscillator during a start period of the voltage control oscillator, and a starting circuit that sets the control voltage to the starting voltage during the start period after a start-up of the voltage control oscillator.
Provided is a semiconductor device which includes: a semiconductor substrate containing silicon carbide; a plurality of first gate trench portions arranged side by side in a first direction; a first mesa portion sandwiched between two of the first gate trench portions; and a mesa facing region not sandwiched between two of the first gate trench portions in the first direction and arranged to face the first mesa portion in a second direction different from the first direction, and in which a contact hole is not provided in an interlayer dielectric film above the first mesa portion, and a source region is provided to extend from the first mesa portion to the mesa facing region and is connected to an upper-surface electrode via the contact hole.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Provided is a manufacturing method of a semiconductor device, comprising: performing a zincate treatment on a first metal layer provided above a semiconductor substrate with a zincate solution; forming a nickel-plated layer above the first metal layer; and forming a gold-plated layer above the nickel-plated layer, wherein in the performing the zincate treatment, a flow rate of the zincate solution supplied to a bath for performing the zincate treatment is 16 L/min or more and 20 L/min or less.
Provided is a semiconductor device that includes one or more transistor portions and one or more diode portions provided at different positions in a top view, a semiconductor substrate provided with the one or more transistor portions and the one or more diode portions, an upper surface electrode arranged above the semiconductor substrate, and one or more first mark portions arranged upper than the upper surface electrode, each of the one or more first mark portions being arranged so as to overlap both one of the one or more transistor portions and one of the one or more diode portions in the top view, in which each of the one or more first mark portions has a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A semiconductor device is provided that includes a semiconductor substrate containing silicon carbide, and a control circuit unit including one or more control elements and in which the one or more control elements each include a control source region provided in the upper surface of the semiconductor substrate, a control drain region provided in the upper surface of the semiconductor substrate and being of a same conductivity type as the control source region, a control base region provided in contact with the control source region and being of a different conductivity type from the control source region, and a control gate trench section provided from the upper surface of the semiconductor substrate to an internal portion of the semiconductor substrate and being in contact with the control base region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A silicon carbide semiconductor device includes an active region, a first-conductivity-type region, and a termination region. The active region has first second-conductivity-type regions and first silicide films in trenches, second second-conductivity-type regions and a second silicide film between the trenches that are adjacent to one another, and a first electrode while the termination region has a third second-conductivity-type region. The active region includes ohmic regions, non-operating regions and Schottky regions, each of which has a stripe shape. Each ohmic region is a region where the first electrode is in contact with either the first silicide film or the second silicide film. Each non-operating region is a region where the first electrode is in contact with either the first or second second-conductivity-type regions. Each Schottky region is a region where the first electrode forms a Schottky barrier junction with the first-conductivity-type region.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A switching control circuit for a power supply circuit that includes a transformer including primary and secondary coils, and first and second transistors controlling a current flowing through the primary coil. The power supply circuit generates an output voltage at a target level. The switching control circuit controls switching of the first and second transistors. The switching control circuit includes: a drive signal output circuit configured to output drive signals according to a normal mode, when the output voltage is lower than a first level, and output the drive signals according to a burst mode, when the output voltage is higher than the first level; and a driver circuit configured to switch the first and second transistors in response to the drive signals. The drive signal output circuit reduces a first time period in the burst mode, in response to the output voltage rising above the first level.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/00 - Conversion of dc power input into dc power output
33.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor substrate of a first conductivity-type: an insulated gate electrode structure buried in a first trench provided in the semiconductor substrate; a base region of a second conductivity-type provided in the semiconductor substrate so as to be in contact with the first trench; a first main electrode region of the first conductivity-type provided at an upper part of the base region so as to be in contact with the first trench: a polysilicon film of the second conductivity-type having a higher impurity concentration than the base region and buried in a second trench provided in the semiconductor substrate so as to be in contact with the base region; and a second main electrode region provided on a bottom surface side of the semiconductor substrate.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
N+-type source regions, low-concentration regions, and p++-type contact regions are each selectively provided in surface regions of a semiconductor substrate, at a front surface thereof, and are in contact with a source electrode. The n+-type source regions and the low-concentration regions are in contact with a gate insulating film at sidewalls of a trench and are adjacent to channel portions of a p-type base region, in a depth direction. The p++-type contact regions are disposed apart from the trench. In surface regions of an epitaxial layer constituting the p-type base region, portions left free of the n+-type source regions and the p++-type contact regions configure the low-concentration regions of an n−-type or a p−-type. The low-concentration regions are disposed periodically along the trench, between the trench and the p++-type contact regions. By the described structure, short-circuit withstand capability may be increased without increasing the number of processes.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
35.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device with a vertical, the vertical element having drift region of a first conductivity type provided on a semiconductor substrate, a first injection portion provided below the drift region, and a second injection portion provided below the drift region and having a lower carrier injection efficiency than that of the first injection portion. The first injection portion is larger in area than the second injection portion on a back surface of the semiconductor substrate, and the vertical element has the first injection portion and the second injection portion provided alternately in a predetermined direction.
The present invention reduces uneven filling of encapsulant in a semiconductor module using a case with an integrated lid. A semiconductor module (2) includes: a case (210) covering a circuit board (4) mounted on a base (200), the case including sides (211) surrounding the perimeter of the circuit board and a lid (212) located above the circuit board; a plurality of conductor plates (6A-6D), each being electrically connected to a conductor pattern on the circuit board and extending out of the case through a slit (220) provided in the case; and encapsulants (701, 702) encapsulating the circuit board, wherein the case has partitions (214, 215) which are placed in the area enclosed by the lid, the sides, and the circuit board and which are placed between the plurality of conductor plates to insulate the plurality of conductor plates from one another, and the partitions have notched sections (216, 217) at positions that do not overlap with the plurality of conductor plates, thereby making the height of the portion that does not overlap with the plurality of conductor plates lower than the height of the portion that does overlap.
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
37.
pH ESTIMATION DEVICE AND pH ESTIMATION METHOD FOR SILICA-OVERSATURATED FLUID
In the present invention, the pH of a fluid is estimated without using a pH gauge. Provided is a pH estimation system 10 for a silica-oversaturated fluid, said system comprising: a first flow path L1 which is branched from a pipe 20, through which a silica-containing fluid flows, and extracts a portion of the fluid; a first measurement part 1 which is connected to the first flow path via an open/close valve B2; a retention section L2 which is connected to the first flow path; a second flow path L3 which is connected to the retention section and returns the fluid to the pipe; a second measurement part 2 which is connected to the second flow path via an open/close valve B3; and a calculation device 3 which is electrically connected to the first measurement part and the second measurement part. The first measurement part and the second measurement part comprise a fluid temperature measurement device and a silica concentration measurement device; and the calculation device stores a silica concentration reduction rate, a silica saturation concentration, and a temperature-pH relational expression and calculates the pH of the fluid on the basis of measurement results obtained at the first measurement part and the second measurement part and the relational expression.
An electrophotographic photoconductor including a sequentially-provided conductive substrate, an undercoat layer, and a photosensitive layer. Photosensitive layer is a negatively-charged stacked type including a charge generation layer and a charge transport layer. Undercoat layer contains a resin binder and a first filler, the first filler including a zinc oxide particle surface-treated with an N-acylated amino acid or an N-acylated amino acid salt, and the charge generation layer containing an adduct compound of titanyl phthalocyanine and butanediol.
G03G 5/14 - Inert intermediate or cover layers for charge- receiving layers
G03G 5/047 - Photoconductive layers characterised by having two or more layers or characterised by their composite structure characterised by the charge-generation layers or charge-transporting layers
G03G 5/06 - Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor characterised by the photoconductive material being organic
An object of the present disclosure is to provide a semiconductor module capable of reducing variation in drive characteristics of each of plural semiconductor switching elements. A semiconductor module includes IGBTs configured to supply power to a load and gate driver circuits in which drive targets are set in a one-to-one relationship to the IGBTs and in which according to a positional relationship to, for example, the IGBT as the drive target, a driving capability of the gate driver circuit to drive the IGBT is set.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/32 - Means for protecting converters other than by automatic disconnection
40.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
On a surface of a portion of a front electrode exposed in an opening of a passivation film, a Ni-deposited film having high solder wettability is provided apart from the sidewalls of the opening of the passivation film. Metal wiring is soldered to the Ni-deposited film. The solder layer is formed only on the Ni-deposited film and thus, the solder layer and the passivation film do not contact each other. The front electrode contains Al and an entire area of the surface of the front electrode excluding the portion where the Ni-deposited film is formed is covered by a surface oxide film that is constituted by an aluminum oxide film formed by intentionally oxidizing the surface of the front electrode. The surface oxide film intervenes between the front electrode, the passivation film, and a sealant, whereby the adhesive strength of the passivation film and the sealant is increased.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A semiconductor device includes an insulated circuit board having a semiconductor chip thereon, a W-phase output terminal electrically connected to the chip, a cooling device including a cooling top plate having a top surface on which the insulated circuit board is disposed, and a case including a frame portion on the cooling top plate and having an open storage area in which the insulated circuit board is stored, and a current detection unit for detecting an output current flowing through the output terminal. The output terminal extends from the unit storage portion to an outside the case and passes through the current detection unit. The current detection unit is embedded within the frame portion such that a shortest external dimension thereof is parallel to a first direction that is perpendicular to the top surface in the cooling area of the cooling top plate.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
H01F 17/04 - Fixed inductances of the signal type with magnetic core
H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
An integrated circuit includes: an amplifier circuit outputting a first voltage and a second voltage respectively in a first case and a second case, in which two input voltages of opposite polarities are applied to a pair of input terminals of a bridge circuit, the first and second voltages being based on a reference voltage and first and second amplified voltages, obtained by amplifying, by a predetermined gain, first and second output voltages outputted from a pair of output terminals of the bridge circuit; and a reference voltage output circuit setting the reference voltage to a first level and a second level respectively in the first and second cases. The first and second levels respectively correspond to a sum of, and a difference between, a predetermined voltage and another amplified voltage obtained by amplifying, by the predetermined gain, an offset voltage generated at the output terminals of the bridge circuit.
A semiconductor device comprising a semiconductor substrate having upper and lower surfaces and a hydrogen containing region containing hydrogen and helium is provided. The carrier concentration distribution of the hydrogen containing region has: a first local maximum point; a second local maximum point closest to the first local maximum point among local maximum points positioned between the first local maximum point and the upper surface; a first intermediate point of the local minimum between the first and second local maximum points; and a second intermediate point closest to the second local maximum point among local minimum points or flat points where the carrier concentration remains constant positioned between the second local maximum point and the upper surface. A highest point of a helium concentration peak is positioned between the first and second local maximum points. The carrier concentration is lower at the first intermediate point than the second intermediate point.
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
Provided is a semiconductor device comprising a gate trench portion and a first trench portion adjacent to the gate trench portion, the semiconductor device comprising: a drift region of a first conductivity type; a base region of a second conductivity type; an emitter region of the first conductivity type that is provided above the base region and has a higher doping concentration than that of the drift region; and a contact region of the second conductivity type that is provided above the base region and has a higher doping concentration than that of the base region. In a mesa portion between the gate trench portion and the first trench portion, the contact region may have a first contact portion and a second contact portion that are provided to extend from the first trench portion to below a lower end of the emitter region.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Provided is a semiconductor apparatus having a MOS gate structure, comprising: a semiconductor substrate; a first interlayer dielectric film provided above an upper surface of the semiconductor substrate and including a first opening; and a second interlayer dielectric film stacked on the first interlayer dielectric film and including a second opening overlapping the first opening in a top view, wherein a width of the first opening in a first direction is different from a width of the second opening in the first direction, at a boundary height between the first interlayer dielectric film and the second interlayer dielectric film.
Provided is a semiconductor module, including: a first switching device provided in one of an upper arm or a lower arm; a second switching device provided in another of the upper arm or the lower arm; a first diode device provided in parallel with the first switching device; a second diode device provided in parallel with the second switching device; a laminated substrate of which a main surface has two sides extending in a predetermined first direction and a predetermined second direction; and a gate external terminal and an auxiliary source external terminal provided farther toward a negative side of the first direction than the upper arm and the lower arm, and arranged in the second direction.
H02M 7/00 - Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
An edge termination structure portion has one or more guard rings of a second conductivity type that are provided between a well region and an end side of a semiconductor substrate, and are exposed to an upper surface of the semiconductor substrate, a first conductivity type region that is provided between a first guard ring that is closest to the well region, among the one or more guard rings, and the well region, and a first field plate that is provided above the upper surface of the semiconductor substrate, and is connected to the first guard ring, and the first field plate overlaps 90% or more of the first conductivity type region between the first guard ring and the well region.
A semiconductor device includes: a gate trench portion provided in a semiconductor substrate; a first trench portion provided in the semiconductor substrate and adjacent to the gate trench portion; an emitter region of a first conductivity type provided to be in contact with the gate trench portion in a mesa portion between the gate trench portion and the first trench portion; a contact region of a second conductivity type provided to be in contact with the first trench portion in the mesa portion; a metal layer provided above the semiconductor substrate; and a resistance portion of the first conductivity type provided to be in contact with the metal layer and the emitter region and having a lower doping concentration than that of the emitter region.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
The objective of the present invention is to provide a shielded conductor with an improved insulation property and an opening/closing device using the same. An aspect of the present invention is a shielded conductor (5) serving for electric field relaxation, characterized in that the surface of the shielded conductor is covered with a resin (10) containing a nano-filler. In addition, an opening/closing device (1) according to an aspect of the present invention is characterized by comprising: a hermetic container (2); an insulating spacer (3) fixed inside the hermetic container; high-pressure conductors (4) disposed on both sides of the center of the insulating spacer; and the shielded conductors (5) attached to the high-pressure conductors on both sides and having a diameter greater than that of the high-pressure conductor, the surface of the shielded conductors being covered with the resin (10) containing the nano-filler.
A gate insulating film has a multilayer structure including a SiO2 film, a LaAlO3 film, and an Al2O3 film that are sequentially stacked, relative permittivity of the gate insulating film being optimized by the LaAlO3 film. In forming the LaAlO3 film constituting the gate insulating film, a La2O3 film and an Al2O3 film are alternately deposited repeatedly using an ALD method. The La2O3 film is deposited first, whereby during a POA performed thereafter, a sub-oxide of the surface of the SiO2 film is removed by a cleaning effect of lanthanum atoms in the La2O3 film. A temperature of the POA is suitably set in a range from 700 degrees C. to less than 900 degrees C.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
51.
SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS
A manufacturing method of a semiconductor apparatus, including: preparing a wafer on which an adhesion layer is provided in an outer peripheral region of a front surface; applying a protective tape on the front surface of the wafer, wherein the protective tape is applied on the adhesion layer; cutting a front surface of the protective tape; and grinding a back surface of the wafer while holding the wafer by a grinding apparatus through the protective tape, is provided. In addition, a semiconductor apparatus, including: a wafer; a semiconductor device provided in a central region of a front surface of the wafer; and an adhesion layer of a polyimide film provided in an outer peripheral region surrounding the central region on the front surface of the wafer, is provided.
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
Provided is a semiconductor device including: a plurality of trench portions which are provided to positions below a base region from an upper surface of a semiconductor substrate and are arranged next to one another in a first direction on the upper surface of the semiconductor substrate; a first lower end region of a second conductivity type, which is arranged at a first depth position and is provided in contact with a lower end of two or more of the trench portions; and a second lower end region which is arranged at the first depth position and is arranged at a position not overlapping with the first lower end region, in which the second lower end region includes at least one of a region of a first conductivity type or a region of a second conductivity type which has a lower doping concentration than the first lower end region.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes an integrated circuit having a first resistor configuring a voltage divider circuit, a sensing resistor configured to measure a sheet resistance having a same attribute as that of the first resistor, a temperature detection circuit configured to detect a value of a first temperature, a storage circuit configured to store a table including first information for each of a plurality of values of the first temperatures, the first information corresponding to a sheet resistance of the first resistor obtained based on a result of measurement of the sensing resistor, and indicating a relationship between a second temperature and a divided voltage of the voltage divider circuit at the second temperature, and an arithmetic circuit configured to obtain the second temperature, based on the first information at the value of the first temperature detected by the temperature detection circuit and the divided voltage.
G01K 7/24 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit
G01K 7/42 - Circuits effecting compensation of thermal inertia; Circuits for predicting the stationary value of a temperature
H01L 21/66 - Testing or measuring during manufacture or treatment
54.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device including a semiconductor chip, an insulating circuit board having a circuit pattern formed on an insulating plate, a case including a frame part having an opening that is substantially rectangular in a plan view of the semiconductor device, inner wall surfaces of the frame part at the opening forming a storage part to store the insulating circuit board, and a printed circuit board which has a flat plate shape and which protrudes from one of the inner wall surfaces of the frame part toward the storage part. The semiconductor device further includes a sealing material filled in the storage part, to thereby seal the semiconductor chip and the printed circuit board. A front surface of the sealing material forms a sealing surface, and in a thickness direction of the semiconductor chip, the sealing surface is higher around the printed circuit board than around the semiconductor chip.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/057 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads being parallel to the base
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Provide is a laser welding method of a lamination member including a second base material provided on a first base material, the laser welding method including forming a first scanning route by scanning a laser from a first point of the lamination member to a second point different from the first point, the first point being predetermined, and forming a second scanning route, at least a portion of which is shared with the first scanning route, by scanning the laser from a third point of the lamination member to a fourth point different from the third point, the third point being predetermined, and melting the first base material and the second base material in a common region between the first scanning route and the second scanning route, in which a welding depth of the first base material is 0.2 mm or more and 0.7 mm or less.
A bonding tool for bonding two conductive plates in contact with each other by pressing the bonding tool against the two conductive plates while vibrating a bonding end portion thereof in a direction parallel to the conductive plates. The bonding end portion of the bonding tool includes a bonding base having an end surface, the end surface having a protrusion area that has two sides facing and parallel to each other in a first direction that is parallel to the end surface, a plurality of protrusions provided in the protrusion area of the end surface, and a suppression portion provided on the end surface along the two sides of the protrusion area. The bonding end portion is configured to vibrate in the first direction.
A solder material having a good thermal-cycle fatigue property and wettability. The solder material contains not less than 6.0% by mass and not more than 8.0% by mass Sb, not less than 3.0% by mass and not more than 5.0% by mass Ag, and the balance of Sn and incidental impurities. Also, a semiconductor device may include a joining layer between a semiconductor element and a substrate electrode or a lead frame, the joining layer being obtained by melting this solder material.
B23K 35/02 - Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
B23K 1/00 - Soldering, e.g. brazing, or unsoldering
B23K 1/20 - Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
B23K 35/26 - Selection of soldering or welding materials proper with the principal constituent melting at less than 400°C
C22C 13/02 - Alloys based on tin with antimony or bismuth as the next major constituent
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
58.
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
Provided is a semiconductor device including a semiconductor substrate; a transistor portion provided in the semiconductor substrate; a current sensing portion for detecting current flowing through the transistor portion; an emitter electrode set to an emitter potential of the transistor portion; a sense electrode electrically connected to the current sensing portion; and a Zener diode electrically connected between the emitter electrode and the sense electrode. Provided is a semiconductor device fabricating method including providing a transistor portion in a semiconductor substrate; providing a current sensing portion for detecting current flowing through the transistor portion; providing an emitter electrode set to an emitter potential of the transistor portion; providing a sense electrode electrically connected to the current sensing portion; and providing a Zener diode electrically connected between the emitter electrode and the sense electrode.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The present invention disperses heating caused by an energizing current in a semiconductor device comprising a plurality of semiconductor elements positioned side by side in a row. This semiconductor device (1) comprises: a plurality of semiconductor elements (11) positioned side by side in a row; a first terminal (21) and second terminals (22); a first conductor (31) electrically connected to the first terminal (21) and the plurality of semiconductor elements (11); and a second conductor (32) electrically connected to the plurality of semiconductor elements (11) and the second terminals (22). The first terminal (21) is positioned on one side in the alignment direction of the plurality of semiconductor elements (11) with respect to the plurality of semiconductor elements (11), the first conductor (31), and the second conductor (32), and the second terminals (22) are positioned on the other side. The second conductor (32) has two divided pieces (32a) in which both sides, in the width direction that crosses the alignment direction and the thickness direction of the second conductor (32), extend in the alignment direction with respect to the plurality of semiconductor elements (11), and are each electrically connected to the plurality of semiconductor elements (11).
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
A semiconductor device includes: a resin insulated substrate including a first rein insulating layer, a conductor base provided on one of main surfaces of the first resin insulating layer, and a conductor foil provided on another main surface of the first resin insulating layer; a power semiconductor element bonded to the conductor foil; a case surrounding an outer circumference of the resin insulated substrate; a sealing resin provided inside the case to seal the power semiconductor element; and a second resin insulating layer provided between the first resin insulating layer and the sealing resin and having a lower water-absorption rate than the sealing resin.
A semiconductor device includes a semiconductor chip having a main electrode on a front surface thereof, a wiring board having a front surface to which a rear surface of the semiconductor chip is bonded, a sealing member sealing the wiring board and the semiconductor chip, and an adhesive layer including at least two adhesive films that are laminated to each other. The adhesive layer is provided on surfaces of the wiring board and the semiconductor chip so that the sealing member seals the wiring board and the semiconductor chip via the adhesive layer. As a result, the sealing member is able to reliably seal the semiconductor chip and wiring board via the adhesive layer, thereby preventing an occurrence and extension of separation.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
63.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a transistor portion, in which the transistor portion has a drift region of a first conductivity type provided in a semiconductor substrate, a base region of a second conductivity type provided above the drift region, an accumulation region of the first conductivity type provided above the drift region, a plurality of trench portions provided to extend from a front surface of the semiconductor substrate to the drift region, and a trench bottom portion of the second conductivity type provided in bottom portions of the plurality of trench portions, and the accumulation region has a doping concentration with a half width of 0.3 μm or more.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A switching control circuit for a power factor correction circuit configured to generate an output voltage from an alternating current (AC) voltage, the power factor correction circuit including an inductor configured to receive a rectified voltage corresponding to the AC voltage, and a transistor configured to control an inductor current flowing through the inductor. The switching control circuit is configured to control switching of the transistor. The switching control circuit includes: a driving signal output circuit configured to, when a peak value of the inductor current in a half cycle of the AC voltage is smaller than and greater than a first predetermined value, output a driving signal to operate the power factor correction circuit in a critical mode and in a continuous mode, respectively; and a driver circuit configured to drive the transistor, in response to the driving signal.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/217 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
65.
SWITCHING CONTROL CIRCUIT AND POWER SUPPLY CIRCUIT
A switching control circuit for a power supply circuit that includes an inductor to which a voltage in accordance with an alternating current (AC) voltage is applied, and a transistor controlling an inductor current flowing through the inductor, the power supply circuit generating an output voltage from the AC voltage, the switching control circuit being configured to control switching of the transistor, the switching control circuit comprising: an ON signal output circuit that outputs an ON signal to turn on the transistor in response to the inductor current reaches a predetermined current, when a feedback voltage in accordance with the output voltage indicates that the output voltage is lower than a first level, and outputs the ON signal every first cycle when the feedback voltage indicates that the output voltage is higher than the first level; an OFF signal output circuit that outputs an OFF signal to turn off the transistor based on the feedback voltage; and a driver circuit that drives the transistor based on the ON signal and the OFF signal, wherein the first cycle is longer than a second cycle, which is a cycle of the ON signal when the output voltage is lower than the first level.
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
66.
SEMICONDUCTOR MODULE, POWER CONVERTER, AND POWER CONVERTER MANUFACTURING METHOD
A semiconductor module includes an insulated circuit substrate including a semiconductor chip, an insulated circuit substrate including a wiring board provided on a front surface thereof, the wiring board having the semiconductor chip bonded thereto, a heat dissipation base having a front surface and a rear surface opposite to each other. The front surface has a substrate region to which the insulated circuit substrate is bonded. The rear surface has a heat dissipation region positioned overlapping the substrate region in a plan view of the semiconductor module and a loop-shaped region surrounding the heat dissipation region. The semiconductor module further includes a solid heat dissipation member made of a phase change material and provided on the rear surface of the heat dissipation base in the heat dissipation region, and an elastic member provided on the rear surface of the heat dissipation base in the loop-shaped region.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A method of manufacturing a semiconductor device includes: forming a first trench from an upper surface side of a semiconductor substrate; burying the first trench with an insulated gate electrode structure; forming a base region at an upper part of the semiconductor substrate so as to be in contact with the first trench; forming a first main electrode region at an upper part of the base region so as to be in contact with the first trench; forming a second trench by removing a part of the first main electrode region; implanting first impurity ions entirely into a side wall surface of the second trench from a diagonally upper side; implanting second impurity ions into a bottom surface of the second trench to form a contact region at a bottom of the second trench; and forming a second main electrode region on a bottom surface side of the semiconductor substrate.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
69.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: an insulated gate electrode structure provided in a semiconductor substrate; a base region; a first main electrode region; a contact plug buried in a trench penetrating the first main electrode region to reach the base region with a barrier metal film interposed; an interlayer insulating film provided with a contact hole integrally connected to the trench; a contact region provided in contact with a bottom of the trench; and a second main electrode region, wherein an opening width at a lower end of the contact hole conforms to a width at an opening of the trench, an upper part of a side wall continued from the opening of the trench has a curved surface convex to an outside, and a lower part of the side wall continuously connected to the bottom of the trench has a curved surface convex to the outside.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
The present invention limits reduction of the cooling capacity. A cooling housing (40) includes, when viewed in a plan view: outside surfaces (40a, 40c) located on the long side; outside surfaces (40b, 40d) located on the short side; and an inlet (40h) that is formed in the outside surface (40b) near the outside surface (40c) and that is in communication with a flow path area (41) and through which a medium flows in longitudinally toward the flow path area (41). An inflow area (42) is formed in a flow path bottom surface (41e) near the inlet (40h). The inflow area (42) is concave and depressed lower than the flow path bottom surface (41e), and leads to the inlet (40h). The inflow area (42) includes a diffusion surface (42d) opposed to the inlet (40h).
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
According to the present invention, a front surface side of a semiconductor substrate (30) is provided with a source trench structure that comprises a gate trench (7), in which a gate electrode (9) is buried, and a source trench (11), in which a source electrode (13) is buried. A p-type base region (3) extends along the inner wall of the source trench (11) between the source trench (11) and an n- type drift region (2); and the bottom surface of the source trench (11) is surrounded by the p-type base region (3). An n-type current diffusion region (16) is provided so as to face the lower surface of a p-type base deep portion (4) of the p-type base region (3) in the depth direction (Z), the p-type base deep portion (4) extending along the bottom surface of the source trench (11). The n-type current diffusion region (16) has a function of lowering the breakdown voltage by making avalanche breakdown likely to occur in the vicinity of the bottom surface of the source trench (11) when an SiC-MOSFET is in an off state. Consequently, the present invention is capable of reducing the on-resistance.
A p++-type outer peripheral contact region is provided in an edge termination region and surrounds a periphery of an active region in a rectangular shape having rounded corners, in a plan view. The p++-type outer peripheral contact region faces a gate runner on a front surface of a semiconductor substrate via an insulating layer. In the active region, a p++-type region is provided facing a gate pad on the front surface of the semiconductor substrate via the insulating layer. The p++-type outer peripheral contact region and the p++-type region are provided apart from p++-type contact regions that form source contacts with a source electrode. The p++-type contact regions and contact holes in which the source contacts are formed are disposed in a uniform layout spanning an entire area of the active region so that an end side and a center side of the active region have the same layout.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
73.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; first semiconductor regions of the first conductivity type; trenches; gate insulating films; gate electrodes; first high-concentration regions of the second conductivity type provided at positions facing the trenches in a depth direction; second high-concentration regions of the second conductivity type, selectively provided between the trenches and in contact with the first semiconductor regions, each having an upper surface exposed at the surface of the second semiconductor layer and a lower surface partially in contact with upper surfaces of the first high-concentration regions; a first electrode; and a second electrode. The second high-concentration regions are disposed periodically in a longitudinal direction of the trenches.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
74.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a low-concentration semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a semiconductor layer of the second conductivity type in the active region and a semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the semiconductor layer, and the second semiconductor layer is not in contact with a surface of the semiconductor substrate.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A method of manufacturing a semiconductor module includes: placing, on a lower hot plate, an insulating wiring substrate having an electrically-conductive pattern formed on an insulating substrate; placing sintered materials on the electrically-conductive pattern; placing semiconductor chips on the sintered materials; placing a cushioning material over the semiconductor chips; placing an upper hot plate on the cushioning material; and sintering the sintered materials by pressurizing and heating the sintered materials via the cushioning material and the electronic components by the upper hot plate in a state where a space is provided between the upper hot plate and a part of the insulating substrate.
A method for manufacturing a semiconductor module includes arranging an insulating wiring board on a lower die, arranging sintered materials at a plurality of points on the insulating wiring board, arranging each semiconductor chip on the sintered materials, arranging each buffer material individually on the semiconductor chips, arranging, above the lower die, an upper die including protrusions at points corresponding to arrangement positions of the semiconductor chips so that the protrusions correspond to the semiconductor chips, and sintering by pressurizing and heating the sintered materials by the protrusions through the buffer materials and the semiconductor chips.
Provided is a semiconductor device including a buffer region of a first conductivity type, which is provided between a lower surface of a semiconductor substrate and a drift region, has three or more doping concentration peaks in a depth direction of the semiconductor substrate, and has a higher concentration than the drift region, in which the three or more doping concentration peaks include a deepest peak farthest from the lower surface of the semiconductor substrate and a second peak second closest to the lower surface of the semiconductor substrate, and a peak width of the second peak is 2 times or more of a peak width of the deepest peak in the depth direction.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A switching control circuit for a power supply circuit generating an output voltage from an AC voltage. The power supply circuit includes an inductor receiving a first rectified voltage corresponding to the AC voltage, and a transistor controlling an inductor current flowing through the inductor. The switching control circuit controls switching of the transistor, and comprises: an identification circuit identifying whether an effective value of the AC voltage is a first or second level; a first comparator circuit comparing the inductor current with a first current value and a second current value, respectively when the effective value is the first level and the second level; and a driver circuit driving the transistor based on the inductor current and the output voltage. The driver circuit turns off the transistor in response to the inductor current exceeding the first current value or the second current value as a result of comparison.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
79.
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
To provide a manufacturing method of a semiconductor device including forming a lifetime control region from the side of a front surface of a semiconductor substrate, ion-implanting Ti into a bottom surface of a contact hole provided so as to penetrate through an interlayer dielectric film arranged on the front surface of the semiconductor substrate, and forming a Ti silicide layer at the bottom surface of the contact hole with anneal.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
A manufacturing method of a silicon carbide semiconductor device includes: epitaxially growing a drift layer of a first conductivity-type on a silicon carbide substrate of the first conductivity-type; forming a base region of a second conductivity-type on the drift layer; forming a main region of the first conductivity-type on the drift layer so as to be in contact with the base region; forming a gate insulating film so as to be in contact with the base region and the main region; forming a gate electrode so as to be in contact with the base region and the main region with the gate insulating film interposed; and forming a lifetime killer region at a depth covering a bottom surface of the drift layer by irradiating the top surface side of the drift layer with a lifetime killer after epitaxially growing the drift layer and before forming the gate insulating film.
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
The present invention suppresses the occurrence of a deviated flow distribution in a cooler and the increase in pressure loss. A cooler (10) comprises, inside a container (14): a first flow path (14e) disposed parallel with a first side wall (14a) and communicating with an introduction port (11); a second flow path (14f) disposed parallel with a second side wall (14b) and communicating with a discharge port (12); a third flow path (14g) communicating with the first flow path (14e) and the second flow path (14f); a first flow rate adjustment unit (15) disposed between the first flow path (14e) and the third flow path (14g); and a second flow rate adjustment unit (16) disposed between the second flow path (14f) and the third flow path (14g). The first flow rate adjustment unit (15) includes a first region (15a) having a first opening ratio and a second region (15b) having a second opening ratio smaller than the first opening ratio. The second flow rate adjustment unit (16) includes a third region (16a) having a third opening ratio and a fourth region (16b) having a fourth opening ratio greater than the third opening ratio.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
F28F 3/00 - Plate-like or laminated elements; Assemblies of plate-like or laminated elements
F28F 9/22 - Arrangements for directing heat-exchange media into successive compartments, e.g. arrangements of guide plates
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
A method for manufacturing a semiconductor module can prevent performance and reliability degradation of a semiconductor module. The method for manufacturing a semiconductor module includes: arranging an insulating wiring board on a low die; arranging a sintering material at plural locations on the insulating wiring board and arranging a semiconductor chip on each of the plural sintering materials; arranging a structure above protruding portions of the sintering materials protruding from a periphery of each of the plural semiconductor chips; and sintering by pressurizing and heating the plural sintering materials by an upper die through the structure at the protruding portions and through the semiconductor chips at contacting portions in contact with lower surfaces of the semiconductor chips.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
83.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
An AlSi electrode containing an aluminum alloy that contains silicon is sputtered on a surface of a semiconductor substrate that contains silicon carbide. Si nodules having a dendrite structure precipitate in AlSi electrode. At least some of the Si nodules have a dendrite structure, and the rest of the Si nodules have a prismatic structure. A height of the Si nodules having either dendrite structures or prismatic structures in the AlSi electrode in a thickness direction of the AlSi electrode is not more than 2 μm. A height of the Si nodules having the dendrite structures in the AlSi electrode, preferably, may be 1 μm or less. A solid solubility of silicon in the AlSi electrode is in a range of 0.3 wt % to 1.59 wt %. A sputtering temperature of the AlSi electrode is in a range of 430 degrees C. to 577 degrees C.
A unit cell (16) is a section between the centers of adjacent source trenches (11), includes two or more gate trenches (7) and one source trench (11), and has four or more channels formed therein. The two or more gate trenches (7) and the one source trench (11) are arranged repeating in an alternating manner in a direction parallel to the obverse surface of a semiconductor substrate (30). The total number of gate trenches (7) is greater than the total number of source trenches (11). The total area of the gate trenches (7) is greater than the total area of the source trenches (11). The width (w1) of the gate trenches (7) is equal to or less than the width (w2) of the source trenches (11). The depth (d2) of the source trenches (11) is equal to or greater than the depth (d1) of the gate trenches (7). A p-type base depth portion (4) of the bottom surfaces of the source trenches (11) relaxes an electric field in the vicinity of the bottom surfaces of the gate trenches (7). As a result, it is possible to reduce on-resistance.
A silicon carbide semiconductor device has a first semiconductor region of a first conductivity type, provided in a semiconductor substrate, spanning an active region and a termination region. A second semiconductor region of a second conductivity type is provided between a first main surface and the first semiconductor region, in the active region. A device structure having a first pn junction is provided between the first and second semiconductor regions. An outer peripheral portion of the active region is provided between the first main surface and the first semiconductor region in the active region, and constitutes a second-conductivity-type outer peripheral region that surrounds a periphery of the device structure and forms a second pn junction with the first semiconductor region. A first protective film is provided on the first main surface. The first protective film blocks light generated by a forward current passing through the first and second pn junctions.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Provided is a semiconductor device including a plurality of mesa portions which are arranged one by one between two of trench portions adjacent to each other in a second direction in a semiconductor substrate. The plurality of mesa portions includes a floating mesa portion which is insulated from an emitter electrode, and an emitter-connected mesa portion which is arranged adjacent to the floating mesa portion in the second direction and is connected to the emitter electrode. At least one of the floating mesa portion or the emitter-connected mesa portion is provided in a portion provided at a position not overlapping the well region in a top view to connect two of the trench portions sandwiching the mesa portion, and has a separation portion which separates the well region from at least a part of the mesa portion.
A power conversion apparatus includes a board including a device for power conversion mounted on the board; a connector fixed to the board and configured to electrically connect the board to an external side; a top plate formed of a metal plate and arranged to cover the board; and a bottom plate formed of a metal plate and arranged to face the top plate. The bottom plate includes a bottom-plate folded part that is arranged on an end part of the bottom plate on which the connector is arranged, and is folded to contact the connector whereby preventing movement of the connector.
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
A semiconductor device, including a semiconductor substrate having a transistor portion and a diode portion, a drift region of a first conductivity type provided in the semiconductor substrate, a first electrode provided on one main surface side of the semiconductor substrate, and a second electrode provided on another main surface side of the semiconductor substrate, is provided. The diode portion includes a high concentration region and a crystalline defect region. The high concentration region has a higher doping concentration than the drift region and includes hydrogen. The doping concentration of the high concentration region at a peak position in a depth direction of the semiconductor substrate is equal to or less than 1.0×1015/cm3. The crystalline defect region is provided on the one main surface side of the semiconductor substrate relative to the peak position, has a higher crystalline defect density than the drift region, and includes hydrogen.
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 μm. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/263 - Bombardment with wave or particle radiation with high-energy radiation
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
Provided are a semiconductor module and a method for manufacturing the semiconductor module that make it possible to prevent voids from occurring by means of a joining layer formed of solder. The semiconductor module comprises a laminated substrate (5) on which is mounted a semiconductor element (1) that has a Ni film formed on a rear surface thereof, the rear surface of the semiconductor element (1) being joined to the laminated substrate (5) by solder that has a composition that includes more than 6 mass% but no more than 8.5 mass% of Sb, 2–4.5 mass% of Ag, 1.25–2.0 mass% of Cu, and a remainder made up of Sn and inevitable impurities.
H01L 21/52 - Mounting semiconductor bodies in containers
B23K 35/26 - Selection of soldering or welding materials proper with the principal constituent melting at less than 400°C
C22C 13/02 - Alloys based on tin with antimony or bismuth as the next major constituent
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
A semiconductor device includes: an isolation circuit board; a semiconductor chip provided on one main surface of the isolation circuit board; a first external terminal having a main surface and including a first snubber connecting portion rising from the main surface of the first external terminal, the first external terminal being electrically connected to the semiconductor chip; a second external terminal placed adjacent to the first external terminal, having a main surface facing the same direction as the main surface of the first external terminal, and including a second snubber connecting portion rising from the main surface of the second external terminal, the second external terminal being electrically connected to the semiconductor chip; and a capacitor having one end connected to the first snubber connecting portion and the other end connected to the second snubber connecting portion
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
An integrated circuit for a power supply circuit that includes a detection resistor. The integrated circuit includes: a first pad; a first terminal coupled to the detection resistor, the first terminal being electrically connected to the first pad in a first case, and being electrically separated from the first pad in a second case; a first temperature detection circuit having a temperature detection element, and being configured to detect a first temperature based on a voltage of the temperature detection element; a second temperature detection circuit configured to detect a second temperature of the integrated circuit, based on a first voltage corresponding to a resistance value of the detection resistor, received through the first pad in the first case; and a circuit configured to operate based on results of detection of the second and first temperature detection circuits, respectively in the first case and in the second case.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
A semiconductor module includes: first and second switching devices coupled in series; a casing housing the first and second switching devices, and having first to fourth edges respectively on first to forth edge sides thereof; positive and negative terminals provided on the first edge side of the casing; an output terminal provided on the second edge side of the casing; a first control terminal and a first sense terminal for the first switching device, and a second control terminal and a second sense terminal for the second switching device, all provided on the third edge side of the casing; first and second conductive patterns respectively coupled to the positive terminal and the output terminal, and on which the first and second switching device are respectively arranged; and a third conductive pattern coupled to the negative terminal and the second switching device, on a side corresponding to the fourth edge side.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A silicon carbide semiconductor device has an n-type silicon carbide semiconductor substrate, an n-type first semiconductor layer, n-type first JFET regions, a p-type second semiconductor layer, n-type first semiconductor regions, and trenches. The first semiconductor layer has an impurity concentration lower than that of the substrate. The first JFET regions are provided in a surface layer of the first semiconductor layer and have an effective donor concentration higher than that of the first semiconductor. The p-type second semiconductor layer is provided at a surface of the first semiconductor layer. The n-type first semiconductor regions are selectively provided in a surface layer of the second semiconductor layer. The trenches penetrate through the first semiconductor regions, the second semiconductor layer, and the first JFET regions. The first JFET regions are doped with an acceptor that is aluminum and a donor that is nitrogen or phosphorus.
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Provided is a manufacturing method of a semiconductor apparatus including: detecting a position by detecting positional deviation of the upper surface mark and the lower surface mark, by acquiring an upper surface image obtained by observing the upper surface mark from above the upper surface of the semiconductor substrate and a lower surface image obtained by observing the lower surface mark through the semiconductor substrate from above the upper surface of the semiconductor substrate; and forming an element by forming a semiconductor element in the semiconductor substrate, where in a top view in which the upper surface mark and the lower surface mark are projected onto a plane parallel to the upper surface, one of the upper surface mark and the lower surface mark is larger than an other, and the one entirely covers the other.
A semiconductor device includes a main circuit and a control circuit. The main circuit includes a plurality of series circuits that are connected in parallel to one another. Each series circuit includes a high-side switching element and a low-side switching element that are connected in series. The control circuit includes first to third input terminals through which a serial drive signal serving as a driving signal of each high-side switching element and each low-side switching element is inputted, a first clock signal, and a second clock signal are respectively inputted, and a plurality of output terminals. The control circuit holds the serial drive signal based on the first clock signal, and based on the second clock signal outputs, to each high-side switching element and each low-side switching element, parallel signals generated from the serial drive signal.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 7/5387 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor module includes at least, a conductive pattern on the insulating substrate; a first semiconductor element on the conductive pattern, a second semiconductor element on the conductive pattern, a first power collecting portion connected to a first output electrode of the first semiconductor element with a first line; and a second power collecting portion connected to a second output electrode of the second semiconductor element with a second line. Each of the first and second semiconductor elements includes both a switching element and a diode. The conductive pattern is provided between the first power collecting portion and the second power collecting portion. A current path length from a first output electrode of the first semiconductor element to the first power collecting portion and a current path length from a second output electrode of the second semiconductor element to the second power collecting portion are equal to each other.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/528 - Layout of the interconnection structure
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Provided is a semiconductor device including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region arranged sandwiching the active portion in a top view, provided on the semiconductor substrate; an emitter electrode arranged above the active portion; and a pad arranged above the first well region, away from the emitter electrode, wherein the emitter electrode is provided above the second well region. The provided semiconductor device further includes a peripheral well region arranged enclosing the active portion in a top view, wherein the first well region and the second well region may protrude to the center side of the active portion rather than the peripheral well region.
A manufacturing method of a semiconductor apparatus including: setting, depending on a distribution of the carrier concentrations that the buffer region should have, a dose amount of hydrogen ions to be implanted into a plurality of depth positions corresponding to the plurality of concentration peaks; and implanting, depending on the dose amount that is set in the setting, the hydrogen ions into the semiconductor substrate is provided. In the setting, among the plurality of concentration peaks, the dose amount of the hydrogen ions for a deepest peak farthest from the lower surface of the semiconductor substrate is set depending on a carbon concentration of the semiconductor substrate, and the dose amount for at least one of the concentration peaks other than the deepest peak is set regardless of the carbon concentration of the semiconductor substrate.
The generated amount of silica scale under complicated conditions is accurately predicted. A method for predicting a generated amount of silica scale includes: a step of acquiring a temperature at a prediction portion at which the adherence of silica scale needs to be predicted, Ts (K), and/or time until fluid containing silicic acid reaches the prediction portion, ts (min), and a step of calculating the amount of silica adhered at the prediction portion based on the predictive equation of the saturation concentration of silica depending on the temperature and/or the predictive curve of the concentration of silica dissolved depending on the time, wherein the predictive equation of the saturation concentration of silica and the predictive curve of the concentration of silica dissolved are obtained based on k1, k2, kB, and ka in a three-step precipitation equilibrium reaction model represented by the following
The generated amount of silica scale under complicated conditions is accurately predicted. A method for predicting a generated amount of silica scale includes: a step of acquiring a temperature at a prediction portion at which the adherence of silica scale needs to be predicted, Ts (K), and/or time until fluid containing silicic acid reaches the prediction portion, ts (min), and a step of calculating the amount of silica adhered at the prediction portion based on the predictive equation of the saturation concentration of silica depending on the temperature and/or the predictive curve of the concentration of silica dissolved depending on the time, wherein the predictive equation of the saturation concentration of silica and the predictive curve of the concentration of silica dissolved are obtained based on k1, k2, kB, and ka in a three-step precipitation equilibrium reaction model represented by the following
G01N 17/00 - Investigating resistance of materials to the weather, to corrosion or to light
G16C 60/00 - Computational materials science, i.e. ICT specially adapted for investigating the physical or chemical properties of materials or phenomena associated with their design, synthesis, processing, characterisation or utilisation
