Provided is a semiconductor device comprising a semiconductor substrate provided with a drift region of a first conductivity type, wherein the substrate includes: an active portion; and a trench portion provided in the active portion at an upper surface of the substrate, the active portion includes: a first region in which trench portions including the trench portion are arrayed at a first trench interval in an array direction; and a second region in which trench portions including the trench portion are arrayed at a second trench interval greater than the first trench interval in the array direction, the first region includes a first bottom region of a second conductivity type provided over bottoms of at least two trench portions of the trench portions, and the second region includes a second bottom region of the second conductivity type provided at a bottom of one trench portion of the trench portions.
[Problem] An object of the present invention is to provide a semiconductor module capable of preventing a wire wiring from being broken because of a crack having occurred in sealing resin.
[Problem] An object of the present invention is to provide a semiconductor module capable of preventing a wire wiring from being broken because of a crack having occurred in sealing resin.
[Solution] A semiconductor module 1 includes semiconductor chips 14a to 14d, sealing resin 18 configured to seal the semiconductor chips 14a to 14d, a case 11 including a casting area 117u, first portions 111 and 112, and second portions 113 and 114, wire wirings 101a to 101j and 102a to 102i sealed in the sealing resin 18 while being located closer to the first portion 111 and connected to the semiconductor chips 14a to 14d, and recessed portions 131a, 131b, 132a, and 132b formed on the second portions 113 and 114 between a virtual surface VSu and the first portion 112.
Provided is a semiconductor device comprising: a plurality of trench portions; a first lower end region of a second conductivity type that is provided to be in contact with lower ends of two or more trench portions which include the gate trench portion; a well region of the second conductivity type that is arranged in a different location from the first lower end region in a top view, and a second lower end region of the second conductivity type that is provided between the first lower end region and the well region in a top view being separated from the first lower end region and the well region, and provided to be in contact with lower ends of one or more trench portions including the gate trench portion.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
4.
SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND VEHICLE
A semiconductor module includes: a stacked substrate; a semiconductor element arranged on an upper surface of the first circuit board; a metal wiring board including a first bonding portion bonded to an upper surface of the semiconductor element with a bonding material; and a sealing resin that seals the stacked substrate, the semiconductor element, and the metal wiring board. The first bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The metal wiring board has a first standing portion standing up from one end of the first bonding portion, and a second standing portion standing up from the other end of the first bonding portion. The first standing portion constitutes a part of a wiring path through which a main current flows. The second standing portion constitutes a non-wiring path through which the main current does not flow.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
An integrated circuit for a power supply circuit that generates an output voltage, and that includes: a transformer including primary and secondary coils, first and second transistors controlling a current of the primary coil, and a resonant circuit including the primary coil and a first capacitor. The integrated circuit controls the first and second transistors. The integrated circuit includes: a voltage generator circuit supplying a first current to a second capacitor, and to generate a first voltage at the second capacitor; a driving signal output circuit outputting a driving signal for driving the first and second transistors, based on the first voltage and a feedback voltage corresponding to the output voltage; and a control circuit controlling the voltage generator circuit such that, when the output voltage drops and a derivative of the feedback voltage at a time point is greater than a predetermined value, the first current increases and then decreases.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/00 - Conversion of dc power input into dc power output
In an example, use of a solder joint may include a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface of the joined body in contact with the solder joint layer. The Ni—P—Cu plating layer may contain Ni as a main component and may contain 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, and the Ni—P—Cu plating layer may have a microcrystalline layer at an interface with the solder joint layer.
B23K 35/26 - Selection of soldering or welding materials proper with the principal constituent melting at less than 400°C
B23K 1/00 - Soldering, e.g. brazing, or unsoldering
B23K 35/30 - Selection of soldering or welding materials proper with the principal constituent melting at less than 1550°C
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, i.e. electroless plating
C23C 18/32 - Coating with one of iron, cobalt or nickel; Coating with mixtures of phosphorus or boron with one of these metals
Provided is a clock generating apparatus including a voltage control oscillator that outputs a clock corresponding to a control voltage which is input, a control voltage generator that generates the control voltage corresponding to a difference between a frequency of the clock and a target frequency, a starting voltage generator that generates a starting voltage which is supplied to the voltage control oscillator during a start period of the voltage control oscillator, and a starting circuit that sets the control voltage to the starting voltage during the start period after a start-up of the voltage control oscillator.
Provided is a semiconductor device which includes: a semiconductor substrate containing silicon carbide; a plurality of first gate trench portions arranged side by side in a first direction; a first mesa portion sandwiched between two of the first gate trench portions; and a mesa facing region not sandwiched between two of the first gate trench portions in the first direction and arranged to face the first mesa portion in a second direction different from the first direction, and in which a contact hole is not provided in an interlayer dielectric film above the first mesa portion, and a source region is provided to extend from the first mesa portion to the mesa facing region and is connected to an upper-surface electrode via the contact hole.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Provided is a manufacturing method of a semiconductor device, comprising: performing a zincate treatment on a first metal layer provided above a semiconductor substrate with a zincate solution; forming a nickel-plated layer above the first metal layer; and forming a gold-plated layer above the nickel-plated layer, wherein in the performing the zincate treatment, a flow rate of the zincate solution supplied to a bath for performing the zincate treatment is 16 L/min or more and 20 L/min or less.
Provided is a semiconductor device that includes one or more transistor portions and one or more diode portions provided at different positions in a top view, a semiconductor substrate provided with the one or more transistor portions and the one or more diode portions, an upper surface electrode arranged above the semiconductor substrate, and one or more first mark portions arranged upper than the upper surface electrode, each of the one or more first mark portions being arranged so as to overlap both one of the one or more transistor portions and one of the one or more diode portions in the top view, in which each of the one or more first mark portions has a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A semiconductor device is provided that includes a semiconductor substrate containing silicon carbide, and a control circuit unit including one or more control elements and in which the one or more control elements each include a control source region provided in the upper surface of the semiconductor substrate, a control drain region provided in the upper surface of the semiconductor substrate and being of a same conductivity type as the control source region, a control base region provided in contact with the control source region and being of a different conductivity type from the control source region, and a control gate trench section provided from the upper surface of the semiconductor substrate to an internal portion of the semiconductor substrate and being in contact with the control base region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A silicon carbide semiconductor device includes an active region, a first-conductivity-type region, and a termination region. The active region has first second-conductivity-type regions and first silicide films in trenches, second second-conductivity-type regions and a second silicide film between the trenches that are adjacent to one another, and a first electrode while the termination region has a third second-conductivity-type region. The active region includes ohmic regions, non-operating regions and Schottky regions, each of which has a stripe shape. Each ohmic region is a region where the first electrode is in contact with either the first silicide film or the second silicide film. Each non-operating region is a region where the first electrode is in contact with either the first or second second-conductivity-type regions. Each Schottky region is a region where the first electrode forms a Schottky barrier junction with the first-conductivity-type region.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A switching control circuit for a power supply circuit that includes a transformer including primary and secondary coils, and first and second transistors controlling a current flowing through the primary coil. The power supply circuit generates an output voltage at a target level. The switching control circuit controls switching of the first and second transistors. The switching control circuit includes: a drive signal output circuit configured to output drive signals according to a normal mode, when the output voltage is lower than a first level, and output the drive signals according to a burst mode, when the output voltage is higher than the first level; and a driver circuit configured to switch the first and second transistors in response to the drive signals. The drive signal output circuit reduces a first time period in the burst mode, in response to the output voltage rising above the first level.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/00 - Conversion of dc power input into dc power output
14.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor substrate of a first conductivity-type: an insulated gate electrode structure buried in a first trench provided in the semiconductor substrate; a base region of a second conductivity-type provided in the semiconductor substrate so as to be in contact with the first trench; a first main electrode region of the first conductivity-type provided at an upper part of the base region so as to be in contact with the first trench: a polysilicon film of the second conductivity-type having a higher impurity concentration than the base region and buried in a second trench provided in the semiconductor substrate so as to be in contact with the base region; and a second main electrode region provided on a bottom surface side of the semiconductor substrate.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
N+-type source regions, low-concentration regions, and p++-type contact regions are each selectively provided in surface regions of a semiconductor substrate, at a front surface thereof, and are in contact with a source electrode. The n+-type source regions and the low-concentration regions are in contact with a gate insulating film at sidewalls of a trench and are adjacent to channel portions of a p-type base region, in a depth direction. The p++-type contact regions are disposed apart from the trench. In surface regions of an epitaxial layer constituting the p-type base region, portions left free of the n+-type source regions and the p++-type contact regions configure the low-concentration regions of an n−-type or a p−-type. The low-concentration regions are disposed periodically along the trench, between the trench and the p++-type contact regions. By the described structure, short-circuit withstand capability may be increased without increasing the number of processes.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
16.
ELECTROPHOTOGRAPHIC PHOTOCONDUCTOR, METHOD OF MANUFACTURING THE SAME, AND ELECTROPHOTOGRAPHIC APPARATUS
An electrophotographic photoconductor including a sequentially-provided conductive substrate, an undercoat layer, and a photosensitive layer. Photosensitive layer is a negatively-charged stacked type including a charge generation layer and a charge transport layer. Undercoat layer contains a resin binder and a first filler, the first filler including a zinc oxide particle surface-treated with an N-acylated amino acid or an N-acylated amino acid salt, and the charge generation layer containing an adduct compound of titanyl phthalocyanine and butanediol.
G03G 5/14 - Inert intermediate or cover layers for charge- receiving layers
G03G 5/047 - Photoconductive layers characterised by having two or more layers or characterised by their composite structure characterised by the charge-generation layers or charge-transporting layers
G03G 5/06 - Photoconductive layers; Charge-generation layers or charge-transporting layers; Additives therefor; Binders therefor characterised by the photoconductive material being organic
An object of the present disclosure is to provide a semiconductor module capable of reducing variation in drive characteristics of each of plural semiconductor switching elements. A semiconductor module includes IGBTs configured to supply power to a load and gate driver circuits in which drive targets are set in a one-to-one relationship to the IGBTs and in which according to a positional relationship to, for example, the IGBT as the drive target, a driving capability of the gate driver circuit to drive the IGBT is set.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/32 - Means for protecting converters other than by automatic disconnection
18.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
On a surface of a portion of a front electrode exposed in an opening of a passivation film, a Ni-deposited film having high solder wettability is provided apart from the sidewalls of the opening of the passivation film. Metal wiring is soldered to the Ni-deposited film. The solder layer is formed only on the Ni-deposited film and thus, the solder layer and the passivation film do not contact each other. The front electrode contains Al and an entire area of the surface of the front electrode excluding the portion where the Ni-deposited film is formed is covered by a surface oxide film that is constituted by an aluminum oxide film formed by intentionally oxidizing the surface of the front electrode. The surface oxide film intervenes between the front electrode, the passivation film, and a sealant, whereby the adhesive strength of the passivation film and the sealant is increased.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A semiconductor device includes an insulated circuit board having a semiconductor chip thereon, a W-phase output terminal electrically connected to the chip, a cooling device including a cooling top plate having a top surface on which the insulated circuit board is disposed, and a case including a frame portion on the cooling top plate and having an open storage area in which the insulated circuit board is stored, and a current detection unit for detecting an output current flowing through the output terminal. The output terminal extends from the unit storage portion to an outside the case and passes through the current detection unit. The current detection unit is embedded within the frame portion such that a shortest external dimension thereof is parallel to a first direction that is perpendicular to the top surface in the cooling area of the cooling top plate.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
H01F 17/04 - Fixed inductances of the signal type with magnetic core
H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
An integrated circuit includes: an amplifier circuit outputting a first voltage and a second voltage respectively in a first case and a second case, in which two input voltages of opposite polarities are applied to a pair of input terminals of a bridge circuit, the first and second voltages being based on a reference voltage and first and second amplified voltages, obtained by amplifying, by a predetermined gain, first and second output voltages outputted from a pair of output terminals of the bridge circuit; and a reference voltage output circuit setting the reference voltage to a first level and a second level respectively in the first and second cases. The first and second levels respectively correspond to a sum of, and a difference between, a predetermined voltage and another amplified voltage obtained by amplifying, by the predetermined gain, an offset voltage generated at the output terminals of the bridge circuit.
A semiconductor device comprising a semiconductor substrate having upper and lower surfaces and a hydrogen containing region containing hydrogen and helium is provided. The carrier concentration distribution of the hydrogen containing region has: a first local maximum point; a second local maximum point closest to the first local maximum point among local maximum points positioned between the first local maximum point and the upper surface; a first intermediate point of the local minimum between the first and second local maximum points; and a second intermediate point closest to the second local maximum point among local minimum points or flat points where the carrier concentration remains constant positioned between the second local maximum point and the upper surface. A highest point of a helium concentration peak is positioned between the first and second local maximum points. The carrier concentration is lower at the first intermediate point than the second intermediate point.
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
Provided is a semiconductor device comprising a gate trench portion and a first trench portion adjacent to the gate trench portion, the semiconductor device comprising: a drift region of a first conductivity type; a base region of a second conductivity type; an emitter region of the first conductivity type that is provided above the base region and has a higher doping concentration than that of the drift region; and a contact region of the second conductivity type that is provided above the base region and has a higher doping concentration than that of the base region. In a mesa portion between the gate trench portion and the first trench portion, the contact region may have a first contact portion and a second contact portion that are provided to extend from the first trench portion to below a lower end of the emitter region.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Provided is a semiconductor apparatus having a MOS gate structure, comprising: a semiconductor substrate; a first interlayer dielectric film provided above an upper surface of the semiconductor substrate and including a first opening; and a second interlayer dielectric film stacked on the first interlayer dielectric film and including a second opening overlapping the first opening in a top view, wherein a width of the first opening in a first direction is different from a width of the second opening in the first direction, at a boundary height between the first interlayer dielectric film and the second interlayer dielectric film.
Provided is a semiconductor module, including: a first switching device provided in one of an upper arm or a lower arm; a second switching device provided in another of the upper arm or the lower arm; a first diode device provided in parallel with the first switching device; a second diode device provided in parallel with the second switching device; a laminated substrate of which a main surface has two sides extending in a predetermined first direction and a predetermined second direction; and a gate external terminal and an auxiliary source external terminal provided farther toward a negative side of the first direction than the upper arm and the lower arm, and arranged in the second direction.
H02M 7/00 - Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
An edge termination structure portion has one or more guard rings of a second conductivity type that are provided between a well region and an end side of a semiconductor substrate, and are exposed to an upper surface of the semiconductor substrate, a first conductivity type region that is provided between a first guard ring that is closest to the well region, among the one or more guard rings, and the well region, and a first field plate that is provided above the upper surface of the semiconductor substrate, and is connected to the first guard ring, and the first field plate overlaps 90% or more of the first conductivity type region between the first guard ring and the well region.
A semiconductor device includes: a gate trench portion provided in a semiconductor substrate; a first trench portion provided in the semiconductor substrate and adjacent to the gate trench portion; an emitter region of a first conductivity type provided to be in contact with the gate trench portion in a mesa portion between the gate trench portion and the first trench portion; a contact region of a second conductivity type provided to be in contact with the first trench portion in the mesa portion; a metal layer provided above the semiconductor substrate; and a resistance portion of the first conductivity type provided to be in contact with the metal layer and the emitter region and having a lower doping concentration than that of the emitter region.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
27.
METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
A gate insulating film has a multilayer structure including a SiO2 film, a LaAlO3 film, and an Al2O3 film that are sequentially stacked, relative permittivity of the gate insulating film being optimized by the LaAlO3 film. In forming the LaAlO3 film constituting the gate insulating film, a La2O3 film and an Al2O3 film are alternately deposited repeatedly using an ALD method. The La2O3 film is deposited first, whereby during a POA performed thereafter, a sub-oxide of the surface of the SiO2 film is removed by a cleaning effect of lanthanum atoms in the La2O3 film. A temperature of the POA is suitably set in a range from 700 degrees C. to less than 900 degrees C.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
28.
SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS
A manufacturing method of a semiconductor apparatus, including: preparing a wafer on which an adhesion layer is provided in an outer peripheral region of a front surface; applying a protective tape on the front surface of the wafer, wherein the protective tape is applied on the adhesion layer; cutting a front surface of the protective tape; and grinding a back surface of the wafer while holding the wafer by a grinding apparatus through the protective tape, is provided. In addition, a semiconductor apparatus, including: a wafer; a semiconductor device provided in a central region of a front surface of the wafer; and an adhesion layer of a polyimide film provided in an outer peripheral region surrounding the central region on the front surface of the wafer, is provided.
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
Provided is a semiconductor device including: a plurality of trench portions which are provided to positions below a base region from an upper surface of a semiconductor substrate and are arranged next to one another in a first direction on the upper surface of the semiconductor substrate; a first lower end region of a second conductivity type, which is arranged at a first depth position and is provided in contact with a lower end of two or more of the trench portions; and a second lower end region which is arranged at the first depth position and is arranged at a position not overlapping with the first lower end region, in which the second lower end region includes at least one of a region of a first conductivity type or a region of a second conductivity type which has a lower doping concentration than the first lower end region.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes an integrated circuit having a first resistor configuring a voltage divider circuit, a sensing resistor configured to measure a sheet resistance having a same attribute as that of the first resistor, a temperature detection circuit configured to detect a value of a first temperature, a storage circuit configured to store a table including first information for each of a plurality of values of the first temperatures, the first information corresponding to a sheet resistance of the first resistor obtained based on a result of measurement of the sensing resistor, and indicating a relationship between a second temperature and a divided voltage of the voltage divider circuit at the second temperature, and an arithmetic circuit configured to obtain the second temperature, based on the first information at the value of the first temperature detected by the temperature detection circuit and the divided voltage.
G01K 7/24 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit
G01K 7/42 - Circuits effecting compensation of thermal inertia; Circuits for predicting the stationary value of a temperature
H01L 21/66 - Testing or measuring during manufacture or treatment
31.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device including a semiconductor chip, an insulating circuit board having a circuit pattern formed on an insulating plate, a case including a frame part having an opening that is substantially rectangular in a plan view of the semiconductor device, inner wall surfaces of the frame part at the opening forming a storage part to store the insulating circuit board, and a printed circuit board which has a flat plate shape and which protrudes from one of the inner wall surfaces of the frame part toward the storage part. The semiconductor device further includes a sealing material filled in the storage part, to thereby seal the semiconductor chip and the printed circuit board. A front surface of the sealing material forms a sealing surface, and in a thickness direction of the semiconductor chip, the sealing surface is higher around the printed circuit board than around the semiconductor chip.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/057 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads being parallel to the base
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Provide is a laser welding method of a lamination member including a second base material provided on a first base material, the laser welding method including forming a first scanning route by scanning a laser from a first point of the lamination member to a second point different from the first point, the first point being predetermined, and forming a second scanning route, at least a portion of which is shared with the first scanning route, by scanning the laser from a third point of the lamination member to a fourth point different from the third point, the third point being predetermined, and melting the first base material and the second base material in a common region between the first scanning route and the second scanning route, in which a welding depth of the first base material is 0.2 mm or more and 0.7 mm or less.
A bonding tool for bonding two conductive plates in contact with each other by pressing the bonding tool against the two conductive plates while vibrating a bonding end portion thereof in a direction parallel to the conductive plates. The bonding end portion of the bonding tool includes a bonding base having an end surface, the end surface having a protrusion area that has two sides facing and parallel to each other in a first direction that is parallel to the end surface, a plurality of protrusions provided in the protrusion area of the end surface, and a suppression portion provided on the end surface along the two sides of the protrusion area. The bonding end portion is configured to vibrate in the first direction.
A solder material having a good thermal-cycle fatigue property and wettability. The solder material contains not less than 6.0% by mass and not more than 8.0% by mass Sb, not less than 3.0% by mass and not more than 5.0% by mass Ag, and the balance of Sn and incidental impurities. Also, a semiconductor device may include a joining layer between a semiconductor element and a substrate electrode or a lead frame, the joining layer being obtained by melting this solder material.
B23K 35/02 - Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
B23K 1/00 - Soldering, e.g. brazing, or unsoldering
B23K 1/20 - Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
B23K 35/26 - Selection of soldering or welding materials proper with the principal constituent melting at less than 400°C
C22C 13/02 - Alloys based on tin with antimony or bismuth as the next major constituent
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
35.
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
Provided is a semiconductor device including a semiconductor substrate; a transistor portion provided in the semiconductor substrate; a current sensing portion for detecting current flowing through the transistor portion; an emitter electrode set to an emitter potential of the transistor portion; a sense electrode electrically connected to the current sensing portion; and a Zener diode electrically connected between the emitter electrode and the sense electrode. Provided is a semiconductor device fabricating method including providing a transistor portion in a semiconductor substrate; providing a current sensing portion for detecting current flowing through the transistor portion; providing an emitter electrode set to an emitter potential of the transistor portion; providing a sense electrode electrically connected to the current sensing portion; and providing a Zener diode electrically connected between the emitter electrode and the sense electrode.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes: a resin insulated substrate including a first rein insulating layer, a conductor base provided on one of main surfaces of the first resin insulating layer, and a conductor foil provided on another main surface of the first resin insulating layer; a power semiconductor element bonded to the conductor foil; a case surrounding an outer circumference of the resin insulated substrate; a sealing resin provided inside the case to seal the power semiconductor element; and a second resin insulating layer provided between the first resin insulating layer and the sealing resin and having a lower water-absorption rate than the sealing resin.
A semiconductor device includes a semiconductor chip having a main electrode on a front surface thereof, a wiring board having a front surface to which a rear surface of the semiconductor chip is bonded, a sealing member sealing the wiring board and the semiconductor chip, and an adhesive layer including at least two adhesive films that are laminated to each other. The adhesive layer is provided on surfaces of the wiring board and the semiconductor chip so that the sealing member seals the wiring board and the semiconductor chip via the adhesive layer. As a result, the sealing member is able to reliably seal the semiconductor chip and wiring board via the adhesive layer, thereby preventing an occurrence and extension of separation.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
39.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a transistor portion, in which the transistor portion has a drift region of a first conductivity type provided in a semiconductor substrate, a base region of a second conductivity type provided above the drift region, an accumulation region of the first conductivity type provided above the drift region, a plurality of trench portions provided to extend from a front surface of the semiconductor substrate to the drift region, and a trench bottom portion of the second conductivity type provided in bottom portions of the plurality of trench portions, and the accumulation region has a doping concentration with a half width of 0.3 μm or more.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A switching control circuit for a power factor correction circuit configured to generate an output voltage from an alternating current (AC) voltage, the power factor correction circuit including an inductor configured to receive a rectified voltage corresponding to the AC voltage, and a transistor configured to control an inductor current flowing through the inductor. The switching control circuit is configured to control switching of the transistor. The switching control circuit includes: a driving signal output circuit configured to, when a peak value of the inductor current in a half cycle of the AC voltage is smaller than and greater than a first predetermined value, output a driving signal to operate the power factor correction circuit in a critical mode and in a continuous mode, respectively; and a driver circuit configured to drive the transistor, in response to the driving signal.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/217 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
41.
SWITCHING CONTROL CIRCUIT AND POWER SUPPLY CIRCUIT
A switching control circuit for a power supply circuit that includes an inductor to which a voltage in accordance with an alternating current (AC) voltage is applied, and a transistor controlling an inductor current flowing through the inductor, the power supply circuit generating an output voltage from the AC voltage, the switching control circuit being configured to control switching of the transistor, the switching control circuit comprising: an ON signal output circuit that outputs an ON signal to turn on the transistor in response to the inductor current reaches a predetermined current, when a feedback voltage in accordance with the output voltage indicates that the output voltage is lower than a first level, and outputs the ON signal every first cycle when the feedback voltage indicates that the output voltage is higher than the first level; an OFF signal output circuit that outputs an OFF signal to turn off the transistor based on the feedback voltage; and a driver circuit that drives the transistor based on the ON signal and the OFF signal, wherein the first cycle is longer than a second cycle, which is a cycle of the ON signal when the output voltage is lower than the first level.
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
42.
SEMICONDUCTOR MODULE, POWER CONVERTER, AND POWER CONVERTER MANUFACTURING METHOD
A semiconductor module includes an insulated circuit substrate including a semiconductor chip, an insulated circuit substrate including a wiring board provided on a front surface thereof, the wiring board having the semiconductor chip bonded thereto, a heat dissipation base having a front surface and a rear surface opposite to each other. The front surface has a substrate region to which the insulated circuit substrate is bonded. The rear surface has a heat dissipation region positioned overlapping the substrate region in a plan view of the semiconductor module and a loop-shaped region surrounding the heat dissipation region. The semiconductor module further includes a solid heat dissipation member made of a phase change material and provided on the rear surface of the heat dissipation base in the heat dissipation region, and an elastic member provided on the rear surface of the heat dissipation base in the loop-shaped region.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A method of manufacturing a semiconductor device includes: forming a first trench from an upper surface side of a semiconductor substrate; burying the first trench with an insulated gate electrode structure; forming a base region at an upper part of the semiconductor substrate so as to be in contact with the first trench; forming a first main electrode region at an upper part of the base region so as to be in contact with the first trench; forming a second trench by removing a part of the first main electrode region; implanting first impurity ions entirely into a side wall surface of the second trench from a diagonally upper side; implanting second impurity ions into a bottom surface of the second trench to form a contact region at a bottom of the second trench; and forming a second main electrode region on a bottom surface side of the semiconductor substrate.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
45.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: an insulated gate electrode structure provided in a semiconductor substrate; a base region; a first main electrode region; a contact plug buried in a trench penetrating the first main electrode region to reach the base region with a barrier metal film interposed; an interlayer insulating film provided with a contact hole integrally connected to the trench; a contact region provided in contact with a bottom of the trench; and a second main electrode region, wherein an opening width at a lower end of the contact hole conforms to a width at an opening of the trench, an upper part of a side wall continued from the opening of the trench has a curved surface convex to an outside, and a lower part of the side wall continuously connected to the bottom of the trench has a curved surface convex to the outside.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A p++-type outer peripheral contact region is provided in an edge termination region and surrounds a periphery of an active region in a rectangular shape having rounded corners, in a plan view. The p++-type outer peripheral contact region faces a gate runner on a front surface of a semiconductor substrate via an insulating layer. In the active region, a p++-type region is provided facing a gate pad on the front surface of the semiconductor substrate via the insulating layer. The p++-type outer peripheral contact region and the p++-type region are provided apart from p++-type contact regions that form source contacts with a source electrode. The p++-type contact regions and contact holes in which the source contacts are formed are disposed in a uniform layout spanning an entire area of the active region so that an end side and a center side of the active region have the same layout.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
47.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; first semiconductor regions of the first conductivity type; trenches; gate insulating films; gate electrodes; first high-concentration regions of the second conductivity type provided at positions facing the trenches in a depth direction; second high-concentration regions of the second conductivity type, selectively provided between the trenches and in contact with the first semiconductor regions, each having an upper surface exposed at the surface of the second semiconductor layer and a lower surface partially in contact with upper surfaces of the first high-concentration regions; a first electrode; and a second electrode. The second high-concentration regions are disposed periodically in a longitudinal direction of the trenches.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
48.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device has an active region through which current flows and an edge termination structure region arranged outside the active region. The semiconductor device includes a low-concentration semiconductor layer of a first conductivity type, and formed in the edge termination structure region, on a front surface of a semiconductor substrate. The semiconductor device includes a second semiconductor layer of a second conductivity type, in contact with one of a semiconductor layer of the second conductivity type in the active region and a semiconductor layer of the second conductivity type in contact with a source electrode. The second semiconductor layer has an impurity concentration that is lower than that of the semiconductor layer, and the second semiconductor layer is not in contact with a surface of the semiconductor substrate.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A method of manufacturing a semiconductor module includes: placing, on a lower hot plate, an insulating wiring substrate having an electrically-conductive pattern formed on an insulating substrate; placing sintered materials on the electrically-conductive pattern; placing semiconductor chips on the sintered materials; placing a cushioning material over the semiconductor chips; placing an upper hot plate on the cushioning material; and sintering the sintered materials by pressurizing and heating the sintered materials via the cushioning material and the electronic components by the upper hot plate in a state where a space is provided between the upper hot plate and a part of the insulating substrate.
A method for manufacturing a semiconductor module includes arranging an insulating wiring board on a lower die, arranging sintered materials at a plurality of points on the insulating wiring board, arranging each semiconductor chip on the sintered materials, arranging each buffer material individually on the semiconductor chips, arranging, above the lower die, an upper die including protrusions at points corresponding to arrangement positions of the semiconductor chips so that the protrusions correspond to the semiconductor chips, and sintering by pressurizing and heating the sintered materials by the protrusions through the buffer materials and the semiconductor chips.
Provided is a semiconductor device including a buffer region of a first conductivity type, which is provided between a lower surface of a semiconductor substrate and a drift region, has three or more doping concentration peaks in a depth direction of the semiconductor substrate, and has a higher concentration than the drift region, in which the three or more doping concentration peaks include a deepest peak farthest from the lower surface of the semiconductor substrate and a second peak second closest to the lower surface of the semiconductor substrate, and a peak width of the second peak is 2 times or more of a peak width of the deepest peak in the depth direction.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A switching control circuit for a power supply circuit generating an output voltage from an AC voltage. The power supply circuit includes an inductor receiving a first rectified voltage corresponding to the AC voltage, and a transistor controlling an inductor current flowing through the inductor. The switching control circuit controls switching of the transistor, and comprises: an identification circuit identifying whether an effective value of the AC voltage is a first or second level; a first comparator circuit comparing the inductor current with a first current value and a second current value, respectively when the effective value is the first level and the second level; and a driver circuit driving the transistor based on the inductor current and the output voltage. The driver circuit turns off the transistor in response to the inductor current exceeding the first current value or the second current value as a result of comparison.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
53.
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
To provide a manufacturing method of a semiconductor device including forming a lifetime control region from the side of a front surface of a semiconductor substrate, ion-implanting Ti into a bottom surface of a contact hole provided so as to penetrate through an interlayer dielectric film arranged on the front surface of the semiconductor substrate, and forming a Ti silicide layer at the bottom surface of the contact hole with anneal.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
A manufacturing method of a silicon carbide semiconductor device includes: epitaxially growing a drift layer of a first conductivity-type on a silicon carbide substrate of the first conductivity-type; forming a base region of a second conductivity-type on the drift layer; forming a main region of the first conductivity-type on the drift layer so as to be in contact with the base region; forming a gate insulating film so as to be in contact with the base region and the main region; forming a gate electrode so as to be in contact with the base region and the main region with the gate insulating film interposed; and forming a lifetime killer region at a depth covering a bottom surface of the drift layer by irradiating the top surface side of the drift layer with a lifetime killer after epitaxially growing the drift layer and before forming the gate insulating film.
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
A method for manufacturing a semiconductor module can prevent performance and reliability degradation of a semiconductor module. The method for manufacturing a semiconductor module includes: arranging an insulating wiring board on a low die; arranging a sintering material at plural locations on the insulating wiring board and arranging a semiconductor chip on each of the plural sintering materials; arranging a structure above protruding portions of the sintering materials protruding from a periphery of each of the plural semiconductor chips; and sintering by pressurizing and heating the plural sintering materials by an upper die through the structure at the protruding portions and through the semiconductor chips at contacting portions in contact with lower surfaces of the semiconductor chips.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
56.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
An AlSi electrode containing an aluminum alloy that contains silicon is sputtered on a surface of a semiconductor substrate that contains silicon carbide. Si nodules having a dendrite structure precipitate in AlSi electrode. At least some of the Si nodules have a dendrite structure, and the rest of the Si nodules have a prismatic structure. A height of the Si nodules having either dendrite structures or prismatic structures in the AlSi electrode in a thickness direction of the AlSi electrode is not more than 2 μm. A height of the Si nodules having the dendrite structures in the AlSi electrode, preferably, may be 1 μm or less. A solid solubility of silicon in the AlSi electrode is in a range of 0.3 wt % to 1.59 wt %. A sputtering temperature of the AlSi electrode is in a range of 430 degrees C. to 577 degrees C.
A silicon carbide semiconductor device has a first semiconductor region of a first conductivity type, provided in a semiconductor substrate, spanning an active region and a termination region. A second semiconductor region of a second conductivity type is provided between a first main surface and the first semiconductor region, in the active region. A device structure having a first pn junction is provided between the first and second semiconductor regions. An outer peripheral portion of the active region is provided between the first main surface and the first semiconductor region in the active region, and constitutes a second-conductivity-type outer peripheral region that surrounds a periphery of the device structure and forms a second pn junction with the first semiconductor region. A first protective film is provided on the first main surface. The first protective film blocks light generated by a forward current passing through the first and second pn junctions.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Provided is a semiconductor device including a plurality of mesa portions which are arranged one by one between two of trench portions adjacent to each other in a second direction in a semiconductor substrate. The plurality of mesa portions includes a floating mesa portion which is insulated from an emitter electrode, and an emitter-connected mesa portion which is arranged adjacent to the floating mesa portion in the second direction and is connected to the emitter electrode. At least one of the floating mesa portion or the emitter-connected mesa portion is provided in a portion provided at a position not overlapping the well region in a top view to connect two of the trench portions sandwiching the mesa portion, and has a separation portion which separates the well region from at least a part of the mesa portion.
A power conversion apparatus includes a board including a device for power conversion mounted on the board; a connector fixed to the board and configured to electrically connect the board to an external side; a top plate formed of a metal plate and arranged to cover the board; and a bottom plate formed of a metal plate and arranged to face the top plate. The bottom plate includes a bottom-plate folded part that is arranged on an end part of the bottom plate on which the connector is arranged, and is folded to contact the connector whereby preventing movement of the connector.
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
A semiconductor device, including a semiconductor substrate having a transistor portion and a diode portion, a drift region of a first conductivity type provided in the semiconductor substrate, a first electrode provided on one main surface side of the semiconductor substrate, and a second electrode provided on another main surface side of the semiconductor substrate, is provided. The diode portion includes a high concentration region and a crystalline defect region. The high concentration region has a higher doping concentration than the drift region and includes hydrogen. The doping concentration of the high concentration region at a peak position in a depth direction of the semiconductor substrate is equal to or less than 1.0×1015/cm3. The crystalline defect region is provided on the one main surface side of the semiconductor substrate relative to the peak position, has a higher crystalline defect density than the drift region, and includes hydrogen.
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 μm. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 21/263 - Bombardment with wave or particle radiation with high-energy radiation
H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
A semiconductor device includes: an isolation circuit board; a semiconductor chip provided on one main surface of the isolation circuit board; a first external terminal having a main surface and including a first snubber connecting portion rising from the main surface of the first external terminal, the first external terminal being electrically connected to the semiconductor chip; a second external terminal placed adjacent to the first external terminal, having a main surface facing the same direction as the main surface of the first external terminal, and including a second snubber connecting portion rising from the main surface of the second external terminal, the second external terminal being electrically connected to the semiconductor chip; and a capacitor having one end connected to the first snubber connecting portion and the other end connected to the second snubber connecting portion
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
An integrated circuit for a power supply circuit that includes a detection resistor. The integrated circuit includes: a first pad; a first terminal coupled to the detection resistor, the first terminal being electrically connected to the first pad in a first case, and being electrically separated from the first pad in a second case; a first temperature detection circuit having a temperature detection element, and being configured to detect a first temperature based on a voltage of the temperature detection element; a second temperature detection circuit configured to detect a second temperature of the integrated circuit, based on a first voltage corresponding to a resistance value of the detection resistor, received through the first pad in the first case; and a circuit configured to operate based on results of detection of the second and first temperature detection circuits, respectively in the first case and in the second case.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
A semiconductor module includes: first and second switching devices coupled in series; a casing housing the first and second switching devices, and having first to fourth edges respectively on first to forth edge sides thereof; positive and negative terminals provided on the first edge side of the casing; an output terminal provided on the second edge side of the casing; a first control terminal and a first sense terminal for the first switching device, and a second control terminal and a second sense terminal for the second switching device, all provided on the third edge side of the casing; first and second conductive patterns respectively coupled to the positive terminal and the output terminal, and on which the first and second switching device are respectively arranged; and a third conductive pattern coupled to the negative terminal and the second switching device, on a side corresponding to the fourth edge side.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H02M 3/155 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A silicon carbide semiconductor device has an n-type silicon carbide semiconductor substrate, an n-type first semiconductor layer, n-type first JFET regions, a p-type second semiconductor layer, n-type first semiconductor regions, and trenches. The first semiconductor layer has an impurity concentration lower than that of the substrate. The first JFET regions are provided in a surface layer of the first semiconductor layer and have an effective donor concentration higher than that of the first semiconductor. The p-type second semiconductor layer is provided at a surface of the first semiconductor layer. The n-type first semiconductor regions are selectively provided in a surface layer of the second semiconductor layer. The trenches penetrate through the first semiconductor regions, the second semiconductor layer, and the first JFET regions. The first JFET regions are doped with an acceptor that is aluminum and a donor that is nitrogen or phosphorus.
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Provided is a manufacturing method of a semiconductor apparatus including: detecting a position by detecting positional deviation of the upper surface mark and the lower surface mark, by acquiring an upper surface image obtained by observing the upper surface mark from above the upper surface of the semiconductor substrate and a lower surface image obtained by observing the lower surface mark through the semiconductor substrate from above the upper surface of the semiconductor substrate; and forming an element by forming a semiconductor element in the semiconductor substrate, where in a top view in which the upper surface mark and the lower surface mark are projected onto a plane parallel to the upper surface, one of the upper surface mark and the lower surface mark is larger than an other, and the one entirely covers the other.
A semiconductor device includes a main circuit and a control circuit. The main circuit includes a plurality of series circuits that are connected in parallel to one another. Each series circuit includes a high-side switching element and a low-side switching element that are connected in series. The control circuit includes first to third input terminals through which a serial drive signal serving as a driving signal of each high-side switching element and each low-side switching element is inputted, a first clock signal, and a second clock signal are respectively inputted, and a plurality of output terminals. The control circuit holds the serial drive signal based on the first clock signal, and based on the second clock signal outputs, to each high-side switching element and each low-side switching element, parallel signals generated from the serial drive signal.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 7/5387 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor module includes at least, a conductive pattern on the insulating substrate; a first semiconductor element on the conductive pattern, a second semiconductor element on the conductive pattern, a first power collecting portion connected to a first output electrode of the first semiconductor element with a first line; and a second power collecting portion connected to a second output electrode of the second semiconductor element with a second line. Each of the first and second semiconductor elements includes both a switching element and a diode. The conductive pattern is provided between the first power collecting portion and the second power collecting portion. A current path length from a first output electrode of the first semiconductor element to the first power collecting portion and a current path length from a second output electrode of the second semiconductor element to the second power collecting portion are equal to each other.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/528 - Layout of the interconnection structure
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Provided is a semiconductor device including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region arranged sandwiching the active portion in a top view, provided on the semiconductor substrate; an emitter electrode arranged above the active portion; and a pad arranged above the first well region, away from the emitter electrode, wherein the emitter electrode is provided above the second well region. The provided semiconductor device further includes a peripheral well region arranged enclosing the active portion in a top view, wherein the first well region and the second well region may protrude to the center side of the active portion rather than the peripheral well region.
A manufacturing method of a semiconductor apparatus including: setting, depending on a distribution of the carrier concentrations that the buffer region should have, a dose amount of hydrogen ions to be implanted into a plurality of depth positions corresponding to the plurality of concentration peaks; and implanting, depending on the dose amount that is set in the setting, the hydrogen ions into the semiconductor substrate is provided. In the setting, among the plurality of concentration peaks, the dose amount of the hydrogen ions for a deepest peak farthest from the lower surface of the semiconductor substrate is set depending on a carbon concentration of the semiconductor substrate, and the dose amount for at least one of the concentration peaks other than the deepest peak is set regardless of the carbon concentration of the semiconductor substrate.
The generated amount of silica scale under complicated conditions is accurately predicted. A method for predicting a generated amount of silica scale includes: a step of acquiring a temperature at a prediction portion at which the adherence of silica scale needs to be predicted, Ts (K), and/or time until fluid containing silicic acid reaches the prediction portion, ts (min), and a step of calculating the amount of silica adhered at the prediction portion based on the predictive equation of the saturation concentration of silica depending on the temperature and/or the predictive curve of the concentration of silica dissolved depending on the time, wherein the predictive equation of the saturation concentration of silica and the predictive curve of the concentration of silica dissolved are obtained based on k1, k2, kB, and ka in a three-step precipitation equilibrium reaction model represented by the following
The generated amount of silica scale under complicated conditions is accurately predicted. A method for predicting a generated amount of silica scale includes: a step of acquiring a temperature at a prediction portion at which the adherence of silica scale needs to be predicted, Ts (K), and/or time until fluid containing silicic acid reaches the prediction portion, ts (min), and a step of calculating the amount of silica adhered at the prediction portion based on the predictive equation of the saturation concentration of silica depending on the temperature and/or the predictive curve of the concentration of silica dissolved depending on the time, wherein the predictive equation of the saturation concentration of silica and the predictive curve of the concentration of silica dissolved are obtained based on k1, k2, kB, and ka in a three-step precipitation equilibrium reaction model represented by the following
G01N 17/00 - Investigating resistance of materials to the weather, to corrosion or to light
G16C 60/00 - Computational materials science, i.e. ICT specially adapted for investigating the physical or chemical properties of materials or phenomena associated with their design, synthesis, processing, characterisation or utilisation
A semiconductor module includes: a laminated substrate configured by laminating an insulating plate, a heat dissipation plate disposed on a lower surface of the insulating plate, and a circuit plate disposed on an upper surface of the insulating plate; a semiconductor element disposed on an upper surface of the circuit plate; a case that surrounds the laminated substrate and a space housing the semiconductor element; a sealing resin filling the space of the case to seal the semiconductor element; and a partition wall that extends in an up-down direction to divide the space filled with the sealing resin into a plurality of subspaces. The partition wall has a lower end and an upper end opposite to each other in the up-down direction. At least a portion of the lower end of the partition wall is connected to the upper surface of the circuit plate.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor apparatus includes a semiconductor module, a substrate having a control unit that controls an operation of the semiconductor module, a busbar that allows a current to flow through the semiconductor module, and a shield arranged between at least respective opposing surfaces of the control unit and the busbar that oppose to each other.
H05K 9/00 - Screening of apparatus or components against electric or magnetic fields
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
An integrated circuit for a power supply circuit. The integrated circuit includes: a first terminal to which a first resistor, a second resistors, and a switch, of the power supply circuit are coupled; a current output circuit outputting a current to the first terminal; a switch control circuit causing the switch to be in a first state or a second state, in which a voltage according to the first resistor or the second resister are respectively applied to the first terminal; a storage circuit; a processing circuit storing an operating condition of the integrated circuit in the storage circuit, based on a first voltage at the first terminal when the switch is in the first state; and a temperature detection circuit detecting a temperature, based on a second voltage at the first terminal when the switch is in the second state.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes a first semiconductor unit that includes a first substrate including a first wiring board to which a first semiconductor chip is bonded, a second semiconductor unit that includes a second substrate including a second wiring board to which a second semiconductor chip is bonded, a cooling unit including a first cooling surface and a second cooling surface that are opposite to each other and respectively have the first semiconductor unit facing the first substrate thereon and the second semiconductor unit facing the second substrate thereon, and an output terminal provided at a first side of the cooling unit and being connected to both the first wiring board and the second wiring board.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
P++-type contact regions are disposed apart from one another, and in a p−-type base region, at least hole current regions directly beneath the contact regions have an impurity concentration of not more than 5×1016/cm3. A p+-type region for mitigating electric field and disposed between adjacent gate trenches is separated into first portions in contact with the hole current regions and second portions in contact with only a portion of the base region other than the hole current regions. During conduction of body diodes, forward current flows into an n−-type drain region through the contact regions, the hole current regions, and the first portions. Thus, in the drain region, holes from the base region are injected only into hole injection regions that are directly beneath the first portions, but are not injected into regions that respectively surround peripheries of the hole injection regions.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a main semiconductor region and a current detecting region. The main semiconductor region and the current detecting region have a semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type, first semiconductor regions of a second conductivity type, second semiconductor regions of the first conductivity type, trenches, first high-concentration regions of the second conductivity type, and second high-concentration regions of the second conductivity type. An active region through which a current flows when the current detecting region is in an on-state has a first cell region that operates as a transistor and second cell regions that are provided, respectively, in four corners of the first cell region and operate only as diodes and not as a transistor.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
In an intermediate region between an active region and an edge termination region, on a front surface of a semiconductor substrate, a gate polysilicon wiring layer is provided via an insulating layer in which a gate insulating film and a field oxide film are stacked sequentially. An inner peripheral end of the field oxide film is positioned directly beneath the gate polysilicon wiring layer, which extends inward from the field oxide film and terminates on the gate insulating film. At the surface of the insulating layer directly beneath the gate polysilicon wiring layer, on the inner peripheral end of the field oxide film, a drop is formed by a difference in thickness due to whether the field oxide film is present. A distance from the drop to a contact hole of the active region is 21 μm or less.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
80.
SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE
A semiconductor module includes a stacked substrate includes an insulating plate and first and second circuit boards arranged on the insulating plate, a semiconductor element arranged on the first circuit board, and a metal wiring board having a first bonding portion bonded to an upper surface of the semiconductor element via a first bonding material. The first bonding portion includes a first plate-shaped portion that has at a lower surface thereof, a boss protruding toward the semiconductor element, and at an upper surface thereof, a first recess at a position corresponding to a position immediately above the boss and multiple second recesses. At the upper surface of the first plate-shaped portion, each of the second recesses has an opening area smaller than an opening area of the first recess.
A silicon carbide semiconductor device has an active region, a first-conductivity-type region, and an edge termination region. The active region has first second-conductivity-type regions, a silicide film, and a first electrode; the edge termination region has a second second-conductivity-type region. The active region is configured by an ohmic region in which the silicide film is in contact with the first second-conductivity-type region, non-operating regions in which the first electrode is in contact with the first second-conductivity-type regions, and a Schottky region in which the first electrode is in contact with the first-conductivity-type region. The ohmic region, the non-operating regions, and the Schottky regions are provided in a striped pattern. A bottom surface of the silicide film in the ohmic region is positioned deeper than is an interface between the first electrode and the first second-conductivity-type regions in each of the plurality of non-operating regions.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
There is provided a semiconductor device that includes a diode portion, the semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; an anode region of a second conductivity type provided to be closer to a front surface side of the semiconductor substrate than the drift region; and a trench contact portion provided at a front surface of the semiconductor substrate in the diode portion, in which in a depth direction of the semiconductor substrate, a doping concentration of the anode region at a same depth as that of a bottom portion of the trench contact portion is 1E16 cm−3 or more and 1E17 cm−3 or less.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/745 - Gate-turn-off devices with turn-off by field effect
84.
SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE
A semiconductor module includes: a semiconductor device; a bonding layer that is arranged on the semiconductor device, and contains nickel or copper, an entire back surface of the bonding layer being electrically connected to and in direct contact with an electrode in the semiconductor device; an anti-oxidation layer disposed on the bonding layer; and a protective layer disposed directly on a top surface of a peripheral portion of the bonding layer on which the anti-oxidation layer is absent, covering an outer peripheral edge of the bonding layer, wherein the protective layer is made of an electrically insulating resin.
An object of the present invention is to provide a semiconductor device capable of suppressing loss in a switching element at high temperature without increasing radiation noise of the switching element. A semiconductor device includes an IGBT including a gate to which a gate signal is input, a temperature detection element that detects temperature of the IGBT, and a capacitance adjustment unit that is arranged between the gate of the IGBT and a reference potential terminal and that adjusts a capacitance between the gate and an emitter of the IGBT according to a detection temperature detected by the temperature detection element.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
86.
PRESSURE DETECTION DEVICE AND MANUFACTURING METHOD
Provided is a pressure detection device including: a semiconductor substrate having an upper surface; a bulk region of a first conductivity type provided in the semiconductor substrate; a piezo-resistive region of the first conductivity type provided between the bulk region and the upper surface of the semiconductor substrate; a first well region of a second conductivity type provided between the piezo-resistive region and the bulk region; and a first low-concentration region of the second conductivity type provided between the first well region and the bulk region and having a lower concentration than the first well region.
G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
Between the front surface of a semiconductor substrate and an n−-type drift region, a p++-type contact region, a p-type base region, a p+-type high-concentration region, and an n-type current spreading region are provided directly beneath a gate pad, sequentially from a front side of the semiconductor substrate so as to face an entire surface of a gate pad, via a field oxide film. The high-concentration region is electrically connected to source electrode wiring via a p++-type wiring region. N+-type regions that are electrically floating (or n+-type wiring regions of the source potential) are selectively provided between the front surface of the semiconductor substrate and the contact region. The n+-type regions have a function of drawing out holes in the high-concentration region and discharging the holes to the source electrode, when the voltage applied to the drain electrode rapidly increases with respect to the potential of the source electrode.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
88.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A diode formed by a polysilicon layer is disposed between a field oxide film and an interlayer insulating film, in a semiconductor substrate, at a front surface of the semiconductor substrate. One resist mask is used to form contact holes of the interlayer insulating film and contact trenches and a p+-type region of the polysilicon layer. The contact trenches are continuously formed from bottoms of the contact holes, respectively, in a depth direction. A low-resistance contact between the p+-type region and an anode electrode is formed at least at a bottom of the contact trench. During the formation of the p+-type region, while a p-type impurity is ion-implanted in an inner wall of the contact trench 3b, an n-type cathode region maintains an n-type conductivity thereof and a contact with a cathode electrode is formed at sidewalls of the contact trench.
A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
90.
POWER CONVERSION APPARATUS AND BIDIRECTIONAL SWITCH
A bidirectional switch, having: a first silicon carbide transistor; a first diode which is provided in series with the first silicon carbide transistor, and of which on voltage is lower than that of a built-in diode of the first silicon carbide transistor at a rated current of the bidirectional switch; a second silicon carbide transistor provided in parallel with the first diode; a second diode which is provided in series with the second silicon carbide transistor and in parallel with the first silicon carbide transistor, and of which on voltage is lower than that of a built-in diode of the second silicon carbide transistor at the rated current of the bidirectional switch; and a connection line which connects a first connection point between the first silicon carbide transistor and the first diode, and a second connection point between the second silicon carbide transistor and the second diode, is provided.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A permanent field magnet for a linear motor is provided. The permanent field magnet includes a plurality of permanent magnets arranged along a moving path of a mover; a first member that includes a soft magnetic material and is disposed between and in contact with mutually adjacent ones of the plurality of permanent magnets; and a suppressing portion configured to suppress application of a magnetic field from an armature to each of the permanent magnets.
Provided is a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; a base region of a second conductivity type provided between the drift region and the upper surface of the semiconductor substrate; a plurality of trench portions provided from the upper surface of the semiconductor substrate to below the base region; a lower end region of the second conductivity type provided in contact with lower ends of two or more trench portions; a well region of the second conductivity type which is provided from the upper surface of the semiconductor substrate to below the base region, and has a higher doping concentration than the base region; and a high resistance region of the second conductivity type which is arranged between the lower end region and the well region in the top view and has a lower doping concentration than the lower end region.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Provided is a semiconductor device in which each of a transistor portion and a diode portion has one or more trench contact portions provided from an upper surface of a semiconductor substrate in a depth direction of the semiconductor substrate, the transistor portion has a first bottom region of a second conductivity type provided in contact with a bottom of any one of the one or more trench contact portions, the diode portion has a second bottom region of the second conductivity type provided in contact with a bottom of any one of the one or more trench contact portions, and a length of the first bottom region in the extending direction is larger than a length of the second bottom region in the extending direction.
A semiconductor device includes an insulated circuit substrate, a semiconductor chip, a printed circuit board, an interposer, and a sealing member, the interposer including a plurality of post electrodes each having one end bonded to the semiconductor chip via a solder layer, an insulating layer provided to be separately opposed to the semiconductor chip and provided with a first penetration hole filled with part of the solder layer, and a conductor layer provided to be opposed to the printed circuit board and connected to another end of each of the post electrodes via the insulating layer.
A power conversion device includes a sealing material that fills the housing space of a case and that has a sealing surface located above a peak point of a wire included in a semiconductor unit in a side view of the device. The power conversion device further includes a buffering member that extends in a predetermined direction in plan view of the device and that has a buffering bottom surface located above the peak point of the wire and under the sealing surface in the side view.
A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01R 43/02 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections
Provided is a control circuit for controlling an ON period and an OFF period in a switching cycle of a switching element configured to perform switching control of a principal current flowing through a transformer of a switching power source, and performing control to turn off the switching element when an overcurrent is detected after an elapse of an invalidation period in the switching cycle and to set a period in which the switching element is turned on in the switching cycle to be minimum period or more, the control circuit including a shared timer unit configured to output a first timer signal for defining the invalidation period and a second timer signal for defining the minimum period.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
A semiconductor module includes: a mounting substrate including a mounting surface; a semiconductor element disposed on the mounting surface; a housing for the semiconductor element; a lid fixed to the housing and facing the mounting surface; an insulating sealing material disposed in a space inside the housing and sealing the semiconductor element; and a first adsorbent disposed between the lid and the insulating sealing material and is swollen by adsorption.
H01L 23/24 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel, at the normal operating temperature of the device
H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/26 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances
IGBT includes an n-type drift layer, an n-type accumulation layer provided on the upper surface of the drift layer having higher impurity concentration than the drift layer, a base layer provided on the upper surface of the accumulation layer, a gate electrode embedded inside a striped gate trench penetrating the base layer and the storage layer through a gate insulating film, and a dummy electrode embedded inside a dummy trench provided to face the gate trench across the base layer and the accumulation layer through a dummy insulating film. The base layer has a p-type active base region and a p-type floating base region arranged alternately in the extending direction of the gate trench, and an n-type base isolation region isolating the active base region and the floating base region.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
100.
SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD FOR SEMICONDUCTOR MODULE
A semiconductor module includes: a first die pad having a first face, and a second face directed in a direction opposite to the first face, a first outer lead positioned in the direction in which the second face is directed relative to the first die pad, a first inner lead connecting the first die pad and the first outer lead to each other and having a stepped portion, a first semiconductor chip joined to the second face, and a sealing material sealing the first die pad and the first semiconductor chip, in which the sealing material includes a first sealing portion joined to the first face and constituted of a first resin composition, and a second sealing portion joined to the second face and constituted of a second resin composition lower in thermal conductivity than the first resin composition, and the first sealing portion has an exposed face constituting a part of an outer surface of the sealing material, a first joining face joined to the first die pad, and a second joining face joined to the stepped portion along a height direction of the stepped portion.
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