A cleaner including a body including a body exhaust vent; a filter installable inside the body; and a fan motor device including a rotatable impeller to generate a suction force inside the body, a motor to rotate the impeller, and a diffuser device including a radiating diffuser extending in a radial direction from a rotational axis of the impeller, and an axial diffuser extending from the radiating diffuser. The fan motor device is configured so that, with the filter installed inside the body, rotation of the impeller by the power provided by the motor causes air to pass through the fan motor device and be discharged from the impeller, and then guided by the radiating diffuser in the radial direction from the rotational axis of the impeller, and then guided by the axial diffuser to the filter to be filtered, and then discharged through the body exhaust vent.
A47L 5/28 - Suction cleaners with handles and nozzles fixed on the casings, e.g. wheeled suction cleaners with steering handle
A47L 9/00 - DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL - Details or accessories of suction cleaners, e.g. mechanical means for controlling the suction or for effecting pulsating action; Storing devices specially adapted to suction cleaners or parts thereof; Carrying-vehicles specially adapted for suction cleaners
A semiconductor package includes: a semiconductor chip having chip pads disposed on a first surface thereof; a redistribution wiring layer formed on the first surface, wherein the redistribution wiring layer includes an insulating layer, redistribution wirings, a protective layer, and an under bump metallurgy (UBM) pad of UBM pads, wherein the insulating layer is formed on the first surface, wherein the redistribution wirings are provided on the insulating layer and are electrically connected to the chip pads, wherein the protective layer is provided on the insulating layer and has an opening that exposes at least a portion of a first redistribution wiring of the redistribution wirings, and wherein the under bump metallurgy (UBM) pad is provided on the at least a portion of the first redistribution wiring that is exposed by the opening; and conductive bumps disposed on the UBM pads of the redistribution wiring layer.
Disclosed is an electronic device according to various embodiments. The electronic device includes: a housing including a metal portion and a polymer portion, a substrate disposed in the housing, a connector disposed in the housing and that electrically connecting the metal portion and the substrate, and a screw fastening the metal portion of the housing and the connector and passing through the connector and at least a portion of the metal portion. The connector includes: a base portion seated on the metal portion and through which the screw passes, a movable portion at least partially facing the base portion and through which the screw passes, a bending portion connecting one side of the base portion and the movable portion, and a connecting portion extending from an opposite side of the base portion and connected to the substrate.
An electronic device is provided. The electronic device includes a speaker, a communication module for supporting Bluetooth communication, one or more processors and, memory storing one or more programs including computer-executable instructions that, when executed by the one or more processors, cause the electronic device to identify the received signal strength indication (RSSI) of a Bluetooth communication signal received from an external electronic device via the communication module, during executing a first function using the speaker, identify whether a second function using the speaker is executed together with the first function, control a frequency value of a driving clock of the one or more processor based on the RSSI and the first function and the second function being executed together, adjust the driving clock of the one or more processor to the first frequency value when the RSSI is included in a first range indicating a weak electric field, and adjust the driving clock to a second frequency value that is lower than the first frequency value when the RSSI is included in a second range indicating a strong electric field.
A system and a method are disclosed for processing and combining feature maps using a hardware friendly multi-kernel convolution block (HFMCB). The method including splitting an input feature map into a plurality of feature maps, each of the plurality of feature maps having a reduced number of channels; processing each of the plurality of feature maps with a different series of kernels; and combining the processed plurality of feature maps.
G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding
G06V 10/77 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using data integration or data reduction, e.g. principal component analysis [PCA] or independent component analysis [ICA] or self-organising maps [SOM]; Blind source separation
G06V 10/80 - Fusion, i.e. combining data from various sources at the sensor level, preprocessing level, feature extraction level or classification level
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
A clothes treating apparatus includes: a cabinet; a tub; a drum; a base forming an air flow path including an air inlet and an air outlet; a heat exchanger; a supply duct forming a first supply flow and a second supply flow path; a discharge duct forming a first discharge flow path and a second discharge flow path; a first damper configured to be movable to a first position of opening the first supply flow path and closing the second supply flow path or a second position of closing the first supply flow path and opening the second supply flow path; and a second damper configured to be movable to a third position of opening the first discharge flow path and closing the second discharge flow path or a fourth position of closing the first discharge flow path and opening the second discharge flow path.
D06F 58/20 - General details of domestic laundry dryers
D06F 25/00 - Washing machines with receptacles, e.g. perforated, having a rotary movement, e.g. oscillatory movement, the receptacle serving both for washing and for centrifugally separating water from the laundry and having further drying means, e.g. using hot a
D06F 29/00 - Combinations of a washing machine with other separate apparatus in a common frame or the like, e.g. with rinsing apparatus
A dishwasher including a tub including an opening; a door configured to open and close the opening; a first blower positioned at a first side of the tub; and a second blower positioned at a second side of the tub; wherein the first blower is configured to, while the door is positioned to open the opening, discharge a portion of air inside of the tub through the opening to outside of the tub so as to lower humidity inside of the tub, and the second blower is configured to, while the door is positioned to open the opening, circulate air inside of the tub that is not discharged by the first blower.
The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. Disclosed is a method of performing localisation of a User Equipment, UE, in a Non-Public Network, NPN, wherein the NPN, utilises an at least partially coextensive Public Land Mobile Network, PLMN, with which the UE is registered, to perform the localisation.
An image sensor including a substrate, at least one transfer gate on a top surface of the substrate, a floating diffusion region located in the substrate and disposed apart from the at least one transfer gate in a first direction, the first direction being parallel to the top surface of the substrate, an intrinsic semiconductor region located in the substrate and disposed between the at least one transfer gate and the floating diffusion region in the first direction, and a photoelectric conversion region located in the substrate and disposed apart from the floating diffusion region in a second direction, wherein the second direction is perpendicular to the first direction, and wherein the intrinsic semiconductor region is an undoped region.
A semiconductor memory device includes a cell substrate, a plurality of gate electrodes sequentially stacked on the cell substrate and extending in a first direction, first and second channel structures extending in a second direction different from the first direction and penetrating the plurality of gate electrodes, and a bit line disposed on the plurality of gate electrodes. The first and second channel structures each include a ferroelectric layer, a channel layer, a gate insulating layer and a back gate electrode, which are sequentially disposed on side walls of the plurality of gate electrodes. The first channel structure and the second channel structure are adjacent to each other in the first direction and share a bit line.
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
12.
ELECTRONIC DEVICE COMPRISING FRONTEND MODULE FOR COMMUNICATING THROUGH WIRELESS LAN
An electronic device includes a wireless communication circuit for a wireless LAN, a first frontend module connected to the wireless communication circuit, a second frontend module connected to the wireless communication circuit, a first antenna connected to the first frontend module, a second antenna connected to the second frontend module, a third antenna connected to the second frontend module, and a processor. The processor is configured to provide a first signal in 5 GHz band or 6 GHz band to the first frontend module. The processor is configured to set a first operation mode of the first operation mode for transmitting a signal related to wireless LAN, and a second operation mode, and the processor is configured to set to provide a second signal in the 5 GHz band or the 6 GHz band to the second frontend module while the first signal is provided to the first frontend module.
An electronic device includes: a plurality of image sensors including a first image sensor and a second image sensor; a processor; a display connected to the processor; and memory storing instructions being executable by the processor, which cause the electronic device to at least: execute a camera application; activate all of the plurality of image sensors, based on at least one of a specified event executed through the camera application, determine a first image sensor among the plurality of image sensors as an image sensor outputting image data to be displayed on the display, set a resolution of first image data acquired through the first image sensor as a first resolution, and in response to the determination, set a resolution of second image data acquired through a second image sensor among the plurality of image sensors as a second resolution lower than the first resolution.
H04N 23/80 - Camera processing pipelines; Components thereof
H04N 23/45 - Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
An electronic device is provided. The electronic device includes a first housing structure, a second housing structure, a hinge structure rotatably connecting the first housing structure and the second housing structure and including a first hinge plate and a second hinge plate, a hinge cover covering at least part of the hinge structure when the hinge structure is viewed from the outside, and a flexible printed circuit board crossing the hinge structure and extending from an inside of the first housing structure to an inside of the second housing structure and including a pair of fixing members to permit deformation of the flexible printed circuit board in the internal space of the hinge cover, wherein the hinge structure includes a first member attached to the first hinge plate, and a second member attached to the second hinge plate, and wherein the first member and the second member are disposed to face the flexible printed circuit board so as to prevent direct contact between the hinge structure and the printed circuit board during folding and/or unfolding of the electronic device.
A test device includes a memory and a controller. The memory stores reference data including a reference image obtained by photographing a reference pattern on a first semiconductor sample, a first height of the reference pattern, a first shadow length of the reference pattern, and a reference value that represents a correlation between the first height and the first shadow length. The controller receives an image obtained by photographing a pattern on a second semiconductor sample, measures a second shadow length of the pattern from the image, and calculates a second height of the pattern from the second shadow length based on the reference data.
The system includes a voice assistant receiving a voice command as input from user. The speech to text convertor converts the voice command into a text. A feature extractor extracts acoustic features from raw waveform of voice command and textual features from converted text for determining nearby context tokens. A multi modal unified attention sequence tagger determines a connection between the audio and the text based on an individual contextual embedding and a fused contextual embedding at context tokens level. It further tags replacement, cue and correction words sequentially based on determined connection between the audio and the text. An on-the-fly decoder decodes revised text on-the-fly based on tagged replacement, cue and correction words, to display the decoded revised text on user interface and sends the decoded revised text to NLP to generate a response corresponding to the input speech.
An operating method of a wireless communication device includes receiving a reference signal from a base station, estimating a first channel between the wireless communication device and the base station based on the reference signal, extracting, based on a first artificial intelligence model trained to reduce a difference between the first channel estimated by the wireless communication device and a second channel estimated by the base station, a feature including grouped attributes from the first channel, quantizing the grouped attributes using a codebook that is based on a second artificial intelligence model and by generating one or more indices of the codebook for each group of the attributes, and transmitting, to the base station, a bitstream including combination information of the indices of the codebook.
An electronic device includes a communication circuit, a speaker, and a processor. The processor is configured to identify a bitrate of a first audio bitstream received via the communication circuit from an external electronic device. The processor is configured to obtain, in response to the bitrate lower than a reference value, an audio signal by executing a bandwidth extension (BWE) for the first audio bitstream based on at least one coding parameter obtained from a second audio bitstream previously received via the communication circuit from the external electronic device before the first audio bitstream. The processor is configured to obtain, in response to the bitrate higher than or equal to the reference value, the audio signal for the first audio bitstream without executing the BWE. The processor is configured to output, based on the audio signal, audio via the speaker.
G10L 19/02 - Speech or audio signal analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using spectral analysis, e.g. transform vocoders or subband vocoders
G10L 19/032 - Quantisation or dequantisation of spectral components
19.
APPARATUS AND METHOD WITH HOMOMORPHIC ENCRYPTION OPERATION
An apparatus with a homomorphic encryption operation includes: one or more processors configured to: generate a modified vector by preprocessing vector components of an operand ciphertext of a blind rotation operation based on an order of a polynomial of an output ciphertext of the blind rotation operation and a modulus of the operand ciphertext; and generate a homomorphic encryption operation result by performing the blind rotation operation based on a public key for performing the blind rotation operation and the modified vector.
H04L 9/00 - Arrangements for secret or secure communications; Network security protocols
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
A semiconductor measurement apparatus includes an illuminator configured to output light having a first wavelength band and light having a second wavelength band, different from the first wavelength band, a stage on which a test object is positioned, a camera configured to receive light reflected or scattered from the test object or transmitted through the test object, and a controller configured to control the illuminator and the camera, and to measure, based on information indicated by the light received by the camera, a plurality of structures included in the test object. The controller is configured to set an exposure time of the camera to a first exposure time while the illuminator outputs the light having the first wavelength band, and to set the exposure time of the camera to a second exposure time, different from the first exposure time, while the illuminator outputs the light having the second wavelength band.
Provided is a semiconductor device that includes a plurality of ports and a PCIe controller. The PCIe controller includes: a link training and status state machine (LTSSM) configured to perform a link-up by configuring a plurality of lanes on the plurality of ports, and a memory storing a first preset as a reference value, the first preset being configured based on a successful link-up performed by the LTSSM. The PCIe controller is configured to perform a verification of a second preset that is configured by the LTSSM based on the reference value, to determine whether the second preset is valid.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
22.
ELECTRONIC DEVICE FOR DETERMINING LOCATION INFORMATION OF EXTERNAL ELECTRONIC DEVICE, AND OPERATING METHOD THEREOF
An electronic device for controlling devices includes: a communication module configured to communicate with the devices; a memory configured to store computer-executable instructions; and at least one processor. The at least one processor when executing the instructions by accessing the memory is configured to: determine a target device of which an envelope is to be registered among the devices, determine a first control area for the target device based on (i) first coordinates of a location of the electronic device in a preset coordinate system, (ii) a first direction from the first coordinates to the target device, and (iii) a field of view (FoV) for the target device, determine a second control area for the target device, and register an overlap area as the envelope for the target device, the overlap area being where the first control area and the second control area overlap.
A depth sensor includes a substrate that includes a first face and a second face opposite to each other in a first direction; a photoelectric conversion element disposed in the substrate; and first and second taps connected to the photoelectric conversion element. Each of the first and second taps includes: a floating diffusion area disposed in the substrate; a transfer transistor connected to the floating diffusion area; a photo transistor connected to the photoelectric conversion element; a tap transfer transistor connected to the photo transistor; and a storage transistor connected to the tap transfer transistor and the transfer transistor. The storage transistor includes a storage gate electrode. The storage gate electrode includes a first extension and a second extension that extend from the first face of the substrate toward the second face, and the first extension and the second extension are spaced apart from each other in a second direction.
Provided is an image decoding method including: determining a first coding block and a second coding block corresponding to the first coding block; when a size of the first coding block is equal to or smaller than a preset size, obtaining first split shape mode information and second split shape mode information from a bitstream; determining a split mode of the first coding block, based on the first split shape mode information, and determining a split mode of the second coding block, based on the second split shape mode information; and decoding a coding block of a first color component which is determined based on the split mode of the first coding block and a coding block of a second color component which is determined based on the split mode of the second coding block.
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/103 - Selection of coding mode or of prediction mode
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/184 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/60 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
25.
HOME APPLIANCE, AND METHOD FOR OUTPUTTING INFORMATION ABOUT HOME APPLIANCE
A method, for outputting information related to a second home appliance. The method includes: obtaining group information for grouping the first home appliance and the second home appliance by assigning the first home appliance as an assistant device and assigning the second home appliance as an actually used device; activating a group mode for operating the first home appliance as an assistant device of the second home appliance, based on the group information; controlling a communication interface to receive information related to operations of the second home appliance from the second home appliance assigned as the actually used device, through a communication channel established based on communication connection information of the second home appliance, the communication channel to connect to the second home appliance; and outputting the information related to the operations of the second home appliance through a first user interface, while the group mode is activated.
An electronic apparatus and a control method thereof are provided. The electronic apparatus includes a communication interface configured to receive content comprising image data and speech data; a memory configured to store a language contextual model trained with relevance between words; a display; and a processor configured to: extract an object and a character included in the image data, identify an object name of the object and the character, generate a bias keyword list comprising an image-related word that is associated with the image data, based on the identified object name and the identified character, convert the speech data to a text based on the bias keyword list and the language contextual model, and control the display to display the text that is converted from the speech data, as a caption.
A method of controlling a wearable device worn on a finger of a user, includes: sensing a contact by a second finger of the user via an outer surface electrode located on an outer circumferential surface of the wearable device worn on a first finger of the user; based on the sensing of the contact, measuring an impedance between the outer surface electrode and an inner surface electrode that is in contact with the first finger of the user; identifying a type of the second finger based on the impedance; and controlling an operation of the wearable device based on the type of the second finger.
The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Methods and apparatuses in provided in which a session description protocol (SDP) offer including a list of artificial intelligence (AI) models is received from a media resource function (MRF) entity. At least one AI model is identified from the list for outputting at least one result using first media data, based on a type of the first media data and a media service in which the at least one result is used. An SDP response is transmitted to the MRF entity, requesting the at least one AI model as a response to the SDP offer, and the first media data is processed based on the at least one AI model received from the MRF entity.
H04W 24/02 - Arrangements for optimising operational condition
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
29.
SEMICONDUCTOR DEVICE, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
30.
ELECTRONIC DEVICE AND METHOD FOR INDICATING NON-SCHEDULING LAYER IN FRONTHAUL INTERFACE
A radio unit (RU) is provided. The RU includes memory storing instructions, one or more transceivers configured to transmit signals or receive signals on a fronthaul interface, and one or more processors. Wherein the instructions cause, when executed by the one or more processors, the RU to receive, from a distributed unit (DU), a control plane (C-plane) message including section information for user equipment (UE) scheduling information and section extension information for a group configuration of multiple ports, wherein the section information including information on a resource region of a section description and a UE identifier, and the section extension information including information on a beam group type, information on the number of one or more ports indicated by the section extension information, and a UE identifier per port, and, in case that a UE identifier of a specified port is set to 0x7FFF in the C-plane message, identify that the resource region is not allocated for the specified port.
An electronic apparatus comprises a memory configured to store identification information of a content providing apparatus; a display; and at least one processor configured to: control the display to display a first content received from the content providing apparatus, based on a determination that a predetermined event has occurred, transmit the identification information of the content providing apparatus to the server, receive, from the server, user interface (UI) location information corresponding to the identification information, based on reception of a user instruction for changing the displayed first content to a second content, control the display to display the second content, and acquire content information corresponding to the second content based on the received UI location information, wherein the UI location information is acquired from a combined image that includes a plurality of images overlapped and merged into the combined image.
A memory device may include word line patterns stacked on a substrate and spaced from each other in a vertical direction, a channel structure extending in the vertical direction, and first contact plugs and second contact plugs extending in the vertical direction. The substrate may include a cell area, a cell wiring area, and a through-hole wiring area. The word line patterns may be on the cell area and the cell wiring area and may extend to the cell wiring area in a direction parallel to an upper surface of the substrate. The first contact plugs may be on the cell wiring area and each may be electrically connected with a corresponding one of the word line patterns and insulated from remaining word line patterns other than the corresponding one of the word line patterns. The second contact plugs may be on the through-hole wiring area.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor package includes semiconductor structures stacked in a stepwise manner. Each of the semiconductor structures may include a lower structure, an upper structure on the lower structure, and an insulating layer provided on a bottom surface of the upper structure to be in contact with at least a portion of side surfaces of the lower structure. An area of the lower structure may be smaller than an area of the upper structure, when viewed in a plan view, and a side surface of the insulating layer may be vertically aligned to a side surface of the upper structure.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A semiconductor memory device includes a substrate, a bit line on the substrate, word lines provided on the bit line and spaced apart in a first direction parallel to a top surface of the substrate, a back gate electrode provide between a pair of adjacent word lines among the word lines, active patterns provided between the back gate electrode and the pair of adjacent word lines, contact patterns respectively provided on the active patterns, a first back gate insulating pattern provided between the bit line and the back gate electrode, and a second back gate insulating pattern and a third back gate insulating pattern which are provided on the back gate electrode, where the back gate upper insulating pattern includes a material having a first dielectric constant and the back gate lower insulating pattern includes a material having a second dielectric constant that is greater than the first dielectric constant.
SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION (Republic of Korea)
Inventor
Jung, Geonwoong
Shim, Byonghyo
Kim, Hyunsoo
Byun, Yongsuk
Abstract
The present disclosure relates to a method and device for communication by a base station in a wireless communication system supporting multiple reconfigurable intelligent surface (RIS) devices. According to an embodiment A method for operating a base station, the method comprises selecting at least two reference reconfigurable intelligent surface (RIS) devices for estimating a position of a user equipment (UE) from among a plurality of RIS devices, estimating position information about the UE using the selected at least two reference RIS devices, receiving an uplink pilot signal of the UE through the selected at least two reference RIS devices; and estimating a multi-RIS channel for the plurality of RIS devices based on the uplink pilot signal of the UE and the estimated position information about the UE.
G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinations; Position-fixing by co-ordinating two or more distance determinations using radio waves
H04B 7/04 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
36.
LIGHT-EMITTING DEVICE AND ELECTRONIC APPARATUS INCLUDING THE LIGHT-EMITTING DEVICE
A light-emitting device including a first electrode, a second electrode opposing the first electrode, and an interlayer located between the first electrode and the second electrode, wherein the interlayer includes an emission layer, wherein the emission layer includes m1 dopants and m2 hosts, and m1 and m2 are each 1 or greater, when m1 is 2 or greater, then two or more of the dopants are different from each other, when m2 is 2 or greater, then two or more of the hosts are different from each other, and the light-emitting device satisfies Condition 1:
A light-emitting device including a first electrode, a second electrode opposing the first electrode, and an interlayer located between the first electrode and the second electrode, wherein the interlayer includes an emission layer, wherein the emission layer includes m1 dopants and m2 hosts, and m1 and m2 are each 1 or greater, when m1 is 2 or greater, then two or more of the dopants are different from each other, when m2 is 2 or greater, then two or more of the hosts are different from each other, and the light-emitting device satisfies Condition 1:
0 debye·V≤DMEML×(Vop−Vinj)≤3.41 debye·V Condition 1
A light-emitting device including a first electrode, a second electrode opposing the first electrode, and an interlayer located between the first electrode and the second electrode, wherein the interlayer includes an emission layer, wherein the emission layer includes m1 dopants and m2 hosts, and m1 and m2 are each 1 or greater, when m1 is 2 or greater, then two or more of the dopants are different from each other, when m2 is 2 or greater, then two or more of the hosts are different from each other, and the light-emitting device satisfies Condition 1:
0 debye·V≤DMEML×(Vop−Vinj)≤3.41 debye·V Condition 1
wherein Condition 1 may be understood by referring to the description provided herein.
An electronic device and/or a wearable device providing an exercise program, and/or a control method thereof are provided. The electronic device may include a communication module configured to communicate with the wearable device. The electronic device may include at least one processor. The processor may provide a first exercise program of a first exercise period according to an initial exercise intensity range to a user wearing the wearable device. The processor may measure a first posture score of the user while the user is performing the first exercise program. The processor may compare the first posture score to a posture boundary value. The processor may set a personal exercise intensity range of the user based on a result of the comparing. The processor may provide a second exercise program of a second exercise period according to the personal exercise intensity range.
A method of detecting clusters of defects includes measuring each of a plurality of wafers to obtain a plurality of wafer level maps of a plurality of wafer measurement points, creating a composite wafer level map by combining the plurality of wafer level maps, dividing the composite wafer level map into a plurality of grid areas, obtaining a plurality of target grid areas from the plurality of grid areas using unique values of the plurality of grid areas, grouping the plurality of target grid areas into a plurality of target grid clusters corresponding to the clusters of defects, and obtaining a detection priority for each of the plurality of target grid clusters based on the unique value of the plurality of target grid areas included in the plurality of target grid clusters.
The disclosure relates to a 5G or 6G communication system to support a higher data transmission rate. The disclosure relates to a reconfigurable intelligent surface (RIS) enabling a low phase error at various incidence angles/reflection angles and an apparatus including the same. The RIS comprises a unit cell pattern formed in a direction corresponding to a polarization direction, the unit cell configured to adjust a reflection phase; a switch operably connected to the unit cell pattern, the switch configured to adjust the reflection phase; and a dummy pattern positioned between unit cell patterns in case that a plurality of unit cells is arranged.
A method and a system for classifying one or more hyperlinks in a document are provided. The method includes identifying the one or more hyperlinks in the document based on an analysis of text strings of the document. The method further includes analyzing surrounding text strings around each of the one or more hyperlinks and classifying, based on the analysis of the surrounding text strings around each of the one or more hyperlinks, the one or more hyperlinks into at least one category among a plurality of predetermined categories.
Provided are a polymer, a resist composition including the same, and a method of forming a pattern using the resist composition, the polymer including one or more of a first repeating unit represented by Formula 1 and a second repeating unit represented by Formula 2, and free of a repeating unit of which a structure changes by an acid:
Provided are a polymer, a resist composition including the same, and a method of forming a pattern using the resist composition, the polymer including one or more of a first repeating unit represented by Formula 1 and a second repeating unit represented by Formula 2, and free of a repeating unit of which a structure changes by an acid:
Provided are a polymer, a resist composition including the same, and a method of forming a pattern using the resist composition, the polymer including one or more of a first repeating unit represented by Formula 1 and a second repeating unit represented by Formula 2, and free of a repeating unit of which a structure changes by an acid:
In Formulae 1 and 2, R11 to R16, b12, X−, R21 to R24, b22, and Y are as described in the specification.
C08F 228/06 - Copolymers of compounds having one or more unsaturated aliphatic radicals, each having only one carbon-to-carbon double bond, and at least one being terminated by a bond to sulfur or by a heterocyclic ring containing sulfur by a heterocyclic ring containing sulfur
G03F 7/038 - Macromolecular compounds which are rendered insoluble or differentially wettable
A wireless audio device includes a memory including instructions; and a processor operatively connected to the memory and configured to execute the instructions to: detect an audio signal, determine, based on an analysis result of the audio signal, an operation mode of the wireless audio device to be one of a singing mode and a dialogue mode, and control an output signal of the wireless audio device according to the determined operation mode, wherein the dialogue mode is configured to output one or more ambient sounds included in the audio signal, and wherein the singing mode is configured to output one or more media sounds and the one or more ambient sounds included in the audio signal.
G10L 25/78 - Detection of presence or absence of voice signals
G10L 25/72 - Speech or voice analysis techniques not restricted to a single one of groups specially adapted for particular use for transmitting results of analysis
A wearable electronic device according to an embodiment may comprise a plurality of speakers, a plurality of vibration devices, and at least one processor. The at least one processor may be configured to identify a first object corresponding to a first sound and a position of the first object in a virtual space of VR content displayed through the display. The at least one processor may be configured to obtain a second sound corresponding to the movement of the first object based on the first sound and the position of the first object. The at least one processor may be configured to output the second sound through the plurality of speakers. The at least one processor may be configured to determine one or more vibration devices corresponding to the movement of the first object among the plurality of vibration devices. The at least one processor may be configured to control the one or more vibration devices to vibrate while the second sound is output through the plurality of speakers.
The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The disclosure provides a method and an apparatus for efficient event management using a secure element and a bundle installed therein.
POWER GENERATOR WITH PARTIAL SINUSOIDAL WAVEFORM, PLASMA PROCESSING APPARATUS INCLUDING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
A power generator with partial sinusoidal waveform includes a resonance module circuit and a pulse module circuit. The resonance module circuit includes a plurality of resonance control switches, and generates a first output voltage by selectively turning on and off the plurality of resonance control switches based on a plurality of resonance control signals. The pulse module circuit includes a plurality of pulse control switches, and generates a second output voltage by selectively turning on and off the plurality of pulse control switches based on a plurality of pulse control signals. The power generator generates a bias power based on the plurality of resonance control signals, the plurality of pulse control signals, the first output voltage and the second output voltage. The bias power has a non-sinusoidal voltage waveform during an entire time interval and a sinusoidal voltage waveform during a partial time interval.
H02M 7/539 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
H01J 37/24 - Circuit arrangements not adapted to a particular application of the tube and not otherwise provided for
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 7/48 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
46.
ELECTRONIC DEVICE AND METHOD OF OPERATING THE ELECTRONIC DEVICE
An electronic device for executing a service and an application suitable for a nearby Internet-of-Things (IoT) device paired with the electronic device by using a short-range communication method, based on the performance and state of the IoT device, and a method of operating the electronic device are provided. The first electronic device includes receiving, from a second electronic device, information about the second electronic device including identification information of the second electronic device, information about a communication protocol available in the second electronic device, and information about a wireless communication method available in the second electronic device, and based on the information about the second electronic device, determining at least one application executable by the second electronic device.
H04W 4/70 - Services for machine-to-machine communication [M2M] or machine type communication [MTC]
G06F 3/0488 - Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser using a touch-screen or digitiser, e.g. input of commands through traced gestures
H01Q 5/25 - Ultra-wideband [UWB] systems, e.g. multiple resonance systems; Pulse systems
47.
METHODS OF TESTING NONVOLATILE MEMORY DEVICES AND NONVOLATILE MEMORY DEVICES
In a method of testing a nonvolatile memory device including a first semiconductor layer in which and a second semiconductor layer formed prior to the first semiconductor layer, circuit elements including a page buffer circuit and at least one driver spaced apart from the page buffer circuit are provided in the second semiconductor layer, an on-state of nonvolatile memory cells which are not connected to the page buffer circuit is mimicked by providing at least one discharging path between a sensing node and a plurality of discharge transistors of the at least one driver, a sensing and latching operation with the on-state being mimicked is performed in the page buffer circuit and whether the page buffer circuit operates normally is determined based on a result of the sensing and latching operation.
An electronic device is provided. The electronic device includes a housing, a support plate comprising a body, a first support substantially protruding from the body in a first direction, and a second support spaced apart from the first support and substantially protruding from the body in the first direction, the support plate disposed in the housing, a flexible printed circuit board comprising a first part, at least a portion of which is disposed between the first support and the second support, and a second part extending from the first part disposed on the body of the support plate such that the first part is vertically disposed with respect to the second part, wherein at least one first conductive member is disposed at the first part, and at least one second conductive member is disposed at the second part.
H01Q 3/12 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system using mechanical relative movement between primary active elements and secondary devices of antennas or antenna systems
H01Q 1/24 - Supports; Mounting means by structural association with other equipment or articles with receiving set
A communication method and system for converging a fifth generation (5G) communication system for supporting higher data rates beyond a fourth generation (4G) system with a technology for Internet of things (IoT) are provided. The communication method and system may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method for performing a random access procedure in a wireless communication system is provided.
An organometallic compound represented by Formula 1:
An organometallic compound represented by Formula 1:
M1(L1)n1(L2)n2 Formula 1
An organometallic compound represented by Formula 1:
M1(L1)n1(L2)n2 Formula 1
wherein, M1 is a transition metal, L1 is a ligand represented by Formula 1A, L2 is a ligand represented by Formula 1B, and n1 and n2 are each independently 1 or 2,
An organometallic compound represented by Formula 1:
M1(L1)n1(L2)n2 Formula 1
wherein, M1 is a transition metal, L1 is a ligand represented by Formula 1A, L2 is a ligand represented by Formula 1B, and n1 and n2 are each independently 1 or 2,
An organometallic compound represented by Formula 1:
M1(L1)n1(L2)n2 Formula 1
wherein, M1 is a transition metal, L1 is a ligand represented by Formula 1A, L2 is a ligand represented by Formula 1B, and n1 and n2 are each independently 1 or 2,
wherein X1 is C or N, X2 is C or N, at least one R2 is a C1-C10 alkyl group that is substituted with a fluorine, b1 is an integer from 1 to 6, b2 is an integer from 1 to 10, * and *′ each indicate a binding site to M1, and the other substituent groups of Formulae 1A and 1B are as described herein.
An integrated circuit (IC) device is provided. The IC device includes: a substrate having active regions; word lines extending in a first horizontal direction across the active regions; conductive expanded pads on the substrate and connected to the active regions; pad isolation structures located between the conductive expanded pads; direct contacts connected to the active regions; bit lines extending in a second horizontal direction perpendicular to the first horizontal direction, on the direct contacts and the pad isolation structures, and connected to the direct contacts; conductive plugs extending in a vertical direction on the conductive expanded pads and connected to the conductive expanded pads; and separation fences passing through the conductive expanded pads and the conductive plugs, and having sidewalls extending linearly in the vertical direction.
An embodiment provides a test element group (TEG) circuit, including: a first pad configured for a test voltage to be applied; an amplifier including a first input terminal connected to the first pad, a second input terminal connected to a first terminal of a test transistor, and an output terminal electrically connected to the second input terminal; a variable resistor including one terminal connected to the output terminal of the amplifier and the other terminal connected to the first terminal of the test transistor; and a gate driving circuit that supplies a gate voltage to a gate of the test transistor.
Methods and apparatuses are provided in which a slot is generated including a symbol and a synchronization signal, which is transmitted through the symbol. The slot is transmitted to a reconfigurable intelligent surface (RIS) and a user equipment (UE). The symbol is used to determine an operation to be performed by the UE during a predetermined time period including the slot. The slot is transmitted to the UE through beams formed according to a first RIS pattern. A result of measuring each beam based on the beams is received from the UE. A second RIS pattern is determined for transmitting data based on the result of measuring each beam. A signal for controlling the first RIS pattern based on the second RIS pattern is transmitted to the RIS. A data signal is transmitted to the UE through the RIS. The second RIS pattern is applied to the RIS.
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
An apparatus monitoring semiconductor manufacturing equipment includes; an optical detector, a light generator generating light along a first optical path towards a semiconductor substrate, wherein upon irradiating the semiconductor substrate, the light becomes reflected light along a second optical path away from the semiconductor substrate and towards the optical detector, a first grating reticle between the light generator and the semiconductor substrate and including first slits having a first pitch and second slits having a second pitch different from the first pitch, a second grating reticle between the semiconductor substrate and the optical detector and including third slits having a third pitch different from the first pitch and the second pitch, wherein the optical detector determines a positional attribute of the semiconductor substrate in relation to a first pattern and a second pattern, the first pattern corresponds to a first portion of light/reflected light sequentially passing through the first slits and the third slits, and the second pattern corresponds to a second portion of light/reflected light sequentially passing through the second slits and the third slits.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
55.
DECODING DEVICE AND DECODING METHOD USING LOW-DENSITY PARITY CHECK CODE INCLUDING CODE DIFFERENT FROM SINGLE PARITY CHECK CODE
A decoding device and a decoding method which relate to: receiving a codeword; estimating a number of errors included in the received codeword; and decoding the codeword based on the estimated number of errors using at least one of a first parity check matrix and a second parity check matrix, wherein the first parity check matrix corresponds to a first low-density parity check (LDPC) code, and the second parity check matrix corresponds to a second LDPC code, and wherein the first parity check matrix is based on a first code type, and the second parity check matrix is based on a second code type different from the first code type.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
A memory device includes a memory cell array having a plurality of word lines and a plurality of common source lines therein, which constitute a row. A refresh manager is provided, which is configured to perform a refresh operation for the memory cell array. The refresh manager is further configured to: (i) initialize a count for the row of the memory cell array, (ii) transmit a refresh command to the memory cell array, (iii) write first data into the row when the refresh operation for the memory cell array is a normal refresh operation, and (iv) write second data into a row associated with a word line adjacent to a word line in which row hammering has occurred, when the refresh operation for the memory cell array is not a normal refresh operation.
A clothes treating apparatus including a housing; a tub inside the housing; a drum configured to be rotated inside the tub; a spin-drying shaft connected to the drum; a motor assembly including a rotor configured to be rotated; a coupler: a first element; and a second element inside the coupler, wherein the coupler is positionable in a first position in which the coupler is coupled to the spin-drying shaft and the rotor, the coupler is positionable in a second position in which the coupler is coupled to the spin-drying shaft and disengaged from the rotor, and with the coupler being positioned in the second position, the first element and the second element are configured to interact to move the second element away from the first element and thereby move the coupler from the second position to the first position.
D06F 23/04 - Washing machines with receptacles, e.g. perforated, having a rotary movement, e.g. oscillatory movement, the receptacle serving both for washing and for centrifugally separating water from the laundry and rotating or oscillating about a vertical axis
D06F 37/20 - Mountings, e.g. resilient mountings, for the rotary receptacle, motor, tub or casing; Preventing or damping vibrations
D06F 37/24 - Mountings, e.g. resilient mountings, for the rotary receptacle, motor, tub or casing; Preventing or damping vibrations in machines with a receptacle rotating or oscillating about a vertical axis
H02K 7/116 - Structural association with clutches, brakes, gears, pulleys or mechanical starters with gears
H02K 21/22 - Synchronous motors having permanent magnets; Synchronous generators having permanent magnets with stationary armatures and rotating magnets with magnets rotating around the armatures, e.g. flywheel magnetos
H02K 49/10 - Dynamo-electric clutches; Dynamo-electric brakes of the permanent-magnet type
A semiconductor package includes a first redistribution structure, a first semiconductor chip disposed on an upper surface of the first redistribution structure, an encapsulant disposed between the first redistribution structure and the first semiconductor chip, a plurality of first conductive posts electrically connecting the first redistribution structure and the first semiconductor chip with each other, and penetrating through the encapsulant in a first direction, a heat dissipation member having at least a portion that overlaps the first semiconductor chip in a second direction that is perpendicular to the first direction, and a second semiconductor chip disposed between the first redistribution structure and the heat dissipation member, and encapsulated by the encapsulant. The first semiconductor chip overlaps the plurality of first conductive posts in the first direction. The first semiconductor chip does not overlap the second semiconductor chip in the first direction.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
59.
METHOD AND APPARATUS FOR PROCESSING SIGNAL IN WIRELESS COMMUNICATION SYSTEM
UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY (Republic of Korea)
Inventor
Seo, Bongsung
Kim, Kwangsoon
Kim, Jonghyun
Lee, Kwanghoon
Jin, Euiwhan
Abstract
The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate than 4G communication systems such as LTE systems. A method performed by a user equipment (UE) in a wireless communication system may comprise receiving a signal, converting the signal into a digital signal, receiving, from a base station, transmission spectrum information for the UE and information for a time window, estimating a timing skew and a reception signal-to-noise ratio (SNR) of the digital signal based on the information for the time window and the transmission spectrum information, and compensating for a distortion of the digital signal based on the estimated timing skew and the reception SNR.
The present disclosure provides plasma etching apparatuses and operating methods of the plasma etching apparatuses. In some embodiments, a plasma etching apparatus includes a processing chamber, a plasma source generator, a bias generator, and an acoustic wave generator. The processing chamber is configured to receive etching gas, and to etch a wafer using plasma that has been formed according to a plasma source pulse and a bias pulse. The a plasma source generator is configured to generate the plasma source pulse. The bias generator is configured to generate the bias pulse. The acoustic wave generator is configured to generate an acoustic wave having a wavefront with a first direction parallel to the wafer and to control a density of a reactive gas of the plasma.
The present disclosure discloses methods and systems for providing communication between a multiple subscriber identity module (SIM) user equipment (UE) and multiple networks. The method may comprise notifying at least one second SIM to hold decoding of paging data associated with a paging channel monitoring request, the at least one second SIM registered with at least one second network of the plurality of networks. The method may comprise receiving an indication associated with the paging channel monitoring request from the at least one second network. The method may comprise transmitting the indication associated with paging channel monitoring request, to a first SIM registered with a first network of the plurality of networks, the indication associated with the paging channel monitoring request meant for at least one second SIM and allowing the first SIM to instruct the at least one second SIM to resume decoding of the paging data.
Provided is a video decoding method including: obtaining a first motion vector indicating a first reference block of a current block in a first reference picture and a second motion vector indicating a second reference block of the current block in a second reference picture; obtaining a parameter related to pixel group unit motion compensation of the current block, based on at least one of information of the parameter related to the pixel group unit motion compensation and a parameter related to an image including the current picture; generating a prediction block by performing, with respect to the current block, block unit motion compensation based on the first motion vector and the second motion vector and performing the pixel group unit motion compensation based on the parameter related to the pixel group unit motion compensation; and reconstructing the current block. Here, a pixel group may include at least one pixel.
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/573 - Motion compensation with multiple frame prediction using two or more reference frames in a given prediction direction
A washing machine comprises a housing, a drum rotatably disposed inside the housing, a driving shaft configured to transfer a rotational force from a driving motor of the washing machine to the drum, and a driving shaft flange configured to connect the driving shaft to the drum. The driving shaft flange comprises a first surface, a second surface substantially parallel to the first surface, wherein the first surface and the second surface are spaced apart from each other by a predetermined distance in the vertical direction, and an extension portion formed perpendicular to the first surface and the second surface and connecting the first surface to the second surface. An edge of the first surface and an edge of the second surface and an edge of the extension portion are substantially aligned in vertical direction of the drum.
A semiconductor package includes; a semiconductor substrate including a device region and an edge region, a first redistribution layer on a lower surface of the semiconductor substrate, a second redistribution layer on an upper surface of the semiconductor substrate, through vias vertically penetrating the semiconductor substrate in the edge region to electrically connect the first redistribution layer and the second redistribution layer, and a circuit layer between the lower surface of the semiconductor substrate and the first redistribution layer. The circuit layer may include; a circuit element on the lower surface of the semiconductor substrate, a circuit wiring pattern electrically connected to the circuit element and the first redistribution layer, and a device interlayer dielectric layer substantially encompassing the circuit element and the circuit wiring pattern, wherein the circuit element and the circuit wiring pattern are disposed in the device region and not in the edge region.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
A semiconductor device includes a substrate having an active region; a bit line structure on the substrate and extending in one direction; a bit line contact electrically connecting a first impurity region of the active region and the bit line structure; and a storage node contact disposed on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, wherein the storage node contact includes a vertical extension portion extending in a vertical direction, perpendicular to an upper surface of the substrate, and a horizontal extension portion integrally connected to the vertical extension portion and extending in a horizontal direction, parallel to the upper surface of the substrate.
A three-dimensional semiconductor memory device may include a substrate, a stack including interlayer insulating layers and gate electrodes alternatingly stacked on the substrate, a dummy pad on a pad portion of each gate electrode, a source structure between the substrate and the stack, and first vertical channel structures that penetrate the stack and the source structure. The pad portions may include a first pad portion vertically overlapped with the dummy pad and a second pad portion horizontally overlapped with the dummy pad. The first and second pad portions may be spaced apart from the dummy pad, and one of the interlayer insulating layers may be interposed between the first pad portion and the dummy pad. The one of the interlayer insulating layers may extend continuously from a first portion to a second portion via a connection portion.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
67.
METHOD OF DATA RECOVERY AND STORAGE SYSTEM PERFORMING THE SAME
A storage system includes: an interconnector; a plurality of storage devices connected to the interconnector and configured to store data; a host device connected to the interconnector, and configured to: set a plurality of erasure coding schemes that are different from each other, and determine a target erasure coding scheme corresponding to original data to be stored in the plurality of storage devices among the plurality of erasure coding schemes, based on device characteristics of the plurality of storage devices or data characteristics of the original data; and an erasure coding controller configured to: divide the original data into a plurality of data blocks corresponding to the target erasure coding scheme, and generate one or more parity blocks corresponding to the target erasure coding scheme, by encoding the plurality of data blocks.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
68.
INTEGRATED CIRCUIT INCLUDING STANDARD CELL WITH A METAL LAYER HAVING A PATTERN AND METHOD OF MANUFACTURING THE SAME
An integrated circuit including a standard cell including: a metal layer including a pattern extending in a first horizontal direction and a plurality of tracks spaced apart from one another in a second horizontal direction, wherein the plurality of tracks include a plurality of cell tracks and one power distribution network (PDN) track, wherein cell patterns are formed on the plurality of cell tracks, and a PDN pattern or a routing pattern is formed on the one power distribution network (PDN) track, wherein a first pattern is spaced apart from a cell boundary of the standard cell by a first length and is formed on a first cell track among the plurality of cell tracks, and wherein a second pattern is spaced apart from a cell boundary of the standard cell by a second length and is formed on a second cell track among the plurality of cell tracks.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A hair dryer including a main body; a fan inside the main body to generate a flow of air; and a nozzle connected to the main body so that the air flows into the nozzle. The nozzle includes a nozzle body having an inner space, a nozzle partition wall inside the nozzle body dividing the inner space into first and second nozzle passages, a plurality of first nozzle holes formed in the nozzle body to communicate with the first nozzle passage, and a plurality of second nozzle holes formed in the nozzle body to communicate with the second nozzle passage. The nozzle is configured so that air flowing into the first nozzle passage is discharged through the first nozzle holes in a first direction, and air flowing into the second nozzle passage is discharged through the second nozzle holes in a second direction that is different from the first direction.
A module tray for a semiconductor device includes a base plate, first and second sidewalls extending in a vertical direction from opposite sides of the base plate to define an accommodation space, a dividing wall extending in the vertical direction from the base plate between the first and second sidewalls, first to fourth fastening guides with first to fourth fastening grooves, respectively, on inner surfaces of the first and second sidewalls and opposite side surfaces of the dividing wall, and first to fourth guide grooves on the inner surfaces of the first and second sidewalls and the opposite side surfaces of the dividing wall, respectively, the first to fourth guide grooves having curved concave shapes, and an upper end portion of each of the first to fourth fastening grooves gradually widening toward a top thereof.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
71.
REMOTE AUTHORIZATION METHOD AND ELECTRONIC DEVICE FOR PERFORMING SAME METHOD
A remote authorization method and an electronic device for performing the method are provided. The remote authorization method includes the steps of identifying information of a target device connected to a network, transmitting a request for remote login to the target device to an account server, in response to the remote login request, receiving, from the account server, a remote login code for identifying the remote login request and a remote login method determined according to the information of the target device, requesting a terminal authorization code from the target device by using the remote login code, receiving an input of the terminal authorization code, which is output by the target device according to the remote login method, from a user, transmitting the terminal authorization code to the account server, and receiving a login key for remote login of the target device from the account server, and transmitting the login key to the target device.
Methods for executing a user input in an IoT environment by at least one IoT device. The method may include receiving a user input from a user of the IoT device to execute at least one task associated with the IoT device. The method may include determining a multimodal context of the IoT environment relevant to the at least one task associated with the IoT device based on the received user input. The method may include retrieving multimodal data of the IoT environment corresponding to the determined multimodal context. The method may include determining a task execution intensity for the task associated with the IoT device based on the retrieved multimodal data. The method may include executing the task associated with the at least one IoT device using the determined task execution intensity.
A layout optimization system for correcting a target layout of a semiconductor process includes a deep reinforcement learning (DRL) module, a memory storing instructions, and a processor configured to execute the instructions to receive a target layout, generate, by the DRL module, a prediction layout by applying a simulation to the target layout, generate, by the DRL module, an optimal layout based on the prediction layout, and apply a size correction to at least one pattern of the prediction layout based on the optimal layout.
An electronic device is provided. The electronic device includes a housing, a display, a middle plate, an adhesive layer, a support layer, and a coating layer. The housing includes a front plate facing a direction, a rear plate facing an opposite direction, and a lateral member surrounding a space between the front and rear plate. The display is configured to be seen through the front plate, and includes a first and second surface. The middle plate is disposed between the display and the rear plate, and includes a surface facing the display, and a recess. The adhesive layer is attached to the display, and the support layer is disposed between the adhesive layer and the middle plate. The coating layer is disposed between the support layer and the adhesive layer and is disposed in a first portion overlapped with the recess when viewed from the display.
A method includes obtaining a 2D image captured using an imaging sensor. The 2D image is associated with an imaging sensor pose. The method also includes providing the 2D image, the imaging sensor pose, and one or more additional imaging sensor poses to at least one machine learning model that is trained to generate a texture map and a depth map for the imaging sensor pose and each additional imaging sensor pose. The method further includes generating a stereo image pair based on the texture maps and the depth maps. The stereo image pair represents a 2.5D view of the 2D image. The 2.5D view includes a pair of images each including multiple collections of pixels and, for each collection of pixels, a common depth associated with the pixels in the collection of pixels. In addition, the method includes initiating display of the stereo image pair on an XR device.
A semiconductor device includes an active region including a first portion and a second portion; an isolation region on a side surface of the active region; a plurality of active layers stacked and spaced apart from each other in a vertical direction on the first portion of the active region; an epitaxial structure disposed on the second portion of the active region, connected to the plurality of active layers, and overlapping the isolation region in the vertical direction; a gate structure extending by intersecting the active region and surrounding each of the plurality of active layers; and a gate spacer on a side surface of the gate structure. The epitaxial structure includes a blocking layer and a source/drain structure on the blocking layer. The blocking layer includes a plurality of active blocking portions contacting the plurality of active layers, respectively, and at least one first bent portion bent and extending from at least one of the plurality of active blocking portions and contacting the gate spacer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A semiconductor memory device comprises a substrate; a mold structure on the substrate; a plurality of channel structures extending in the mold structure; a source layer and a source sacrificial layer between the substrate and the mold structure, wherein the source sacrificial layer is spaced apart from the source layer; and a source support layer on the source layer and the source sacrificial layer, wherein the source support layer is between the source layer and the source sacrificial layer, wherein an upper surface of the source support layer includes first and second portions extending parallel to the substrate, and a third portion that connects the first and second portions, wherein a vertical distance from an upper surface of the source layer to the first portion is smaller than a vertical distance from an upper surface of the substrate to the second portion.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/528 - Layout of the interconnection structure
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A semiconductor device includes a substrate, an isolation layer defining an active region in the substrate, a word line extending in a first horizontal direction in a first area of the substrate, a bit line extending in a second horizontal direction perpendicular to the first horizontal direction, on the substrate, and a plurality of first dummy word lines provided in a second area of the substrate adjacent in the second horizontal direction to a first end portion of the first area in the first horizontal direction, the plurality of first dummy word lines extending in the first horizontal direction, wherein a length of each of the plurality of first dummy word lines in the first horizontal direction is less than a length of the word line in the first horizontal direction.
An integrated circuit includes a plurality of cells in a series of rows, wherein a first cell of the plurality of cells includes a plurality of logic circuits, each logic circuit of the plurality of logic circuits configured to independently generate an output bit signal according to input bit signals, a first input pin group including at least one input pin commonly connected to the plurality of logic circuits, a second input pin group including at least one input pin commonly connected to two or more logic circuits among the plurality of logic circuits, and a third input pin group including at least one input pin respectively connected exclusively to at least one of the plurality of logic circuits.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A low power flip-flop includes a master section including a multiplexer, a first AND-OR-Inverter (AOI) gate circuit, a second AOI gate circuit, and a first inverter circuit and configured to receive a data input signal, a scan input signal, a scan enable signal, and an inverted scan enable signal, and output a second internal signal and a third internal signal, a slave section including a third AOI gate circuit, a fourth AOI gate circuit, and a second inverter circuit, and configured to receive the second and third internal signals to output an output signal, and a third inverter circuit configured to generate the inverted scan enable signal. The first to fourth AOI gate circuits are configured to receive a clock signal.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
81.
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package includes a lower substrate including a lower interconnection layer; an upper substrate on the lower substrate, a recessed surface having a step difference, and an upper interconnection layer having a through-hole extending from the recessed surface to the first surface of the upper substrate and electrically connected to the lower interconnection layer; semiconductor chip between the recessed surface of the upper substrate and the lower substrate and including connection pads electrically connected to the lower interconnection layer; interconnect structure between the second surface of the upper substrate and the lower substrate and electrically connecting the lower interconnection layer to the upper interconnection layer; and an insulating member including a first portion covering at least a portion of the semiconductor chip and interconnect structure, a second portion extending from the first portion into the through-hole, and a third portion covering at least a portion of the first surface.
H01L 23/528 - Layout of the interconnection structure
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
82.
INTER-FLOOR TRANSPORT SYSTEM AND METHOD OF DRIVING THE SAME
An inter-floor transport system includes a first interface unit at a first floor and configured to receive containers from a transport vehicle, and a car configured to receive containers from the first interface unit at the first floor and move containers to a second floor, where the car includes a cage, a storage unit in the cage and including a plurality of storage areas, and an arrangement unit in the cage, the arrangement unit being configured to receive containers from the first interface unit and store containers in respective storage areas of the plurality of storage areas of the storage unit.
B65G 49/06 - Conveying systems characterised by their application for specified purposes not otherwise provided for for fragile or damageable materials or articles for fragile sheets, e.g. glass
A semiconductor device comprising: a lower insulating layer; a field insulating layer on the lower insulating layer; an upper insulating layer on the field insulating layer; a first through via in the upper insulating layer; a second through via in the field insulating layer; and a third through via in the lower insulating layer, wherein the second through via is connected to the first and third through vias, and wherein a width of a top surface of the second through via is greater than a width of a bottom surface of the first through via, a width of a bottom surface of the second through via is greater than a width of a top surface of the third through via, and a width of a middle portion of the second through via is greater than the widths of the top surface and the bottom surface of the second through via.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
Disclosed herein are a communication technique for merging, with an IoT technology, a 5G communication system for supporting a data transmission rate higher than that of a 4G system; and a system therefor.
Disclosed herein are a communication technique for merging, with an IoT technology, a 5G communication system for supporting a data transmission rate higher than that of a 4G system; and a system therefor.
Embodiments herein disclose a method of protecting sensitive user plane traffic in an User Equipment (UE) (100), the method comprising: transmitting, to a network (200), by the UE (100) a first NAS message comprising an indicator indicating that the UE (200) supports of a secure channel for domain name system (DNS); receiving, from the network (200), by the UE (100) a second NAS message including DNS server security information in response to transmitting the first NAS message; and transmitting, to the network (200), by the UE (100) the DNS over the secure channel based on the DNS server security information.
A solder reflow apparatus may include a reflow chamber, a heater and a stage. The reflow chamber may be configured to receive a heat transfer fluid. The heat transfer fluid may be configured for transferring heat to a solder for mounting an electronic part on a substrate. The heater may be configured to heat the heat transfer fluid in the reflow chamber. The stage may be in the reflow chamber to support the substrate. The stage may be inclined to a bottom surface of the reflow chamber to induce the heat transfer fluid toward a central portion of the substrate. Thus, the vertically ascended heat transfer fluid may be uniformly applied to the central portion and an edge portion of the substrate so that the solders at the central portion and the edge portion of the substrate may be uniformly soldered.
POSTECH Research and Business Development Foundation (Republic of Korea)
Inventor
Kim, Sunil
Rho, Junsuk
Yang, Younghwan
Park, Junghyun
Abstract
Provided is a spatial light modulator configured to modulate light, the spatial light modulator including a first reflective layer, a resonance layer on the first reflective layer, and a second reflective layer on the resonance layer, the second reflective layer including a plurality of grating structures space apart from each other, wherein the plurality of grating structures include silicon (Si) having an extinction coefficient k that is less than or equal to 1e-5 with respect to light in the predetermined wavelength band.
G01S 7/481 - Constructional features, e.g. arrangements of optical elements
G01S 17/08 - Systems determining position data of a target for measuring distance only
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference
A load port module includes: a mounting table configured to receive a container, wherein the container is configured to receive a substrate therein; a door opener is configured to open and close a door of the container; an image generator is on the door opener, and the image generator is configured to generate a first image of the substrate at a first angle with respect to the substrate, and a second image of the substrate at a second angle with respect to the substrate different from the first angle; and a controller is configured to determine warpage of the substrate based on the first image and to determine alignment of the substrate based on the second image.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
89.
DIFFERENTIAL SIGNALING CIRCUIT FOR CORRECTING FOR DUTY CHANGE DUE TO NBTI DEGRADATION, OPERATING METHOD THEREOF, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
A differential signaling circuit is provided. The differential signaling circuit includes: a differential amplifier configured to generate differential signals; a first signal path circuit; a second signal path circuit; a phase control circuit configured to receive the differential signals having a common phase, output DC signals having a common level in a first operating period, and transmit the differential signals to the first signal path circuit and the second signal path circuit, respectively, in a second operating period; and a duty ratio correction circuit connected between the first signal path circuit and the second signal path circuit, and configured to control duty ratios of the differential signals to be equal to each other in the second operating period.
In a backlight apparatus, a master driving circuit generates a transmission frame including a training period including a clock training pattern and a data period including a plurality of data packets respectively corresponding to the plurality of blocks. A plurality of slave driving circuits correspond to the plurality of blocks, respectively, and are connected to the master driving circuit in a daisy chain structure. Each slave driving circuit receives the transmission frame through the daisy chain structure, recovers a clock based on the clock training pattern, and drives the plurality of light emitting elements included in a corresponding block among the plurality of blocks based on its own data packet among a plurality of data packets.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
91.
SYSTEM AND METHOD FOR CONTINUOUS ATRIAL FIBRILLATION DETECTION VIA PPG TO ECG SIGNAL TRANSLATION
A system and a method are disclosed for AFib detection using ECG signals generated from monitored PPG signals. A method includes receiving PPG signals of a user measured by a PPG sensor; translating the measured PPG signals into ECG signals using a dynamic model; analyzing the translated ECG signals using an AFib detection model, which is trained on measured ECG signals for AFib detection; and providing the analyzed AFib detection results to the user.
A method of measuring a load current provided to a load of a switching converter includes obtaining a first reference voltage defining a peak of an inductor current passing through an inductor of the switching converter, generating a pulse based on the first reference voltage and an on-time of at least one power switch of the switching converter, generating an output signal by filtering the pulse, and setting a second mode from a first mode when a value of the load current is less than a first threshold value based on the output signal. The generating of the pulse further includes generating the pulse having a width extended in proportion to the on-time in the second mode.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
93.
SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
Disclosed are a semiconductor device and a method of fabricating the same. In the semiconductor device, a supporting pattern may be used to fix upper portions of active patterns, when a gap-filling process is performed to fill a region between active patterns, and thus, it may be possible to prevent or reduce the likelihood of the active patterns from being bent or fallen. Thus, it may be possible to reduce failure of the semiconductor device and/or to improve reliability of the semiconductor device.
An integrated circuit device includes a substrate having an active area therein, a bit line on the substrate, and a direct contact, which extends between the active area and the bit line and electrically couples the bit line to a portion of the active area. A spacer structure is also provided, which extends on sidewalls of the bit line and on sidewalls of the direct contact. Afield passivation layer is provided, which extends between the sidewalls of the direct contact and the spacer structure. The spacer structure and the field passivation layer may include different materials, and the field passivation layer may directly contact the sidewalls of the direct contact. The field passivation layer can include nonstoichiometric silicon oxide SiOx, where 0.04≤x≤0.4, and may have a thickness of less than about 25 Å.
The present disclosure relates to a ventilation apparatus including a housing including: an intake flow path provided to draw outdoor air into an indoor space and an discharge flow path provided to discharge indoor air to the outside, a cover covering the housing, a total heat exchanger configured to exchange heat between air flowing in the intake flow path and air flowing in the discharge flow path, and a dehumidification unit including a heat exchanger provided on the intake flow path configured to remove moisture in the air flowing in the intake flow path and a drain tray configured to collect condensate generated from the heat exchanger, wherein the housing includes a first housing including a first hole asymmetrically formed on one surface of the housing with respect to a center line of the one surface extending in a long axis direction and a short axis direction of the one surface and configured to allow the drain tray and the total heat exchanger to be withdrawn from the outside of the housing, and a second housing coupled to the first housing in an up-down direction and including a second hole disposed on an other surface of the housing and having a shape corresponding to the first hole in the up-down direction, wherein the cover includes a first cover forming a lower portion of the cover and a second cover coupled to the first cover in the up-down direction and forming an upper portion of the cover, and wherein one of the first housing and the second housing is covered by the first cover, and an other one of the first housing and the second housing is covered by the second cover.
F24F 3/147 - Air-conditioning systems in which conditioned primary air is supplied from one or more central stations to distributing units in the rooms or spaces where it may receive secondary treatment; Apparatus specially designed for such systems characterised by the treatment of the air otherwise than by heating and cooling by dehumidification with both heat and humidity transfer between supplied and exhausted air
B01D 46/00 - Filters or filtering processes specially modified for separating dispersed particles from gases or vapours
B01D 46/42 - Auxiliary equipment or operation thereof
F24F 8/108 - Treatment, e.g. purification, of air supplied to human living or working spaces otherwise than by heating, cooling, humidifying or drying by separation, e.g. by filtering using dry filter elements
F24F 12/00 - Use of energy recovery systems in air conditioning, ventilation or screening
96.
PORTABLE COMMUNICATION DEVICE INCLUDING SEALING MEMBER
A portable communication device or electronic device is provided. The communication device includes a housing including a first housing structure, a second housing structure, and a hinge cover positioned between at least a portion of the first housing structure and at least a portion of the second housing structure, a flexible display at least partially received in the housing and including a first portion corresponding to the first housing structure, a second portion corresponding to the second housing structure, and a third portion corresponding to the hinge cover, a hinge structure positioned between the third portion of the flexible display and the hinge cover and connected with the first housing structure and the second housing structure, and at least one sealing member positioned between the third portion of the flexible display and the hinge cover and contacting the hinge cover.
A vertical nonvolatile memory device may include a peripheral circuit portion including a memory cell driving circuit and connection wiring; a first hydrogen diffusion barrier layer above the peripheral circuit portion; a first insulating layer above the first hydrogen diffusion barrier layer; a common source line layer above the first insulating layer; a second hydrogen diffusion barrier layer above the first insulating layer; and a memory cell stack structure above the common source line layer and the second hydrogen diffusion barrier layer.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/528 - Layout of the interconnection structure
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
98.
NON-VOLATILE MEMORY DEVICE, METHOD FOR MANUFACTURING THE NON-VOLATILE MEMORY DEVICE, AND ELECTRONIC SYSTEM INCLUDING THE NON-VOLATILE MEMORY DEVICE
A non-volatile memory device including a substrate including a first area and a second area, a mold structure on the substrate, the mold structure including gate electrodes and mold insulating films alternately stacked on each other in a stepwise manner, an interlayer insulating film covering the mold structure, a channel structure on the first area, the channel structure extending through the mold structure and connected to the gate electrodes, and a through-contact on the second area and extending through the interlayer insulating film, the through-contact including a first portion in a first trench and a second portion in a second trench, the first portion including a liner film along a sidewall and a bottom surface of the first trench and a filling film on the liner film, wherein the filling film being a multi-grain conductive material, and the second portion being a single grain conductive material, may be provided.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
99.
GROUND-CONNECTED SUPPORTS WITH INSULARING SPACERS FOR SEMICONDUCTORMEMORY CAPACTITORS AND METHOD OF FABRICATING THE SAME
A semiconductor device may comprise: a plurality of lower electrodes which are on a substrate; a first electrode support which is between adjacent lower electrodes and comprises a metallic material; a dielectric layer which is on the lower electrodes and the first electrode support to extend along profiles of the first electrode support and each of the lower electrodes; and an upper electrode which is on the dielectric layer.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 5/10 - Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
G11C 11/402 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
100.
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
