Lam Research Corporation

United States of America

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H01J 37/32 - Gas-filled discharge tubes 448
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components 435
H01L 21/3065 - Plasma etching; Reactive-ion etching 286
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 277
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber 228
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1.

INHIBITED OXIDE DEPOSITION FOR REFILLING SHALLOW TRENCH ISOLATION

      
Application Number US2023073760
Publication Number 2024/081473
Status In Force
Filing Date 2023-09-08
Publication Date 2024-04-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Baker, Jonathan Grant
  • Agarwal, Pulkit
  • Agnew, Douglas Walter
  • Petraglia, Jennifer Leigh
  • Park, Dae-Jin
  • Fellis, Aaron

Abstract

Examples are disclosed relate to using an inhibitor with a silicon oxide ALD deposition process to refill recesses in STI regions. One example provides a method of processing a substrate. The method comprises depositing an inhibitor on the substrate, wherein a concentration of the inhibitor on a gate structure of the substrate is greater relative to the concentration of the inhibitor on a recessed shallow trench isolation (STI) region of the substrate. The method further comprises depositing a layer of silicon oxide on the substrate, the inhibitor inhibiting growth of the layer of silicon oxide such that the layer of silicon oxide is thicker on the recessed STI region and thinner on the gate structure.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/762 - Dielectric regions
  • H01J 37/32 - Gas-filled discharge tubes

2.

OXYMETHYLENE COPOLYMERS FOR TRANSIENT SURFACE PROTECTION DURING CHEMICAL VAPOR DEPOSITION

      
Application Number US2023034707
Publication Number 2024/081174
Status In Force
Filing Date 2023-10-06
Publication Date 2024-04-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Chen, Zhengtao
  • Blachut, Gregory
  • Phillips, Oluwadamilola Sanyaolu
  • Hymes, Diane

Abstract

The present disclosure relates to methods for protecting semiconductor substrate surfaces by coating the surfaces with a stimulus responsive polymer layer, the stimulus responsive polymer layer composed of copolymers with oxymethylene-containing backbones and hydrophobicity enhancing and/or crystallinity reducing substituents.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/311 - Etching the insulating layers
  • C08G 2/20 - Copolymerisation of aldehydes or ketones with other aldehydes or ketones
  • C08L 59/04 - Copolyoxymethylenes

3.

BAFFLE FOR PROVIDING UNIFORM PROCESS GAS FLOW ON SUBSTRATE AND AROUND PEDESTAL

      
Application Number US2023034730
Publication Number 2024/081183
Status In Force
Filing Date 2023-10-09
Publication Date 2024-04-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sathish, Karthik Adappa
  • Barnett, Cody
  • Basargi, Mitali Mrigendra
  • Kumar, Ravi

Abstract

A substrate processing chamber includes a pedestal and a baffle. The pedestal is arranged in the substrate processing chamber. The pedestal includes a base portion and a stem portion. The base portion is greater in diameter than the stem portion. The baffle is arranged around the pedestal to direct flow of gases supplied to the substrate processing chamber to flow around the pedestal from a periphery of the base portion of the pedestal towards the stem portion of the pedestal and towards one or more exhaust ports of the substrate processing chamber.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

4.

PURGING TOXIC AND CORROSIVE MATERIAL FROM SUBSTRATE PROCESSING CHAMBERS

      
Application Number US2023034417
Publication Number 2024/081135
Status In Force
Filing Date 2023-10-04
Publication Date 2024-04-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Parmar, Ravi
  • Nuisud, Soonton
  • Pyle, Jonathan
  • Jonathans, Raymond
  • Deen, Raees Amer
  • Rachakonda, Sai
  • Chouhan, Nishant
  • Park, Jun-Hwa
  • Tokairin, Shawn
  • Rumer, Michael
  • Ko, Eunsuk
  • Boochakravarthy, Ashwin Agathya

Abstract

A system for performing preventive maintenance of a processing chamber of a substrate processing system using atmospheric air comprises a first plurality of valves and manifolds, a second plurality of valves and manifolds, and a controller. The first plurality of valves and manifolds are located downstream from the processing chamber. The second plurality of valves and manifolds are located upstream from the processing chamber. The controller is configured to perform the preventive maintenance by: initially purging the processing chamber and the first plurality of valves and manifolds while maintaining pressure in the processing chamber between a first pressure and a second pressure that is greater than the first pressure and less than atmospheric pressure, and subsequently purging the processing chamber and the second plurality of valves and manifolds while maintaining pressure in the processing chamber between the first pressure and a third pressure that is less than the first pressure.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

5.

DEPOSITION OF METAL-CONTAINING FILMS

      
Application Number US2023034858
Publication Number 2024/081263
Status In Force
Filing Date 2023-10-10
Publication Date 2024-04-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Mandia, David Joseph
  • Agnew, Douglas Walter
  • Smith, Joel David
  • Griffiths, Matthew Bertram Edward
  • Richey, Nathaniel Elba
  • Fox, Alexander Ray
  • Blakeney, Kyle Jordan
  • Hausmann, Dennis M.
  • Na, Jeong-Seok
  • Lai, Chiukin Steven
  • Kanakasabapathy, Sivananda Krishnan

Abstract

in situin situ generation of an iodine-bond containing metal species with an iodine-containing reagent and a metal-containing precursor followed by reduction at a process temperature below 400ºC. In particular, the film can be a molybdenum-containing film. The methods may also include simultaneous introduction of the reagent and the precursor or an optional pretreatment with a passivation gas. Also provided are methods for depositing molybdenum-containing films on semiconductor using low valent molybdenum-containing precursors. The low valent molybdenum precursors of one or two molybdenum atoms may have at least one ligand which is an isocyanohaloalkyl, an allyl, an aryl, a tertiary organophosphino or an alkoxide group.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds
  • C07F 11/00 - Compounds containing elements of Groups 6 or 16 of the Periodic System
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

6.

ELECTRODEPOSITION SYSTEM WITH ION-EXCHANGE MEMBRANE IRRIGATION

      
Application Number US2023075229
Publication Number 2024/081507
Status In Force
Filing Date 2023-09-27
Publication Date 2024-04-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Wilmot, Frederick Dean
  • Sigamani, Nirmal Shankar
  • Feng, Jingbin

Abstract

Examples are disclosed that relate to irrigating an ion exchange membrane in an electrodeposition system. In one example, the electrodeposition system comprises a fluid distribution system comprising a membrane assembly that comprises a membrane frame configured to support an ion exchange membrane that defines a boundary of a cathode chamber. The fluid distribution system further comprises a high resistance virtual anode (HRVA) positioned between the membrane frame and a substrate holder, a catholyte circulation loop operable to flow catholyte in a first direction across a surface of the HRVA facing the substrate holder and a plurality of flow barriers extending between the membrane frame and the HRVA along a second direction, transverse to the first direction. Irrigation conduits are positioned between adjacent flow barriers, each irrigation conduit configured to receive catholyte from the catholyte circulation loop and to direct catholyte towards the membrane assembly via a plurality of emitters.

IPC Classes  ?

  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 17/10 - Electrodes
  • C25D 5/08 - Electroplating with moving electrolyte, e.g. jet electroplating
  • C25D 7/12 - Semiconductors

7.

CLEANING A CHEMICAL VAPOR DEPOSITION CHAMBER

      
Application Number US2023075660
Publication Number 2024/081516
Status In Force
Filing Date 2023-10-01
Publication Date 2024-04-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Cao, Chezheng
  • Zheng, Huifeng
  • Hong, Tu
  • Sanchez, Ivan Alexander
  • Ji, Chunhai
  • Li, Ming

Abstract

A method is provided for cleaning deposition residue from a processing chamber of a processing tool. The method comprises introducing a reactive cleaning species generated by a remote plasma into the processing chamber. An in-situ plasma is formed at a processing station within the processing chamber while introducing the reactive cleaning species generated by the remote plasma into the processing chamber.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/52 - Controlling or regulating the coating process

8.

SHOWERHEAD FOR DIFFUSION BONDED, MULTI-ZONE GAS DISPERSION

      
Application Number US2023033786
Publication Number 2024/076477
Status In Force
Filing Date 2023-09-27
Publication Date 2024-04-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lind, Gary B.
  • Chandrashekar, Anand
  • Donnelly, Sean M.
  • Kho, Leonard
  • Garg, Atul Kumar
  • Hosur Shivalinge Gowda, Arun Kumar

Abstract

A showerhead for a substrate processing chamber configured to perform bulk deposition includes a faceplate, a backplate, and a faceplate. The faceplate defines a first plenum corresponding to center and middles zones and a second plenum corresponding to an edge zone. The faceplate includes a first plurality of holes distributed throughout the center zone and the middle zone and a second plurality of holes distributed throughout the edge zone. The middle plate is disposed between the faceplate and the backplate. The faceplate is configured to receive a first gas mixture supplied to the center zone via a center inlet, receive a second gas mixture supplied to the middle zone via a middle inlet, blend the first gas mixture and the second gas mixture within the first plenum, and receive a third gas mixture supplied to the edge zone via an edge inlet.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

9.

SHOWERHEAD GAS INLET MIXER

      
Application Number US2023033788
Publication Number 2024/076478
Status In Force
Filing Date 2023-09-27
Publication Date 2024-04-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lind, Gary B.
  • Kho, Leonard
  • Garg, Atul Kumar
  • Hosur Shivalinge Gowda, Arun Kumar
  • Leeser, Karl Frederick

Abstract

A showerhead for a substrate processing chamber includes a head portion configured to receive a gas mixture and a stem portion coupled to the head portion. A first plenum is defined within the head portion and the gas mixture flows into the plenum and from the plenum into the substrate processing chamber via holes arranged in a lower surface of the head portion. The stem portion is configured to supply the gas mixture to the head portion through a central bore. A mixing chamber is arranged on the stem portion. The mixing chamber is configured to receive a first gas supplied from a first mixer inlet and a second gas supplied from a second mixer inlet, mix the first gas and the second gas into the gas mixture, and direct the gas mixture into an upper end of the central bore to be supplied downward into the head portion.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

10.

ANNULAR PUMPING FOR CHAMBER

      
Application Number US2023033794
Publication Number 2024/076480
Status In Force
Filing Date 2023-09-27
Publication Date 2024-04-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lind, Gary B.
  • Kho, Leonard
  • Leeser, Karl Frederick
  • Garg, Atul Kumar
  • Kondi, Sushanth
  • Hosur Shivalinge Gowda, Arun Kumar

Abstract

A processing chamber assembly for a substrate processing system includes a first section, a second section, and a third section. The first section defines a first volume configured to enclose a pedestal arranged within the processing chamber assembly. The first volume includes an upper portion, a middle portion, and a lower portion. The second section is disposed below the first section and defines the lower portion of the first volume. An upper surface of the second section defines a second volume radially outside of the first volume. A lower surface of the second section defines a third volume radially outside of the first volume. The third section is disposed below the second section and defines a main pumping port aligned with the third volume. First channels connect the upper portion of the first volume to the second volume. Second channels connect the second volume to the third volume.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/52 - Controlling or regulating the coating process

11.

HYDROGEN REDUCTION OF SILICON NITRIDE PASSIVATION LAYER BY FORMATION AND TREATMENT OF PASSIVATION SUB-LAYERS

      
Application Number US2023033258
Publication Number 2024/076467
Status In Force
Filing Date 2023-09-20
Publication Date 2024-04-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Pak, Chongin
  • Qi, Chengzhu

Abstract

A method for developing a passivation film on a substrate with less than 10 atomic% of hydrogen includes providing the substrate within a processing station of a substrate processing system. A resultant passivation film is formed with less than 10 atomic% of hydrogen on the substrate by performing the following steps of: depositing a passivation film sub-layer on the substrate, where the passivation film sub-layer lays on a semiconductor device layer or directly on a previously deposited passivation film sub-layer; and after depositing the passivation film sub-layer, performing a post plasma treatment to the passivation film sub-layer with at least one of nitrogen and argon to reduce hydrogen content within the passivation film sub-layer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3105 - After-treatment
  • H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • C23C 16/56 - After-treatment
  • C23C 16/34 - Nitrides

12.

ADJUSTABLE PEDESTAL

      
Application Number US2023033791
Publication Number 2024/076479
Status In Force
Filing Date 2023-09-27
Publication Date 2024-04-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lind, Gary B.
  • Kho, Leonard
  • Eib, Andrew Paul
  • Gulabal, Vinayakaraddy

Abstract

A pedestal assembly for a substrate processing system configured to perform bulk deposition on a substrate is configured to be raised and lowered. The pedestal assembly includes a stem portion, a baseplate portion disposed on the stem portion, and a pumping ring assembly. The baseplate portion is configured to support the substrate. The pumping ring assembly is disposed around the baseplate portion and includes a lower pumping ring and an upper pumping ring disposed above the lower pumping ring. The pumping ring assembly is configured to define an annular volume radially outside of the pumping ring assembly such that the pumping ring assembly separates the annular volume from a volume defined below the baseplate portion of the pedestal assembly.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

13.

IMPROVING CHEMISTRY UTILIZATION BY INCREASING PRESSURE DURING SUBSTRATE PROCESSING

      
Application Number US2023034381
Publication Number 2024/076576
Status In Force
Filing Date 2023-10-03
Publication Date 2024-04-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Richey, Nathaniel Elba
  • Bhimarasetti, Gopinath

Abstract

A substrate processing system comprises a processing chamber comprising a pedestal configured to support a substrate. The processing chamber comprises a showerhead configured to supply precursors during dose steps and a purge gas during purge steps of an atomic layer deposition (ALD) process to process the substrate. The dose steps and the purge steps comprise a sequence of a dose step followed by a subsequent purge step. The substrate processing system comprises a throttle valve connected to the processing chamber and a vacuum pump connected to the throttle valve. The substrate processing system comprises a controller configured to control the vacuum pump, open the throttle valve during the purge steps, and close the throttle valve during at least a portion of the dose steps to increase pressure in the processing chamber during at least the portion of the dose steps of the ALD process.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

14.

DRY CHAMBER CLEAN USING THERMAL AND PLASMA PROCESSES

      
Application Number US2023034545
Publication Number 2024/076679
Status In Force
Filing Date 2023-10-05
Publication Date 2024-04-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Volosskiy, Boris
  • Kc, Shambhu
  • Wang, Chen
  • Lushington, Andrew Pratheep
  • Myers, Michael Thomas
  • Weidman, Timothy William
  • Tucker, Jeremy Todd
  • Peter, Daniel
  • Tan, Samantha S.H.
  • Hubacek, Jerome S.
  • Jensen, Alan J.
  • Ramalingam, Jothilingam
  • Wise, Richard
  • Stevens, Jason
  • Ong, Seng
  • Labib, Shahd Hassan
  • Yamaguchi, Yoko

Abstract

A metal-containing photoresist film may be deposited on a semiconductor substrate. Unintended metal-containing material may form on internal surfaces of a process chamber during deposition, bevel and backside cleaning, exposure, baking, development, etch, or other photolithography operations. A dry chamber clean may remove some of the unintended metal-containing material by exposure to plasma. A dry chamber clean may remove some of the unintended metal-containing material and modify some of the unintended metal-containing material by exposure to an etch gas at an elevated temperature without striking a plasma. The dry chamber clean may remove the modified metal-containing material using plasma having a chemistry configured to form volatile products of the modified metal-containing material. In some embodiments, the plasma includes a halide-containing plasma, hydrogen-containing plasma, hydrocarbon-containing plasma, inert gas-containing plasma, or mixtures thereof.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

15.

LAYERED METAL OXIDE-SILICON OXIDE FILMS

      
Application Number US2023073490
Publication Number 2024/073220
Status In Force
Filing Date 2023-09-05
Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Agarwal, Pulkit
  • Liu, Pei-Chi
  • Kumar, Ravi
  • Petraglia, Jennifer Leigh
  • Srinivasan, Easwar
  • Van Schravendijk, Bart J.

Abstract

Examples are disclosed that relate to layered metal oxide films. One example provides a method of forming a patterning structure. The method comprises performing one or more layered film deposition cycles to form a layered film comprising a metal oxide. A layered film deposition cycle of the one or more layered deposition cycles comprises a metal oxide deposition subcycle and a silicon oxide deposition cycle. The metal oxide deposition subcycle comprises exposing the substrate to a metal-containing precursor and oxidizing metal-containing precursor adsorbed to the substrate. The silicon oxide deposition subcycle comprising exposing a substrate to a silicon-containing precursor and oxidizing silicon-containing precursor adsorbed to the substrate. The method further comprises etching one or more regions of the layered film to form the patterning structure.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • C23C 16/40 - Oxides

16.

GENERATION OF SYNTHETIC SEMICONDUCTOR IMAGES

      
Application Number US2023075014
Publication Number 2024/073344
Status In Force
Filing Date 2023-09-25
Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lee, Yan Kang
  • Agusanto, Kusuma
  • Gowda, Shiva Prasad Mare
  • Alden, Emily Ann

Abstract

Methods, systems, and media for generating synthetic semiconductor image data are provided. In some embodiments, a method comprises generating a set of synthetic segmented images, each synthetic segmented image of the set of synthetic segmented images representing a segmented semiconductor metrology image. The method may comprise generating, using a first trained GAN, a set of virtual images, each virtual image corresponding to one of the synthetic segmented images in the set of synthetic segmented images. The method may comprise constructing a training set comprising a plurality of training samples, each training sample comprising a synthetic segmented image from the set of synthetics segmented images and a corresponding virtual image from the set of virtual images, wherein the training set is usable to train a downstream model configured to model semiconductor fabrication processes.

IPC Classes  ?

17.

POST ETCH PLASMA TREATMENT FOR REDUCING SIDEWALL CONTAMINANTS AND ROUGHNESS

      
Application Number US2023075090
Publication Number 2024/073390
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Agarwal, Daksh
  • Ozel, Taner
  • Mukhopadhyay, Amit
  • Xu, Qing
  • Wong, Merrett

Abstract

A method of forming features in stack with a silicon containing layer below a mask is provided. Features are etched into the stack. A post etch plasma treatment is provided to reduce surface roughness of sidewalls of the features.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

18.

DOME SHAPED CHAMBER FOR GENERATING IN-SITU CLEANING PLASMA

      
Application Number US2023033198
Publication Number 2024/072668
Status In Force
Filing Date 2023-09-20
Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Hart, Kyle Watt
  • Guo, Tongtong
  • Batzer, Rachel E.
  • Das, Shoudho
  • Madineni, Damodar Aravind
  • Wang, Yuxi
  • Gong, Bo
  • Keshav, Pramod
  • Thilagaraj, Mohan
  • Hohn, Geoffrey

Abstract

A processing chamber includes a first portion, including a dome, and a second portion. The dome includes a ceramic material and is elliptical in shape. A pedestal to process a substrate is arranged in the second portion. A showerhead is arranged at a base of the dome between the first and second portions. An injector including the ceramic material is mounted on the dome to inject a process gas and a cleaning gas into the dome during substrate processing and cleaning of the processing chamber, respectively. A coil is disposed around a portion of the dome. An RF generator supplies RF power to the coil to generate plasma in the dome during the substrate processing and the cleaning. A controller controls temperatures of the pedestal and the showerhead at respective predetermined temperatures within a predetermined range during the substrate processing and the cleaning.

IPC Classes  ?

19.

OPTIMIZATION OF FABRICATION PROCESSES

      
Application Number US2023033955
Publication Number 2024/072948
Status In Force
Filing Date 2023-09-28
Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lu, Yu
  • Park, Sae Na
  • Hong, Kah Jun
  • Frey, Lucas Ryan
  • Blum, Zachary Jake
  • Roschewsky, Niklas
  • Ambikapathi, Arulmurugan
  • Liu, Chao
  • Tetiker, Mehmet Derya

Abstract

Methods, systems, and media for optimization of fabrication processes are provided. In some implementations, a method of automatically optimizing fabrication processes comprises: (a) providing a first set of process parameter values associated with a first experiment to a model representing a fabrication process; (b) characterizing a statistical uncertainty of predictions made by the model; (c) using an acquisition function to select a second set of process parameter values, wherein the acquisition function identifies the second set of process parameters based on both: (i) a difference between predicted wafer characteristics and a target specification; and (ii) the statistical uncertainty; (d) receiving results of the fabrication process performed using the second set of process parameter values; and (e) determining whether the performance of the fabrication process generates a post-processed wafer having wafer characteristics that meet the target specification.

IPC Classes  ?

  • G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
  • G05B 23/02 - Electric testing or monitoring

20.

PEDESTAL WITH AXIALLY SYMMETRIC EDGE PURGE PLENUM

      
Application Number US2023075165
Publication Number 2024/073447
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Gage, Christopher
  • Kadam, Nitin

Abstract

This disclosure pertains to pedestal assemblies for supporting wafers in semiconductor manufacturing tools and chambers. Such pedestal assemblies may have an edge purge system that includes an axially symmetric first plenum volume that includes at least a first radial sub-volume, a first axial sub-volume, and a second radial sub-volume. The first axial sub-volume may be fluidically interposed between the first radial sub-volume and the second radial sub-volume. An optional second plenum volume may be provided as well and may be used to fluidically connect a region of a wafer support that is part of the pedestal assembly with a vacuum port to allow the wafer support to provide vacuum clamping functionality.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

21.

ELECTRONIC COMPONENT COOLING USING COOLING MANIFOLDS FOR PRESSURIZED AIR

      
Application Number US2023075166
Publication Number 2024/073448
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Borth, Andrew
  • Donnelly, Sean M.

Abstract

Cooling systems featuring cooling manifolds with features that conform to the shape of an electrical component to be cooled are provided herein. Such cooling manifolds may be connected with a cooling fluid source, such as a clean dry air source, by flexible and/or rigid flow conduits. The cooling manifolds may have one or more outlet ports that are configured to direct cooling fluid towards one or more surfaces of the electrical component to be cooled so that the cooling fluid directly impinges on one or more surfaces thereof.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

22.

AUTOMATED CONTROL OF PROCESS CHAMBER COMPONENTS

      
Application Number US2023033209
Publication Number 2024/072670
Status In Force
Filing Date 2023-09-20
Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sawlani, Kapil
  • Franzen, Paul
  • Martin, Patging John Elsworth

Abstract

Methods, systems, and media for deposition control in a process chamber are provided. In some embodiments, a method comprises (a) obtaining, at a present time, information indicating a status of one or more components of the process chamber during performance of a deposition process on one or more wafers. The method may comprise (b) determining whether adjustments to one or more control components of the process chamber are to be made by providing an input based on the obtained information to a trained machine learning model configured to determine adjustments as an output, wherein the adjustments to the one or more control components cause a change in the deposition process. The method may comprise (c) transmitting instructions to a controller of the process chamber that cause the adjustments to the one or more control components to be implemented.

IPC Classes  ?

  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

23.

PLASMA-EXPOSED PARTS COMPRISING AN ETCH-RESISTANT MATERIAL

      
Application Number US2023072767
Publication Number 2024/064494
Status In Force
Filing Date 2023-08-23
Publication Date 2024-03-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Rajagopalan, Mansa
  • Tom, Kyle Brandon
  • Khirbat, Aditi
  • Canniff, Justin Charles

Abstract

One example provides a plasma-exposed part for a plasma processing tool. The plasma-exposed part comprises an etch-resistant material that has a lower etch rate than silicon or silicon carbide when exposed to plasma process gas chemistries comprising fluorine and/or oxygen. The etch-resistant material comprising one or more of (a) an oxide, a nitride, or an oxynitride of one or more of titanium, hafnium, zirconium, or tin, or (b) one or more of silicon or silicon carbide doped with one or more of titanium, hafnium, zirconium, or tin.

IPC Classes  ?

24.

METHOD FOR ETCHING FEATURES IN A STACK

      
Application Number US2023073655
Publication Number 2024/064526
Status In Force
Filing Date 2023-09-07
Publication Date 2024-03-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Belau, Leonid
  • Hudson, Eric

Abstract

A method for etching features in a stack comprising a silicon oxide layer below a mask is provided. A substrate support for supporting the stack in an etch chamber is cooled to a temperature below 0° C. An etch gas comprising a halogen containing component and a phosphorous containing component is provided. A plasma is generated from the etch gas. A bias is provided to accelerate ions from the plasma to the stack. Features are selectively etched in the stack with respect to the mask.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

25.

GAS DISTRIBUTION PORT INSERT AND APPARATUS INCLUDING THE SAME

      
Application Number US2023033446
Publication Number 2024/064319
Status In Force
Filing Date 2023-09-22
Publication Date 2024-03-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Mak, Joshua Nathaniel Eric
  • Boatright, Daniel
  • Huang, Yanhui
  • Beaudette, Chad Adrien
  • Linebarger Jr., Nick Ray
  • Shaikh, Fayaz A.
  • Luo, Bin
  • Leonard, Callan Patrick
  • Wang, Ruisong
  • Lee, James Forest

Abstract

A gas distribution port insert, and equipment for use therewith, capable of suppressing or at least reducing process gas interaction with and/or back diffusion into a gas distribution body including the gas distribution port insert in association with a semiconductor processing tool.

IPC Classes  ?

26.

PYROCHLORE COMPONENT FOR PLASMA PROCESSING CHAMBER

      
Application Number US2023030811
Publication Number 2024/063892
Status In Force
Filing Date 2023-08-22
Publication Date 2024-03-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Wetzel, David Joseph
  • Xu, Lin
  • Liu, Lei
  • Detert, Douglas
  • Yasseri, Amir A.
  • Daugherty, John

Abstract

A component for use in a plasma processing chamber system is provided. A component body has a plasma facing surface. The plasma facing surface comprises a pyrochlore, comprising at least one of zirconium and hafnium and at least one of lanthanum (La), samarium (Sm), yttrium (Y), erbium (Er), cerium (Ce), gadolinium (Gd), ytterbium (Yb), and neodymium (Nd).

IPC Classes  ?

27.

BELLOWS SEAL FOR LOW THRU-FORCE ACTUATION OF TEMPERATURE PROBE ACROSS VACUUM INTERFACE

      
Application Number US2023032982
Publication Number 2024/064049
Status In Force
Filing Date 2023-09-18
Publication Date 2024-03-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Perez, Aris
  • Stevenot, Scott
  • Matyushkin, Alexander
  • Mace, Adam Christopher

Abstract

An actuator assembly to actuate a plasma tuning ring in a processing chamber includes an actuator, a rod, bellows, and vacuum seals. The actuator is arranged external to the processing chamber. The processing chamber is under vacuum. The actuator is at atmospheric pressure. The rod is coupled to the actuator and to the plasma tuning ring in the processing chamber. The bellows are arranged external to the processing chamber between the actuator and the processing chamber. The rod passes through the bellows into the processing chamber. The vacuum seals are disposed between the bellows and the actuator and between the bellows and the processing chamber to seal the vacuum in the processing chamber from the atmospheric pressure external to the processing chamber.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

28.

BAKE-SENSITIVE UNDERLAYERS TO REDUCE DOSE TO SIZE OF EUV PHOTORESIST

      
Application Number US2023033020
Publication Number 2024/064071
Status In Force
Filing Date 2023-09-18
Publication Date 2024-03-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Demuth, Joshua James
  • Xue, Jun
  • Peter, Daniel
  • Liu, Yulu
  • Tan, Samantha S.H.
  • Chen, I-Cheng
  • Manumpil, Mary Anne

Abstract

Provided are patterning structure underlayers deposited between a. substrate and an imaging layer, the underlayers having chemically labile, activatable bonds useful in extreme ultraviolet lithography. Reactive moieties may be released from the underlayer's activatable bonds in the presence of heat, oxidizing gases and/or inert gases into the imaging layer above.

IPC Classes  ?

  • G03F 7/11 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
  • G03F 7/20 - Exposure; Apparatus therefor
  • G03F 7/38 - Treatment before imagewise removal, e.g. prebaking
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

29.

SEMICONDUCTOR STACKS AND PROCESSES THEREOF

      
Application Number US2023033175
Publication Number 2024/064161
Status In Force
Filing Date 2023-09-19
Publication Date 2024-03-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Srinivasan, Easwar
  • Varadarajan, Bhadri N.
  • Leeser, Karl Frederick
  • Hausmann, Dennis M.
  • Van Schravendijk, Bart J.
  • Durbin, Aaron
  • Chandrasekharan, Ramesh
  • Sakiyama, Yukinori

Abstract

The present disclosure relates to vertical stacks including heterolayers, as well as processes and methods of their manufacture. Also described herein are apparatuses and systems for preparing and making such stacks.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/24 - Deposition of silicon only
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/452 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials by activating reactive gas streams before introduction into the reaction chamber, e.g. by ionization or by addition of reactive species

30.

METHOD FOR ETCHING FEATURES USING HF GAS

      
Application Number US2023073737
Publication Number 2024/059467
Status In Force
Filing Date 2023-09-08
Publication Date 2024-03-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Hudson, Eric
  • Belau, Leonid
  • Lill, Thorsten

Abstract

START PLACE STACK IN CHAMBER ON SUPPORT COOL SUPPORT FLOW HF ETCH GAS INTO CHAMBER FORM ETCH GAS INTO PLASMA EXPOSE STACK TO PLASMA SELECTIVELY ETCH STACK REMOVE STACK FROM CHAMBER STOP

IPC Classes  ?

  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L 21/311 - Etching the insulating layers
  • C09K 13/00 - Etching, surface-brightening or pickling compositions

31.

BACKSIDE LAYER FOR A SEMICONDUCTOR SUBSTRATE

      
Application Number US2023032425
Publication Number 2024/059012
Status In Force
Filing Date 2023-09-11
Publication Date 2024-03-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Hamma, Soumana
  • Shaikh, Fayaz A.
  • Greninger, Sonia

Abstract

A composite nanocrystalline silicon layer can be formed by depositing a polycrystalline silicon sublayer directly or indirectly on a substrate. An amorphous silicon sublayer is deposited on the polycrystalline silicon sublayer. The composite nanocrystalline silicon layer can be formed by repeating the deposition of the polycrystalline silicon sublayer and the amorphous silicon sublayer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01J 37/32 - Gas-filled discharge tubes

32.

SHOWERHEAD FACEPLATES

      
Application Number US2023074154
Publication Number 2024/059684
Status In Force
Filing Date 2023-09-14
Publication Date 2024-03-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Huang, Zubin
  • Tucker, Jeremy Todd
  • Gear, Conor Le
  • Trakroo, Ujjwal Aashray

Abstract

Semiconductor processing tool showerhead designs suitable for multi-gas delivery and for being made through additive manufacturing are provided. Such showerhead designs may feature either internal spiral passages or internal plenums with a plurality of pillars spanning between upper and lower surfaces thereof distributed throughout.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • B33Y 80/00 - Products made by additive manufacturing

33.

SPRING-LOADED SEAL COVER BAND FOR PROTECTING A SUBSTRATE SUPPORT

      
Application Number US2023032885
Publication Number 2024/059276
Status In Force
Filing Date 2023-09-15
Publication Date 2024-03-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Truong, Khoa Dang
  • Behziz, Behnam
  • Lie, Roger
  • Mitrovic, Slobodan
  • Yu, Yixuan
  • Ehrlich, Darrell
  • Wang, Feng
  • Samulon, Eric
  • Chen, Andra Yuting

Abstract

A spring-loaded seal band for protecting a bonding layer of a substrate support, the spring-loaded seal band includes an annular body having a first length when the spring-loaded seal band is in an uncompressed state. The annular body comprises a first annular body portion, an annular arm, and a flexible neck portion that connects the first annular body portion and the annular arm. The spring-loaded seal band is configured to surround the substrate support between a lower surface of a top plate and an upper surface of a baseplate. The lower surface of the top plate and the upper surface of the baseplate is separated by a second length. The first length is greater than the second length. The flexible neck portion is configured to bend when the spring-loaded seal band is in an installed compressed state.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

34.

SHAPED SILICON OUTER UPPER ELECTRODE FOR PLASMA PROCESSING

      
Application Number US2023073229
Publication Number 2024/054774
Status In Force
Filing Date 2023-08-31
Publication Date 2024-03-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Thompson, William, Dean
  • Bailey, Andrew, D.

Abstract

An outer upper electrode for plasma processing. A shaped bottom surface and a top surface having a radial width, wherein a middle portion of the top surface has an oval shape. A cylindrical outline traversing a height of the outer upper electrode, wherein the middle portion of the top surface defines a top of the cylindrical outline. An inner diameter surface joining the top surface and the shaped bottom surface, wherein the inner diameter surface includes a transition edge. An outer diameter surface joining the top surface and the shaped bottom surface. A convex protrusion of the shaped bottom surface protruding below the transition edge of the inner diameter surface, wherein the convex protrusion includes a protrusion minima that is located in an interior region of the cylindrical outline.

IPC Classes  ?

35.

GAS COOLING COVER FOR AN EXHAUST LINE OF A SUBSTRATE PROCESSING SYSTEM

      
Application Number US2023030564
Publication Number 2024/054344
Status In Force
Filing Date 2023-08-18
Publication Date 2024-03-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Borth, Andrew
  • Donnelly, Sean M.

Abstract

A gas cooling cover for an exhaust connector of a substrate processing system includes a first cover portion configured for arrangement around a first portion of the exhaust connector of the substrate processing system and including a first body defining a first gas plenum and a second gas plenum. A first gas inlet is arranged on an outer surface of the first body and in fluid communication with the first gas plenum. A first plurality of nozzles is arranged on an inner surface of the first cover portion and in fluid communication with the first gas plenum. A first plurality of exhaust ports is arranged on the inner surface of the first cover portion and configured to direct gas located between the first cover portion and the first portion of the exhaust connector to the second gas plenum of the first body.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

36.

DOPED SILICON OR BORON LAYER FORMATION

      
Application Number US2023031873
Publication Number 2024/054413
Status In Force
Filing Date 2023-09-01
Publication Date 2024-03-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Yang, Nuoya
  • Wang, Yuxi
  • Gong, Bo
  • Mckerrow, Andrew John

Abstract

An amorphous silicon layer or amorphous boron layer can be deposited on a substrate using one or more silicon or boron-containing precursors, respectively. Radical species are provided from a plasma source or from a controlled reaction chamber atmosphere to convert the amorphous silicon layer to a doped silicon layer with composition tunability. An initiation layer is deposited on one or more semiconductor device structures having a dielectric layer over an electrically conductive layer. The initiation layer may be conformally deposited by a CVD-based process and may comprises amorphous silicon, doped silicon, amorphous boron, or doped boron.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

37.

MULTI-SENSOR DETERMINATION OF A STATE OF SEMICONDUCTOR EQUIPMENT

      
Application Number US2023031458
Publication Number 2024/054380
Status In Force
Filing Date 2023-08-29
Publication Date 2024-03-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sawlani, Kapil
  • Franzen, Paul
  • Vasquez, Miguel Benjamin
  • Yee, Benjamin Tong
  • Konkola, Paul
  • Valley, John

Abstract

Methods and apparatus for multi-sensor determination of a state of semiconductor equipment are provided In some embodiments disclosed herein, semiconductor manufacturing equipment may include: a plurality of sensors comprising one or more spatial sensors, one or more spectral sensors, and one or more temporal sensors disposed about the semiconductor manufacturing equipment; and a controller communicatively coupled to the plurality of sensors, the controller configured to cause: determining a set of signals, from the plurality of sensors, to monitor during a process to be performed by the semiconductor manufacturing equipment; during the process, obtaining measurements associated with the set of signals from the plurality of sensors; and determining an indication of a state of the semiconductor manufacturing equipment based on a combination of data generated from the measurements associated with the set of signals.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes
  • G01J 3/28 - Investigating the spectrum

38.

A TEMPERATURE CONTROLLED SHOWER HEAD FOR A PROCESSING TOOL

      
Application Number US2023072595
Publication Number 2024/050248
Status In Force
Filing Date 2023-08-21
Publication Date 2024-03-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Jones, Christopher Matthew
  • Durbin, Aaron
  • Miller, Aaron Blake
  • Lemaire, Paul C.
  • Edmondson, Bryce Isaiah
  • Abel, Joseph R.

Abstract

An apparatus includes a shower head comprising a disk and a stem coupled with the disk and an adjuster coupled with the stem. The adjuster includes an adapter comprising a heater cartridge; and a fluid line adjacent to the heater cartridge, where the heater cartridge extends from a top surface of the adapter through a first cavity in the adapter and within a second cavity in the stem. The adapter further includes a bellows comprising a flange, where the bellows is coupled with the adapter through the flange.

IPC Classes  ?

39.

MODULAR VAPOR DELIVERY SYSTEM FOR SEMICONDUCTOR PROCESS TOOLS

      
Application Number US2023072597
Publication Number 2024/050249
Status In Force
Filing Date 2023-08-21
Publication Date 2024-03-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Jones, Christopher Matthew
  • Durbin, Aaron
  • Bamford, Thadeous
  • Stumpf, John Folden
  • Lemaire, Paul C.
  • Edmondson, Bryce Isaiah
  • Abel, Joseph R.

Abstract

A modular vapor delivery system comprising a flow control component module that comprises a first inlet port and a second inlet port, a liquid flow controller coupled to an outlet port of the flow control component module, and a vaporizer module coupled to an outlet port of the liquid flow controller.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/52 - Controlling or regulating the coating process

40.

ATOMIC LAYER DEPOSITION WITH IN-SITU SPUTTERING

      
Application Number US2023072609
Publication Number 2024/050252
Status In Force
Filing Date 2023-08-22
Publication Date 2024-03-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Baker, Jonathan Grant
  • Agarwal, Pulkit
  • Liu, Pei-Chi
  • Jiang, Gengwei

Abstract

Examples are disclosed that relate to using in-situ sputtering in an atomic layer deposition tool to form an angular surface feature in a substrate. One example provides a method of forming an angular surface feature on a substrate in an integrated circuit process. The method comprises placing the substrate in a processing chamber of an atomic layer deposition (ALD) tool. The method further comprises controlling the ALD tool to form a film on the substrate by performing one or more ALD cycles. The method further comprises controlling the ALD tool to sputter the film to form the angular surface feature.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/56 - After-treatment
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • H01J 37/32 - Gas-filled discharge tubes

41.

NITRIDE THERMAL ATOMIC LAYER ETCH

      
Application Number US2023031035
Publication Number 2024/049699
Status In Force
Filing Date 2023-08-24
Publication Date 2024-03-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Routzahn, Aaron Lynn
  • Lill, Thorsten Bernd
  • Fischer, Andreas

Abstract

Provided are nitride atomic layer etch including in situ generating a phosphoric acid on the surface of silicon nitride layer by reacting a phosphorus containing reactant with one or more oxidants. Phosphoric acid selectively etches silicon nitride layer over silicon oxide and/or silicon.

IPC Classes  ?

  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

42.

A PLASMA PROCESSING SYSTEM WITH A GAS RECYCLING SYSTEM

      
Application Number US2023030790
Publication Number 2024/044165
Status In Force
Filing Date 2023-08-22
Publication Date 2024-02-29
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Albarede, Luc
  • Paterson, Alexander Miller
  • Marsh, Richard A.

Abstract

A gas recycling system attachable to a semiconductor processing chamber is provided. A membrane filtering system is in fluid connection with the semiconductor processing chamber, the membrane filtering system comprising at least one gas separation membrane, wherein the at least one gas separation membrane filters a pressurized exhaust gas from the semiconductor processing chamber to separate at least one gas from the pressurized exhaust gas.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • B01D 46/10 - Particle separators, e.g. dust precipitators, using filter plates, sheets or pads having plane surfaces

43.

HIGH ASPECT RATIO ETCH WITH A NON-UNIFORM METAL OR METALLOID CONTAINING MASK

      
Application Number US2023030867
Publication Number 2024/044216
Status In Force
Filing Date 2023-08-22
Publication Date 2024-02-29
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Veber, Gregory Clinton
  • Chuang, Ming-Yuan
  • Puthenkovilakam, Ragesh
  • Reddy, Kapu Sirish
  • Bhadauriya, Sonal
  • Yu, Yongsik
  • Mukhopadhyay, Amit
  • Xu, Qing
  • Wong, Merrett

Abstract

A method for etching features in a stack is provided. A non-uniform metal or metalloid containing mask is formed over the stack. The stack is etched through the non-uniform metal or metalloid containing mask, wherein the etching sputters metal or metalloid in the non-uniform metal or metalloid containing mask and the sputtered metal or metalloid physically redeposits on sidewalls of features etched in the stack as a sputtered metal or metalloid containing passivation layer.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

44.

HIGH ASPECT RATIO ETCH WITH A RE-DEPOSITED HELMET MASK

      
Application Number US2023030868
Publication Number 2024/044217
Status In Force
Filing Date 2023-08-22
Publication Date 2024-02-29
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Mukhopadhyay, Amit
  • Piskun, Ilya
  • Veber, Gregory Clinton
  • Xu, Qing
  • Yu, Yongsik
  • Wong, Merrett
  • Roberts, Francis Sloan
  • Maliekkal, Vineet
  • Puthenkovilakam, Ragesh
  • Reddy, Kapu Sirish

Abstract

A method for etching features in a stack is provided. A patterned mask is formed over the stack. The stack is partially etched through the patterned mask. A helmet mask is deposited over the patterned mask. The stack is etched through the helmet mask.

IPC Classes  ?

45.

HIGH ASPECT RATIO ETCH WITH A LINER

      
Application Number US2023030869
Publication Number 2024/044218
Status In Force
Filing Date 2023-08-22
Publication Date 2024-02-29
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Mukhopadhyay, Amit
  • Xu, Qing
  • Wong, Merrett
  • Piskun, Ilya
  • Veber, Gregory Clinton
  • Yu, Yongsik
  • Roberts, Francis Sloan
  • Puthenkovilakam, Ragesh
  • Reddy, Kapu Sirish

Abstract

A method for etching features in a stack is provided. A patterned mask is formed over the stack. Features are partially etched in the stack through the patterned mask. A helmet mask is deposited over the patterned mask and liner on sidewalls of the features. The stack is etched through the helmet mask.

IPC Classes  ?

46.

DUAL-CHANNEL MONOBLOCK GAS MANIFOLD

      
Application Number US2023030521
Publication Number 2024/039811
Status In Force
Filing Date 2023-08-18
Publication Date 2024-02-22
Owner LAM RESEARCH CORPORATION (USA)
Inventor Agarwal, Prahalad Narasinghdas

Abstract

This disclosure pertains to compact, mono-block manifolds for providing dual-channel gas delivery for semiconductor processing tools. Some such manifolds may be designed to have surface-mount flow component interfaces on opposite sides of the manifold so as to reduce the overall footprint of the manifold block.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

47.

SELECTIVE SIGE ETCHING USING THERMAL F2 WITH ADDITIVE

      
Application Number US2023029465
Publication Number 2024/039530
Status In Force
Filing Date 2023-08-04
Publication Date 2024-02-22
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Melaet, Gerome Michel Dominique
  • Zhu, Ji
  • Kawaguchi, Mark Naoshi
  • Hua, Xuefeng
  • Gordon, Madeleine Parker

Abstract

2222. Use of the additive produces a more uniform etch rate for the material being etched than would otherwise be achieved in the absence of the additive.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

48.

MULTICHANNEL HEATED GAS DELIVERY SYSTEM

      
Application Number US2023030150
Publication Number 2024/039602
Status In Force
Filing Date 2023-08-14
Publication Date 2024-02-22
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Campello, Mark
  • Kondi, Sushanth
  • Potdar, Prashant
  • Bamford, Thadeous
  • Jonnagadla Rajagopal, Murali Krishna
  • Sitharamachari, Janardhan Achari Murkai
  • Patil, Naveen

Abstract

A gas conditioning assembly comprising a first block structure and at least a second block structure is disclosed. A first gas flow passage and a second gas flow passage extend within the first block structure. The first gas flow passage is adjacent to the second gas flow passage. The second block structure comprises a reservoir housing block and a reservoir yoke. The reservoir yoke comprises at least one gas reservoir within the reservoir housing block. The second block structure further comprises a nonplanar sidewall adjacent to the first block structure. The nonplanar sidewall comprises a plurality of recessed contours and a plurality of grooves extending along the nonplanar sidewall. Individual recessed contours are in thermal contact with adjacent surface mount components. Individual grooves are in thermal contact with gas line tubing sections extending from the first block structure.

IPC Classes  ?

  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

49.

BOND PROTECTION FOR AN ELECTROSTATIC CHUCK IN A PLASMA PROCESSING CHAMBER

      
Application Number US2023030343
Publication Number 2024/039717
Status In Force
Filing Date 2023-08-16
Publication Date 2024-02-22
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Narendrnath, Kadthala R.
  • Kondekar, Neha
  • Yu, Yixuan
  • Mitrovic, Slobodan
  • Samulon, Eric
  • Purandare, Moreshwar Narayan

Abstract

An electrostatic chuck system for use in a plasma processing chamber is provided. A conductive base plate is provided. A bond of a bonding material is bonded to a surface of the base plate on a first side of the bond. A ceramic plate is bonded to a second side of the bond. A protective strip surrounds the bond and extends between the conductive base plate and the ceramic plate, wherein the protective strip comprises at least one of an anodized strip, a ceramic tape strip, and a coated aluminum strip.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

50.

ELECTRODEPOSITION SYSTEMS

      
Application Number US2023070555
Publication Number 2024/030745
Status In Force
Filing Date 2023-07-20
Publication Date 2024-02-08
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • He, Zhian
  • Subbaiyan, Navaneetha Krishnan
  • Deshmukh, Swapnil Dattatray
  • Sweeney, Cian
  • Smedley, Benjamin
  • Reid, Jonathan
  • Ghongadi, Shantinath

Abstract

Examples are disclosed that relate to operating an electrodeposition system comprising an inert anode. In one example system, the electrodeposition system includes a substrate holder and a cathode chamber configured to hold a catholyte. An anode chamber configured to hold an anolyte during the electrodeposition process comprises an inert anode. An intermediate chamber is positioned between the cathode chamber and the anode chamber. The intermediate chamber is separated from the cathode chamber by an ion exchange membrane.

IPC Classes  ?

  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 17/06 - Suspending or supporting devices for articles to be coated
  • C25D 17/02 - Tanks; Installations therefor
  • C25D 17/10 - Electrodes
  • C25D 21/12 - Process control or regulation
  • C25D 21/22 - Regeneration of process solutions by ion-exchange

51.

SYSTEM AND METHOD TO MAINTAIN CONSTANT CLAMPING PRESSURE DURING CHAMBER REBOOTING AND POWER FAILURE INSTANCES

      
Application Number US2023028770
Publication Number 2024/030307
Status In Force
Filing Date 2023-07-27
Publication Date 2024-02-08
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Ramesh, Hemanth
  • Mace, Adam Christopher
  • Saleh, Muad M Ahmouda

Abstract

A clamping system for a substrate support includes a clamping assembly configured to clamp an edge ring to baseplate of the substrate support, a valve control assembly coupled to a compressed air source, and a valve assembly coupled between the valve control assembly and the clamping assembly. The valve assembly is coupled to the compressed air source and the valve control assembly, and the valve assembly separately receives compressed air as inputs from the compressed air source and the valve control assembly. The valve assembly is configured to selectively supply pressurized air from the compressed air source to the clamping assembly to clamp the edge ring to the baseplate in response to the inputs received from the valve control assembly.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01J 37/32 - Gas-filled discharge tubes

52.

REDUCING THERMAL BOW SHIFT

      
Application Number US2023029129
Publication Number 2024/030382
Status In Force
Filing Date 2023-07-31
Publication Date 2024-02-08
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Ha, Jeongseok
  • Yin, Xin
  • Chan, Michael Anthony
  • Shaikh, Fayaz A.

Abstract

Provided are methods and structures for keeping the integrity of layers deposited on a semiconductor wafer through a thermal cycle. Deposition of a second backside layer, or a cap, with an internal stress opposite to a first backside layer may be used to reduce bow shift of a wafer during a thermal cycle. The first backside layer may have a tensile internal stress or a compressive internal stress. The second backside layer has an internal stress opposite to the first backside layer. Each of the backside layers may be deposited by a backside deposition apparatus.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

53.

CONDUCTIVE BACKSIDE LAYER FOR BOW MITIGATION

      
Application Number US2023029138
Publication Number 2024/030386
Status In Force
Filing Date 2023-07-31
Publication Date 2024-02-08
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Kwon, Byung Seok
  • Huang, Yanhui
  • Hamma, Soumana
  • Ha, Jeongseok
  • Shaikh, Fayaz A.

Abstract

Provided are methods for keeping a semiconductor wafer chucked to an electrostatic chuck. The semiconductor wafer may have a conductive backside layer deposited on a backside of the wafer through backside deposition. The conductive layer may be able increase the electrostatic force between the wafer and the electrostatic chuck and to counteract internal stress the wafer may have due to frontside processing, keeping the wafer substantially flat.

IPC Classes  ?

  • H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • C23C 16/24 - Deposition of silicon only

54.

PLASMA MONITORING AND PLASMA DENSITY MEASUREMENT IN PLASMA PROCESSING SYSTEMS

      
Application Number US2023028018
Publication Number 2024/020024
Status In Force
Filing Date 2023-07-18
Publication Date 2024-01-25
Owner
  • LAM RESEARCH CORPORATION (USA)
  • HANYANG UNIVERSITY (Republic of Korea)
Inventor
  • Kim, Hak-Sung
  • Park, Dong-Woon
  • Kim, Heon-Su
  • Kim, Sang-Il
  • Choi, Jindoo
  • Righetti, Fabio

Abstract

A plasma processing system includes a processing chamber including a substrate support. A plasma generator is configured to selectively generate plasma in the processing chamber to treat a substrate arranged on the substrate support. An emitter is configured to transmit first terahertz waves through the plasma in the processing chamber. A detector is configured to receive second terahertz waves corresponding to the first terahertz waves transmitted through the plasma in the processing chamber.

IPC Classes  ?

55.

HIGH ASPECT RATIO CARBON ETCH WITH SIMULATED BOSCH PROCESS

      
Application Number US2023028263
Publication Number 2024/020152
Status In Force
Filing Date 2023-07-20
Publication Date 2024-01-25
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Tan, Zhongkui
  • Li, Jing
  • Su, Xiaofeng
  • Subramanian, Priyadarsini
  • Kamarthy, Gowri Channa

Abstract

Various embodiments herein relate to methods and apparatus for etching a substrate. The substrate is typically a semiconductor substrate. In various implementations, the method involves receiving the substrate in a process chamber, the substrate including a carbon layer and a mask layer positioned over the carbon layer, where the mask layer is patterned to define where the feature will be etched in the carbon layer; and exposing the substrate to a plasma to etch the feature into the carbon layer of the substrate, wherein a composition of the plasma changes over time to provide at least a deposition step, a clear step, and an etch step, and wherein the deposition step, the clear step, and the etch step are cycled with one another until the feature reaches its final depth.

IPC Classes  ?

  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01J 37/32 - Gas-filled discharge tubes

56.

PRECISE FEEDBACK CONTROL OF BIAS VOLTAGE TAILORED WAVEFORM FOR PLASMA ETCH PROCESSES

      
Application Number US2023027295
Publication Number 2024/019901
Status In Force
Filing Date 2023-07-10
Publication Date 2024-01-25
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Choi, Myeong Yeol
  • Wu, Ying
  • Paterson, Alexander Miller

Abstract

A bias electrode and a mid-level electrode are disposed within a substrate support. A lower portion of the substrate support exists between the bias electrode and the mid-level electrode. An upper portion of the substrate support exists between the mid-level electrode and a top surface of the substrate support. A voltage supply system supplies a bias voltage tailored radiofrequency waveform to the bias electrode. A voltage measurement system measures a first voltage on the bias electrode and a second voltage on the mid-level electrode. A controller uses the first voltage, the second voltage, a capacitance of the substrate support lower portion, and a capacitance of the substrate support upper portion to determine a voltage on a top surface of a substrate present on the top surface of the substrate support. The controller conveys the voltage on the top surface of the substrate to the voltage supply system.

IPC Classes  ?

57.

WEDGE SEAL FOR EFEM FRAME AND PANEL SEAMS

      
Application Number US2023027356
Publication Number 2024/019902
Status In Force
Filing Date 2023-07-11
Publication Date 2024-01-25
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Wong, Scott Vernon
  • Jacob, David E.
  • Wassei, Peter R.
  • Senn, Brandon

Abstract

A seal arrangement for an enclosure in a substrate processing system includes an opening defined in a surface of the enclosure and a seam defined between adjacent first and second sections of the surface of the enclosure. The seam is in fluid communication with an interior of the enclosure via the opening. A cutout is defined in an edge of one of the first and second sections adjacent to the seam. A seal is arranged in the cutout and adjacent to the seam between the first and second sections.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

58.

ISOLATION VALVE

      
Application Number US2023023982
Publication Number 2024/015155
Status In Force
Filing Date 2023-05-31
Publication Date 2024-01-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Miller, Aaron Blake
  • Wongsenakhum, Panya

Abstract

In some examples, an isolation valve is provided to isolate gasses and plasmas in semiconductor manufacturing. An example isolation valve comprises a valve body, a valve actuator, and a poppet comprising a polytetrafluoroethylene (PTFE) material, the poppet movable in the valve body by the valve actuator to hold the PTFE material in sealing engagement with an opposing surface without intervention of an O-ring.

IPC Classes  ?

  • F16K 51/02 - Other details not peculiar to particular types of valves or cut-off apparatus specially adapted for high-vacuum installations
  • F16K 25/00 - VALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING - Details relating to contact between valve members and seats
  • F16K 27/02 - Construction of housings; Use of materials therefor of lift valves
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

59.

HIGH-EFFICIENCY LED SUBSTRATE HEATER FOR DEPOSITION APPLICATIONS

      
Application Number US2023025809
Publication Number 2024/015196
Status In Force
Filing Date 2023-06-21
Publication Date 2024-01-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Konkola, Paul
  • Kenane, Boaz

Abstract

An optical array arranged in a pedestal configured to deposit material on a substrate includes a plurality of optical elements, a window, and an array of pinholes. The optical elements are arranged on a printed circuit board (PCB). The optical elements are configured to emit light. The window comprises an optically transparent material covering the optical elements arranged on the PCB. The array of pinholes is disposed between the optical elements and the window. The pinholes are vertically aligned with the optical elements to direct the light emitted by the optical elements through the window to heat the substrate.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

60.

APPARATUS AND METHOD FOR MODULATING SPATIAL DISTRIBUTION OF PLASMA AND ION ENERGY USING FREQUENCY-DEPENDENT TRANSMISSION LINE

      
Application Number US2023027094
Publication Number 2024/015258
Status In Force
Filing Date 2023-07-07
Publication Date 2024-01-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • French, David
  • Leeser, Karl Frederick

Abstract

A system includes a chamber comprising first and second regions. The chamber is configured to produce and contain a plasma in the second region. The system includes a transmission line positioned in the first region. The transmission line includes a plurality of sections, wherein an individual section of the plurality of sections includes one or more L-C filters which have respective cut-off frequencies. The transmission line includes a transmission line input. A signal source electrically is coupled to the transmission line input to feed an input signal to the transmission line input. The one or more L-C filters pass low frequency components of the input signal but localize high frequency components of the input signal to selected sections of the transmission line.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

61.

EDGE RING VOLTAGE AND PHASE MEASUREMENT AND CONTROL FOR SUBSTRATE PROCESSING SYSTEMS

      
Application Number US2023027213
Publication Number 2024/015273
Status In Force
Filing Date 2023-07-10
Publication Date 2024-01-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Paeng, Dong Woo
  • Bise, Ryan
  • Holland, John
  • Robertson, Paul

Abstract

A voltage control system is disclosed and includes: an edge ring configured to be disposed on a substrate support and surround an outer periphery of a substrate; a tunable edge sheath (TES) ring; a generator; and a controller. The TES ring includes: a TES power electrode capacitively coupled to the edge ring and configured to receive a first radio frequency (RF) voltage signal; and a TES probe electrically coupled to the edge ring and configured to detect a second RF voltage signal at the edge ring. The controller is configured to, based on the second RF voltage signal, control the generator to adjust the first RF voltage signal.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

62.

FAST FREQUENCY TRACKING CONTROL FOR RADIOFREQUENCY POWER AMPLIFIERS WITH RAPIDLY CHANGING PLASMA LOADS

      
Application Number US2023027275
Publication Number 2024/015304
Status In Force
Filing Date 2023-07-10
Publication Date 2024-01-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor Park, Sanghyeon

Abstract

A radiofrequency (RF) power amplifier for a plasma processing system includes a switching transistor having a drain terminal, a source terminal, and a gate. The source terminal is connected to a reference ground potential. The RF power amplifier includes a direct current power supply connected to the drain terminal of the switching transistor. The RF power amplifier includes an impedance matching network connected between the drain terminal of the switching transistor and a coil of the plasma processing system. The RF power amplifier includes an electrical parameter measurement device disposed to measure an electrical parameter related to the coil. The RF power amplifier includes a phase delay module that receives a switching feedback signal from the electrical parameter measurement device. The phase delay module applies a phase adjustment to the switching feedback signal to generate a switching control signal that is used to drive the gate of the switching transistor.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

63.

METAL-OXIDE VARISTOR (MOV) BASED SURGE PROTECTION CIRCUIT FOR PLASMA PROCESSING CHAMBER

      
Application Number US2023024052
Publication Number 2024/015158
Status In Force
Filing Date 2023-05-31
Publication Date 2024-01-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Frotanpour, Ali
  • Frederick, Thomas, Lee

Abstract

A system includes a chamber configured to produce and contain a plasma. The system includes a transmission line positioned in the chamber. The transmission line includes a transmission line input and includes an output coupled to a common potential. The system includes a signal source coupled to the transmission line input to feed an input signal to the transmission line. The system includes a surge protection circuit coupled between the transmission line input and the common potential. An impedance of the surge protection circuit is inversely related to a voltage level at the transmission line input.

IPC Classes  ?

64.

LED SUBSTRATE HEATER FOR DEPOSITION APPLICATIONS

      
Application Number US2023025816
Publication Number 2024/015197
Status In Force
Filing Date 2023-06-21
Publication Date 2024-01-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Badam, Vijay Kumar
  • Leeser, Karl Frederick

Abstract

A pedestal configured to deposit material on a substrate includes a stem portion of the pedestal and a base portion of the pedestal mounted to the stem portion of the pedestal. The base portion includes an array of optical elements configured to emit light to optically heat the substrate.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

65.

PLASMA DETECTION IN SEMICONDUCTOR FABRICATION APPARATUSES

      
Application Number US2023069386
Publication Number 2024/015694
Status In Force
Filing Date 2023-06-29
Publication Date 2024-01-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Wang, Yuhou
  • Rajagopal, Ananya
  • Martin, Michael John
  • Albarede, Luc
  • Paterson, Alexander Miller

Abstract

Methods and systems for detecting plasma are provided. In some embodiments, a method for detecting plasma comprises: obtaining data from one or more sensors, wherein the data characterizes a radio frequency (RF) power provided to one or more inductively-coupled plasma (ICP) coils of a semiconductor fabrication apparatus; determining a load impedance at an ICP coil of the one or more ICP coils using the data from the one or more sensors; and determining a presence or an absence of plasma at a location of the semiconductor fabrication apparatus within a vicinity of the ICP coil based on the load impedance at the ICP coil.

IPC Classes  ?

66.

MOBILE SENSOR DEVICES FOR SEMICONDUCTOR FABRICATION EQUIPMENT

      
Application Number US2023026181
Publication Number 2024/010707
Status In Force
Filing Date 2023-06-26
Publication Date 2024-01-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Taylor, Travis R.
  • Lopes, Todd A.
  • Yadav, Pratik Vijay
  • Burkhart, Christopher William

Abstract

Systems and techniques for obtaining various types of sensor information regarding operational aspects of a semiconductor processing tool are disclosed. Such systems and techniques may involve an instrumented wafer that includes one or more different types of sensors, including, for example, pressure sensors, oxygen (or other gas) sensors, humidity sensors, upward- and/or outward-facing imaging sensors or optical sensors, microphone sensors, and so forth.

IPC Classes  ?

  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • B25J 9/16 - Programme controls
  • B25J 11/00 - Manipulators not otherwise provided for
  • B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices

67.

END EFFECTOR

      
Application Number US2023026279
Publication Number 2024/010711
Status In Force
Filing Date 2023-06-27
Publication Date 2024-01-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Blank, Richard
  • Powell, Roy Scott

Abstract

An end effector for supporting a wafer, the end effector having a temperature sensor that is configured to sense a temperature of a wafer supported by the end effector.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • B25J 11/00 - Manipulators not otherwise provided for
  • B25J 15/00 - Gripping heads
  • B25J 19/02 - Sensing devices

68.

IMPROVED PEDESTALS FOR SUBSTRATE PROCESSING SYSTEMS

      
Application Number US2023027063
Publication Number 2024/010887
Status In Force
Filing Date 2023-07-07
Publication Date 2024-01-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Birru, Krishna
  • Kho, Leonard
  • Rao, Shreesha Yogish
  • Gulabal, Vinayakaraddy
  • Kothapalli, Vijay
  • Chen, Xitong

Abstract

A substrate support includes at least three pockets defined along a perimeter of the substrate support, an edge gas groove located on a top surface of the substrate support, and a first clamping groove located radially inward from the edge gas groove on the top surface of the substrate support. Each pocket comprises a narrow portion and a wide portion located radially outward from the narrow portion. The edge gas groove is concentric with the substrate support. The edge gas groove intersects the narrow portion of each pocket. At least thirty through holes are within the edge gas groove and at least one through hole is within the narrow portion of each pocket.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

69.

MULTI-PLENUM GAS MANIFOLDS FOR SUBSTRATE PROCESSING SYSTEMS

      
Application Number US2023025915
Publication Number 2024/010692
Status In Force
Filing Date 2023-06-22
Publication Date 2024-01-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sitharamachari, Janardhan Achari Murkai
  • Kondi, Sushanth
  • Rajagopal, Premkumar

Abstract

A multi-plenum gas manifold is disclosed and includes a monolithic body, a first plenum and a second plenum. The first plenum is arranged within the monolithic body and configured to distribute to or divert from one or more substrate processing stations a first gas species. The first plenum includes a first cavity and a first set of channels extending outward from the first cavity. The second plenum is arranged within the monolithic body isolated from the first plenum and configured to distribute to or divert from the one or more substrate processing stations a second gas species. The second plenum includes a second cavity disposed radially outward of the first cavity. The second set of channels extends outward from the second cavity.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

70.

MOVEABLE EDGE RINGS FOR PLASMA PROCESSING SYSTEMS

      
Application Number US2022043617
Publication Number 2024/005850
Status In Force
Filing Date 2022-09-15
Publication Date 2024-01-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Kimball, Christopher
  • Ehrlich, Darrell
  • Pham, Johnny

Abstract

An edge ring system includes a moveable top ring and a cover ring configured to be arranged above and radially outward of the moveable top ring. The cover ring includes an annular body and a stepped portion extending radially inward from the annular body. The stepped portion is configured to extend above an outer edge of the moveable top ring. An annular recess is defined in an inner radius of the cover ring below the stepped portion. The moveable top ring includes an annular body and a curved outer radius. A ring centering portion is formed in a lower surface of the annular body and configured to center the moveable top ring on a moveable support ring.

IPC Classes  ?

71.

ROBOT ARM WITH VACUUM-COMPATIBLE SEALS AND INTERNAL COOLING FLOW PATHS

      
Application Number US2023026180
Publication Number 2024/006177
Status In Force
Filing Date 2023-06-26
Publication Date 2024-01-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor Blank, Richard M.

Abstract

This disclosure describes robot arm assemblies for use in vacuum environments. Such robot arm assemblies may feature one or more rotational joints that have ferrofluidic seals or other vacuum-compatible seals. Coolant flow path segments may be provided that pass through one or more of the one or more rotational joints so as to allow coolant to be circulated through one or more cooling features located within the robot arm assembly, thereby allowing components within the robot arm assembly, e.g., motors, ferrofluidic seals, sensors, etc., to be actively cooled.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • B25J 9/10 - Programme-controlled manipulators characterised by positioning means for manipulator elements
  • B25J 11/00 - Manipulators not otherwise provided for
  • B25J 19/00 - Accessories fitted to manipulators, e.g. for monitoring, for viewing; Safety devices combined with or specially adapted for use in connection with manipulators

72.

DEPOSITION AND ETCH OF SILICON-CONTAINING LAYER

      
Application Number US2023026231
Publication Number 2024/006211
Status In Force
Filing Date 2023-06-26
Publication Date 2024-01-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Yang, Nuoya
  • Wang, Yuxi
  • Gong, Bo
  • Mckerrow, Andrew John
  • Chang, Ching-Yun

Abstract

A silicon-based film is conformally deposited in a feature and controllably etched using remote plasma. The silicon-based film may be an amorphous silicon layer or a doped silicon layer comprising silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxynitride, or silicon oxycarbonitride. The silicon-based film may be partially etched using remote plasma according to a desired depth and geometry by modulating one or more of the following etch parameters: chamber pressure, substrate temperature, exposure time, RF power, gas composition, and relative concentrations of the gas composition. Methods of and apparatuses for depositing silicon-containing films with tunable film composition and density are also provided, where the silicon-containing film is formed by thermal atomic layer deposition or thermal chemical vapor deposition and treating the silicon-containing film with a densifying gas plasma.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

73.

SYSTEMS AND METHODS FOR WAFER TEMPERATURE MEASUREMENT

      
Application Number US2023026409
Publication Number 2024/006326
Status In Force
Filing Date 2023-06-28
Publication Date 2024-01-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Gao, Songqi
  • Man, Tianxing
  • Scheifele, Devin

Abstract

Various embodiments herein relate to apparatuses and methods for measuring wafer temperature. In some embodiments, an apparatus comprises a first thermocouple disposed in or on a wafer support, a first conductive pad with a first side and a second side, and a second conductive pad with a first side and a second side. In some embodiments, the first thermocouple is operatively connected to the second side of the second conductive pad, the second side of the first conductive pad is adhered to the first side of the second conductive pad, the first side of the first conductive pad is configured to be proximate to a wafer, and the first thermocouple is configured to indicate an absolute temperature of the wafer.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • G01K 7/02 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using thermoelectric elements, e.g. thermocouples

74.

SYSTEMS AND METHODS FOR CALIBRATING RF GENERATORS IN A SIMULTANEOUS MANNER

      
Application Number US2023069005
Publication Number 2024/006675
Status In Force
Filing Date 2023-06-23
Publication Date 2024-01-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Valcore, John, C.
  • Sapio, Adrian, Esteban
  • Wong, Travis, Joseph

Abstract

Systems and methods for calibrating radio frequency (RF) generators are described. One of the methods includes receiving a plurality of analog measurement signals from a plurality of RF sensors to output a plurality of digital signals. The plurality of analog signals are received by an analytical controller. The method further includes calibrating, in a simultaneous manner, the RF generators based on the plurality of digital signals. The RF generators are calibrated by a process controller.

IPC Classes  ?

75.

INTEGRATED HIGH ASPECT RATIO ETCHING

      
Application Number US2023025448
Publication Number 2024/006088
Status In Force
Filing Date 2023-06-15
Publication Date 2024-01-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Tan, Zhongkui
  • Su, Xiaofeng
  • Pan, Yu
  • Ba, Xiaolan
  • Gao, Juwen
  • Li, Ming

Abstract

Methods for etching features into carbon material using a doped tungsten-containing mask, such as a boron-doped tungsten material, to reduce and eliminate redeposition of silicon-containing residues are provided herein. Methods involve depositing a doped tungsten-containing material over the carbon material prior to etching the carbon material, patterning the doped tungsten-containing material to form a doped tungsten-containing mask, and using the patterned doped tungsten-containing mask to etch the carbon material such that the use of a silicon-containing mask during etch of the carbon material is eliminated.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

76.

PARASITIC PLASMA SUPPRESSOR

      
Application Number US2023026435
Publication Number 2024/006342
Status In Force
Filing Date 2023-06-28
Publication Date 2024-01-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Babbar, Yogesh
  • Jafarian-Tehrani, Sam
  • French, David
  • Sakiyama, Yukinori
  • Cheng, Weifeng
  • Martin, Keith Joseph
  • Breninger, Andrew H.
  • Bailey, Curtis W.

Abstract

A parasitic plasma suppressor configured to suppress (or at least reduce) the generation of parasitic plasma outside an intended region, such as suppress the generation of parasitic plasma in areas adjacent a pedestal in a processing chamber of a plasma-enhanced processing system.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

77.

CYCLIC DEVELOPMENT OF METAL OXIDE BASED PHOTORESIST FOR ETCH STOP DETERRENCE

      
Application Number US2023069419
Publication Number 2024/006938
Status In Force
Filing Date 2023-06-29
Publication Date 2024-01-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Li, Da
  • Kim, Ji Yeon
  • Tan, Samantha S.H.
  • Weidman, Timothy William

Abstract

Provided are processes for development of photopatterned metal or metal oxide-based thin film photoresists post-EUV exposure for removal of non-volatile species and deterring etch stop. Repeated cycles of alternating treatment with an etchant and an oxidizing agent; or treatment with an etchant followed by treatment with a wash agent are effective techniques for removal of the undesired unexposed portion of a photoresist.

IPC Classes  ?

  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • H01J 37/32 - Gas-filled discharge tubes

78.

HIGH ASPECT RATIO ETCH WITH A METAL OR METALLOID CONTAINING MASK

      
Application Number US2023025567
Publication Number 2023/249899
Status In Force
Filing Date 2023-06-16
Publication Date 2023-12-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Veber, Gregory Clinton
  • Chuang, Ming-Yuan
  • Puthenkovilakam, Ragesh
  • Reddy, Kapu Sirish
  • Bhadauriya, Sonal
  • Yu, Yongsik
  • Mukhopadhyay, Amit
  • Xu, Qing
  • Wong, Merrett

Abstract

A method for etching features in a stack is provided. A metal or metalloid containing mask is formed over the stack. The stack is etched through the metal or metalloid containing mask, wherein the etching sputters metal or metalloid in the metal or metalloid containing mask and the sputtered metal or metalloid physically redeposits on sidewalls of features etched in the stack as a sputtered metal or metalloid containing passivation layer.

IPC Classes  ?

  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/311 - Etching the insulating layers

79.

PLASMA ENHANCED LOW TEMPERATURE ATOMIC LAYER DEPOSITION OF METALS

      
Application Number US2023069018
Publication Number 2023/250500
Status In Force
Filing Date 2023-06-23
Publication Date 2023-12-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Fox, Alexander Ray
  • Mohimi, Elham
  • Henri, Jon
  • Erickson, Ann
  • Lai, Chiukin Steven
  • Van Cleemput, Patrick August
  • Blakeney, Kyle Jordan
  • Mandia, David Joseph

Abstract

Provided are reduced-temperature plasma enhanced atomic layer deposition processes including application of a thin metal layer by contacting a substrate surface at temperatures of 300 °C or lower with a metal precursor and a plasma of a hydrogen-containing gas source generated directly or remotely.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

80.

MODULATION OF STATION VOLTAGES DURING PLASMA OPERATIONS

      
Application Number US2023025284
Publication Number 2023/244653
Status In Force
Filing Date 2023-06-14
Publication Date 2023-12-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • French, David
  • Sakiyama, Yukinori

Abstract

Various embodiments herein relate to systems, apparatuses, and methods for modulation of station voltages during plasma operations. In some embodiments, a system comprises: a process chamber; at least one variable reactance element operatively coupled to an unpowered electrode of the process chamber; and a controller. In some embodiments, the controller is configured to determine one or more target voltages associated with one or more components. The controller may be configured to determine a value of the at least one variable reactance element based on the one or more target voltages. The controller may be configured to cause the at least one variable reactance element to have the determined value, wherein causing the at least one variable reactance element to have the determined value causes one or more voltages associated with the one or more components of the process chamber to move towards the one or more target voltages.

IPC Classes  ?

81.

TIN PRECURSORS FOR DEPOSITION OF EUV DRY RESIST

      
Application Number US2023068419
Publication Number 2023/245047
Status In Force
Filing Date 2023-06-14
Publication Date 2023-12-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Vrtis, Raymond Nicholas
  • Weidman, Timothy William
  • Coyle, Jason Philip
  • Lin, Qinghuang
  • Wu, Chenghao
  • Touchton, Alexander James

Abstract

The present disclosure relates to precursor compositions for forming irradiation sensitive films. In particular, the disclosure is directed to use of metal-containing precursors having haloaliphatic or unsaturated substituents, or other reactive moieties which advantageously react in the presence of extreme ultraviolet exposure to form resist films having increased etch resistance and/or reduced shrinkage upon processing. Alternatively, the use of metal-containing precursors having haloaliphatic or unsaturated substituents, or other reactive moieties for patterning structures having carbon-containing underlayers may advantageously react with the underlayer to increase adhesion of the resist film to the underlayer.

IPC Classes  ?

  • G03F 7/004 - Photosensitive materials
  • G03F 1/22 - Masks or mask blanks for imaging by radiation of 100 nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masks; Preparation thereof
  • C07F 7/22 - Tin compounds

82.

RADIO FREQUENCY SYSTEM PROTECTION BASED ON TEMPERATURE INFERENCE

      
Application Number US2023020505
Publication Number 2023/239494
Status In Force
Filing Date 2023-04-29
Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • French, David
  • Rangineni, Yaswanth

Abstract

Described is a method for thermally protecting an electronic circuit. In at least one implementation, electronic circuit comprises at least a first component and a second component. In at least one implementation, method comprises measuring a first input voltage and a first input current of the first component. In at least one implementation, method further comprises computing a second input voltage and a second input current of the second component. In at least one implementation, method further comprises computing a first temperature of the first component and a second temperature of the second component, wherein the first temperature is a function of the first input current and the second temperature is a function of the second input current.

IPC Classes  ?

83.

SYSTEMS AND METHODS FOR COMPRESSING A SENSOR-BASED SIGNAL

      
Application Number US2023022789
Publication Number 2023/239541
Status In Force
Filing Date 2023-05-18
Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Valcore, John, C.
  • Sapio, Adrian, Esteban

Abstract

A method for compressing a sensor-based signal is described. The method includes receiving the sensor-based signal and dividing the sensor-based signal into a plurality of portions. Each portion is generated according to a corresponding cycle of a clock signal. The method further includes identifying a plurality of states of each portion of the sensor-based signal and dividing sensor state data for one of the plurality of states into a parameter list and a difference component. The parameter list includes a value common to all of the sensor state data for the one of the plurality of states, and the difference component includes a plurality of values that are offsets from the common value. The method includes packetizing the parameter list within a header of a packet and the difference component within a payload of the packet to compress the sensor state data.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

84.

VACUUM-INSULATED, HEATED REACTOR CONSTRUCTION

      
Application Number US2023022926
Publication Number 2023/239542
Status In Force
Filing Date 2023-05-19
Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Leeser, Karl Frederick
  • Draper, Emile Charles
  • Wu, Yi-De
  • Fu, Gaosheng

Abstract

A sidewall assembly of a substrate processing chamber has a composite structure comprising an inner layer comprised of a first material and an inward, chamber facing surface, an outer layer that is comprised of a second material and encloses the inner layer, and a middle layer disposed around the inner layer between the inner layer and the outer layer that thermally insulates the outer layer from the inner layer.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

85.

SUBSTRATE TEMPERATURE CONTROL WITH INTEGRATED THERMOELECTRIC COOLING SYSTEM

      
Application Number US2023024144
Publication Number 2023/239585
Status In Force
Filing Date 2023-06-01
Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor Tian, Siyuan

Abstract

A temperature control system for a substrate support in a processing chamber includes a manifold assembly configured to supply a liquid coolant at a first temperature from a first channel of a coolant assembly to the processing chamber, supply the liquid coolant at a second temperature from a second channel of the coolant assembly to the processing chamber, and supply return coolant from the processing chamber to the coolant assembly. A thermoelectric module arranged in a flow path between the manifold assembly and the coolant assembly is configured to receive the return coolant from the manifold assembly, either one of heat and cool the return coolant, and supply heated return coolant and cooled return coolant to the coolant assembly.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

86.

IN SITU DECLOGGING IN PLASMA ETCHING

      
Application Number US2023024361
Publication Number 2023/239617
Status In Force
Filing Date 2023-06-02
Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Tan, Zhongkui
  • Su, Xiaofeng
  • Kawaguchi, Mark Naoshi
  • Zhu, Ji
  • Kamarthy, Gowri Channa
  • Liu, Wenchi
  • Subramanian, Priyadarsini
  • Ma, Qiang

Abstract

In semiconductor processing, plasma etching of materials (e.g., of carbon or silicon) to form vertical high aspect ratio recessed features can lead to clogging inside the recessed features due to unwanted deposition of a mask-derived clogging material (e.g., silicon oxide). This is addressed by declogging, which includes etching the clogging material preferably in the same process chamber by contacting the substrate with a halogen source. After the declogging step, plasma etching proceeds further. The declogging and plasma etching steps can be repeated as many times as needed to etch a recessed feature of desired depth.

IPC Classes  ?

  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks

87.

RF AND DC FREQUENCY AND PHASE LOCKED PULSED EDGE TILT CONTROL SYSTEM

      
Application Number US2023067460
Publication Number 2023/240003
Status In Force
Filing Date 2023-05-25
Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor Jafarian-Tehrani, Seyed, Jafar

Abstract

A method performed within a plasma chamber. The method including providing a first power signal to an electrostatic chuck (ESC). The method including providing a second power signal to an edge ring. The method including measuring an amplitude of a current signal occurring at an interface between the ESC and the edge ring. The method including adjusting one or more parameters of the first power signal and the second power signal to achieve a minimum amplitude of the current signal. The method including determining a phase relationship between a phase of the current signal and a phase of a reference signal to determine a direction of ion tilt at the interface. The method including adjusting at least one parameter of the second power signal to achieve a predetermined angle of the ion tilt at the interface based on the phase relationship and the amplitude of the current signal.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

88.

LIQUID COOLING PLATE FOR COOLING OF DIELECTRIC WINDOW OF A SUBSTRATE PROCESSING SYSTEM

      
Application Number US2023022353
Publication Number 2023/239531
Status In Force
Filing Date 2023-05-16
Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Issavi, Hanry
  • Ronne, Allan
  • Antolik, Jerrell, K.

Abstract

A substrate processing system includes a processing chamber including a dielectric window and a substrate support. A gas delivery device is located in the processing chamber between the dielectric window and the substate support. An inductive coil arranged outside of the processing chamber adjacent to the dielectric window. A cooling plate is arranged between the inductive coil and the dielectric window and configured to flow liquid coolant.

IPC Classes  ?

89.

CHUCKING SYSTEM WITH SILANE COUPLING AGENT

      
Application Number US2023024038
Publication Number 2023/239574
Status In Force
Filing Date 2023-05-31
Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Xu, Lin
  • Srinivasan, Satish
  • Daugherty, John
  • Singh, Harmeet

Abstract

A chuck system for supporting a substrate in a plasma processing chamber is provided. A base plate comprises a substrate support region and a shoulder surrounding the substrate support region. A protective coating is on a surface of the base plate, wherein the protective coating covers at least part of the shoulder. A layer of a silane coupling agent is on the protective coating.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01J 37/32 - Gas-filled discharge tubes

90.

REMOVAL OF METAL SALT PRECIPITATES IN AN ELECTROPLATING TOOL

      
Application Number US2023020862
Publication Number 2023/235099
Status In Force
Filing Date 2023-05-03
Publication Date 2023-12-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Martin, Daniel James
  • Ong, Boon Kang
  • Sigamani, Nirmal Shankar
  • Wilmot, Frederick Dean
  • Chua, Lee

Abstract

Examples are disclosed that relate to the removal of metal salt precipitates from within a circulating loop of an electroplating tool. In one example method, during a processing phase of operation, a metal salt solution is flowed through a circulating loop at a process temperature to deposit a metal on a substrate. The metal salt solution comprises at least a metal cation and a counter ion. In a precipitate removal phase of operation, the metal salt solution is heated to a temperature higher than the process temperature. The heated metal salt solution is then flowed through the circulating loop for a duration to dissolve metal salt precipitates of the metal salt solution within the circulating loop. The metal salt solution is then cooled to the process temperature.

IPC Classes  ?

  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • C09D 7/40 - Additives

91.

REDUCED TEMPERATURE ETCHING OF DOPED SILICON OXIDE

      
Application Number US2023023270
Publication Number 2023/235188
Status In Force
Filing Date 2023-05-23
Publication Date 2023-12-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Church, Jonathan
  • Subramonium, Pramod
  • Yilmaz, Mehmet Fatih
  • Vegh, Joseph James
  • Chi, Hao
  • Hoang, John

Abstract

Examples are disclosed that relate to etching features in a layer of silicon oxide doped with an etch rate-modifying dopant. One example provides a method of performing a memory device fabrication process. The method comprises placing a substrate in a processing chamber of a processing tool, the substrate comprising a first structure comprising alternating layers in a mold stack for a 3D memory structure, and the substrate also comprising a second structure comprising a silicon oxide layer doped with an etch rate-modifying dopant. The method further comprises controlling the processing tool to perform an etching cycle comprising etching at least a portion of a channel hole in the first structure of the substrate and at least a portion of a hole in the second structure of the substrate.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

92.

CUSTOMIZING ETCH SELECTIVITY AND HIGH ASPECT RATIO FEATURE LOADING THROUGH MULTI-LEVEL PULSING SCHEMES UTILIZING SINUSOIDAL AND CUSTOM RF WAVEFORMS

      
Application Number US2023067483
Publication Number 2023/235675
Status In Force
Filing Date 2023-05-25
Publication Date 2023-12-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sriraman, Saravanapriyan
  • Paterson, Alexander

Abstract

A method for performing a plasma etch process in a process chamber is provided, including: applying a source radiofrequency (RF) signal to a top electrode of the process chamber; applying a bias RF signal to a lower electrode of the process chamber; wherein the bias RF signal has two or more pulsed duty cycles, including a first duty cycle having a first sinusoidal waveform at a first frequency and pulsed at a first voltage level, and a second duty cycle having a custom waveform pulsed at a second voltage level, the custom waveform consisting of a second sinusoidal waveform at a second frequency that is combined with a non- sinusoidal waveform.

IPC Classes  ?

93.

IN SITU TREATMENT OF MOLYBDENUM OXYHALIDE BYPRODUCTS IN SEMICONDUCTOR PROCESSING EQUIPMENT

      
Application Number US2023023023
Publication Number 2023/229953
Status In Force
Filing Date 2023-05-19
Publication Date 2023-11-30
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Wongsenakhum, Panya
  • Collins, Joshua
  • Gopinath, Sanjay
  • Madrigal, Kevin
  • Lafferty, William
  • Griffiths, Matthew, Bertram, Edward
  • Mandia, David, Joseph

Abstract

Provided are methods for increasing the efficiency of atomic layer deposition of molybdenum metal by in situ cleaning and decontamination of molybdenum oxyhalide precursor delivery lines to a deposition chamber. The cleaning process may take place by pre-treating the delivery lines with at least one surface passivating agent and/or by periodically treating the delivery lines with at least one corrosion inhibitor. Also provided are methods of removing oxidation from a deposited molybdenum film.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metal halides
  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

94.

SINGLE WAFER REACTOR, LOW TEMPERATURE, THERMAL SILICON NITRIDE DEPOSITION

      
Application Number US2023023633
Publication Number 2023/230296
Status In Force
Filing Date 2023-05-25
Publication Date 2023-11-30
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Miller, Aaron Blake
  • Henri, Jon
  • Durbin, Aaron
  • Goza, Steven
  • Srinivasan, Easwar
  • Gupta, Awnish
  • Van Schravendijk, Bart J.
  • Savchak, Oksana
  • Wei, Fengyan

Abstract

Methods and apparatuses for depositing silicon nitride using a thermal atomic layer deposition process are provided. The temperature of a substrate during deposition is higher than the surround process chamber walls to reduce deposition on the chamber walls, reducing the frequency of chamber cleans.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/34 - Nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

95.

UNDERLAYER WITH BONDED DOPANTS FOR PHOTOLITHOGRAPHY

      
Application Number US2023066718
Publication Number 2023/230406
Status In Force
Filing Date 2023-05-08
Publication Date 2023-11-30
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Kanakasabapathy, Siva Krishnan
  • Varadarajan, Bhadri
  • Mahorowala, Arpan Pravin
  • Singhal, Durgalakshmi A

Abstract

Examples are disclosed that relate to use of extreme ultraviolet (EUV)-absorbing photoelectron-emissive dopants that are bonded to atoms in a hydrogen-contributing photosensitive underlayer for a photoresist. One example provides a method of forming a hydrogen-contributing photosensitive underlayer on a substrate. The method comprises exposing the substrate to a dopant precursor and a hydrocarbon precursor, the dopant precursor comprising an extreme ultraviolet (EUV)-absorbing photoelectron-emissive dopant bonded within a carbon-containing polymerizable molecule. The method further comprises exposing the substrate to a radical species formed by a plasma. The method further comprises forming the hydrogen-contributing photosensitive underlayer on the substrate from the dopant precursor and the hydrocarbon precursor by reaction of the dopant precursor and the hydrocarbon precursor with the radical species.

IPC Classes  ?

  • G03F 7/004 - Photosensitive materials
  • G03F 7/11 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
  • G03F 7/20 - Exposure; Apparatus therefor

96.

YTTRIA COATING FOR PLASMA PROCESSING CHAMBER COMPONENTS

      
Application Number US2023022492
Publication Number 2023/229892
Status In Force
Filing Date 2023-05-17
Publication Date 2023-11-30
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Dederick, Jeremiah Michael
  • Srinivasan, Satish
  • Xu, Lin
  • Daugherty, John

Abstract

A component of a plasma processing chamber is provided. A yttria coating is formed on a surface of a component body, wherein the yttria coating is deposited by aerosol deposition and is annealed, wherein the yttria coating is at least 95% pure yttria by weight.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

97.

THROTTLE VALVE FOR SUBSTRATE PROCESSING SYSTEMS

      
Application Number US2023022909
Publication Number 2023/229936
Status In Force
Filing Date 2023-05-19
Publication Date 2023-11-30
Owner LAM RESEARCH CORPORATION (USA)
Inventor Borth, Andrew

Abstract

A valve of a substrate processing system includes a throttle plate configured to adjust gas flow through a gas line. An outer actuator is arranged outside of the gas line. An inner actuator is arranged inside of the gas line and connected to the throttle plate. The outer actuator is magnetically coupled to the inner actuator. Movement the outer actuator causes movement of the inner actuator relative to the gas line to adjust a position of the throttle plate.

IPC Classes  ?

  • F16K 1/22 - Lift valves, i.e. cut-off apparatus with closure members having at least a component of their opening and closing motion perpendicular to the closing faces with pivoted closure members with pivoted discs or flaps with axis of rotation crossing the valve member, e.g. butterfly valves
  • F16K 31/08 - Operating means; Releasing devices magnetic using a magnet using a permanent magnet
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

98.

HYBRID ATOMIC LAYER DEPOSITION

      
Application Number US2023023418
Publication Number 2023/230170
Status In Force
Filing Date 2023-05-24
Publication Date 2023-11-30
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Gupta, Awnish
  • Van Schravendijk, Bart J.
  • Henri, Jon
  • Savchak, Oksana
  • Wei, Fengyan
  • Srinivasan, Easwar
  • Miller, Aaron Blake
  • Austin, Dustin Zachary

Abstract

Methods and apparatuses for depositing silicon nitride using a hybrid atomic layer deposition technique are provided. Methods and apparatuses for forming halogen-free undercoats in a process chamber using a halogen-free aminosilane precursor are provided. Methods and apparatuses for forming silicon oxynitride using a single-wafer chamber are provided herein. Methods and apparatus also include forming graded silicon oxynitride using cyclic deposition and in-situ nitridation and/or oxidation techniques.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/34 - Nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

99.

REPLACEMENT SIGNALING SEAL

      
Application Number US2023021985
Publication Number 2023/224870
Status In Force
Filing Date 2023-05-12
Publication Date 2023-11-23
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Tucker, Jeremy
  • Leeser, Karl Frederick
  • Hausmann, Dennis

Abstract

A seal for a substrate processing system includes a body comprised of a base material, an outer surface, and a marker material disposed at least one of throughout the base material within the body of the seal, in an outer edge region of the seal, in a coating disposed on the outer surface of the seal, and in an interior region of the seal. The marker material is different from the base material.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

100.

HARDMASK FOR HIGH ASPECT RATIO DIELECTRIC ETCH AT CRYO AND ELEVATED TEMPERATURES

      
Application Number US2023022327
Publication Number 2023/224950
Status In Force
Filing Date 2023-05-16
Publication Date 2023-11-23
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lill, Thorsten Bernd
  • Puthenkovilakam, Ragesh
  • Reddy, Kapu Sirish
  • Hoang, John
  • Shen, Meihua
  • Wu, Hui-Jung
  • Bhadauriya, Sonal
  • Chi, Hao
  • Routzahn, Aaron Lynn
  • Yu, Anthony Sky
  • Roberts, Francis Sloan

Abstract

Various embodiments herein relate to methods, apparatus, and systems for etching high aspect ratio features in dielectric material. The dielectric material is etched using a multi-layer or graded hardmask having at least two different compositions. Different etching regimes are used when the different portions of the hardmask are exposed. For example, a feature may be etched to a first depth at a first temperature while an upper portion of the hardmask is exposed, and then etched to a final depth at a second temperature while a lower portion of the hardmask is exposed, the second temperature being higher than the first temperature.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
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