Lam Research Corporation

United States of America

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H01J 37/32 - Gas-filled discharge tubes 1,097
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components 623
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber 507
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 437
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1.

MONOLITHIC ANISOTROPIC SUBSTRATE SUPPORTS

      
Application Number 17769430
Status Pending
Filing Date 2020-10-20
First Publication Date 2024-04-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Hollingsworth, Joel
  • Lingampalli, Ramkishan
  • Leeser, Karl
  • Topping, Stephen
  • Baker, Noah Elliot

Abstract

A substrate support includes a monolithic anisotropic body, which includes first, second and intermediate layers. The first layer is formed of a first material and disposed therein are RF and clamping electrodes. The second layer is formed of the first material or a second material and disposed therein is a heating element. The intermediate layer is formed of a different material than the first and second layers, such that at least one of: a thermal energy conductivity of the intermediate layer is different than a thermal energy conductivity of at least one of the first or second materials; or an electrical energy conductivity of the intermediate layer is different than an electrical conductivity of at least one of the first or second materials. Either the intermediate layer is disposed between the first and second layers or the second layer is disposed between the first and intermediate layers.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

2.

POLYMERIC COATING FOR SEMICONDUCTOR PROCESSING CHAMBER COMPONENTS

      
Application Number 18546174
Status Pending
Filing Date 2022-02-25
First Publication Date 2024-04-11
Owner Lam Research Corporation (USA)
Inventor
  • Song, Yuanping
  • Pham, Johnny
  • Song, Yiwei
  • Xu, Lin
  • Kimball, Christopher

Abstract

A component in a semiconductor processing chamber is provided. An electrically conductive semiconductor or metal body has a CTE of less than 10.0×10−6/K. An intermediate layer is disposed over at least one surface of the body, the intermediate layer comprising a fluoropolymer. A perfluoroalkoxy alkane (PFA) layer is disposed over the intermediate layer to form the component.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • B05D 1/02 - Processes for applying liquids or other fluent materials performed by spraying

3.

Multiple State Pulsing for High Aspect Ratio Etch

      
Application Number 18011505
Status Pending
Filing Date 2022-06-16
First Publication Date 2024-04-11
Owner Lam Research Corporation (USA)
Inventor
  • Joi, Aniruddha
  • Dole, Nikhil
  • Wong, Merrett
  • Hudson, Eric
  • Sheth, Jay

Abstract

A method for performing an etch process on a substrate includes applying a bias signal and a source signal to an electrode of a plasma processing system. The bias signal and the source signal are pulsed RF signals that together define a repeated pulsed RF cycle, wherein each pulsed RF cycle sequentially includes a first state, a second state, a third state, and a fourth state. The power level of the bias signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state. The power level of the source signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state.

IPC Classes  ?

4.

SYSTEMS AND METHODS FOR ETCHING A HIGH ASPECT RATIO STRUCTURE

      
Application Number 18011837
Status Pending
Filing Date 2021-12-22
First Publication Date 2024-04-11
Owner Lam Research Corporation (USA)
Inventor
  • Dole, Nikhil
  • Yanagawa, Takumi
  • Hudson, Eric A.
  • Wong, Merrett
  • Joi, Aniruddha

Abstract

A method for etching a stack is described. The method includes etching a first nitrogen-containing layer of the stack by applying a non-metal gas and discontinuing the application of the non-metal gas upon determining that a first oxide layer is reached. The first oxide layer is under the first nitrogen-containing layer. The method further includes etching the first oxide layer by applying a metal-containing gas. The application of the metal-containing gas is discontinued upon determining that a second nitrogen-containing layer will be reached. The second nitrogen-containing layer is situated under the first oxide layer. The method includes etching the second nitrogen-containing layer by applying the non-metal gas.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

5.

MATCHING PRE-PROCESSING AND POST-PROCESSING SUBSTRATE SAMPLES

      
Application Number 18262145
Status Pending
Filing Date 2022-01-19
First Publication Date 2024-04-04
Owner Lam Research Corporation (USA)
Inventor
  • Lu, Yu
  • Jin, Yansha
  • Tan, Zhongkui
  • Tetiker, Mehmet Derya

Abstract

Various embodiments herein relate to systems, methods, and media for matching pre-processing and post-processing substrate samples. In some embodiments, a computer program product for matching pre-processing and post-processing substrate samples is provided, the computer program product comprising a non-transitory computer-readable on which is provided computer-executable instructions for: receiving a plurality of samples associated with a first set of dimensions characterizing a pre-processed substrate and a plurality of samples associated with a second set of dimensions characterizing a post-processed substrate; receiving an identification of one of the pre-processed dimensions and one of the post-processed dimensions that are to be matched; generating a first probability distribution of samples for the identified pre-processed dimension and a second probability distribution of samples for the identified post-processed dimension; and matching samples of the identified pre-processed dimension to samples of the identified post-processed dimension based on the first probability distribution and the second probability distribution.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G06T 7/33 - Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods
  • G06T 7/35 - Determination of transform parameters for the alignment of images, i.e. image registration using statistical methods
  • G06T 7/62 - Analysis of geometric attributes of area, perimeter, diameter or volume

6.

Showerhead Faceplate Having Flow Apertures Configured for Hollow Cathode Discharge Suppression

      
Application Number 18529576
Status Pending
Filing Date 2023-12-05
First Publication Date 2024-04-04
Owner Lam Research Corporation (USA)
Inventor
  • Selep, Michael John
  • Breiling, Patrick G.
  • Leeser, Karl Frederick
  • Thomas, Timothy Scott
  • Kamp, David William
  • Donnelly, Sean M.

Abstract

A faceplate of a showerhead has a bottom side that faces a plasma generation region and a top side that faces a plenum into which a process gas is supplied during operation of a substrate processing system. The faceplate includes apertures formed through the bottom side and openings formed through the top side. Each of the apertures is formed to extend through a portion of an overall thickness of the faceplate to intersect with at least one of the openings to form a corresponding flow path for process gas through the faceplate. Each of the apertures has a cross-section that has a hollow cathode discharge suppression dimension in at least one direction. Each of the openings has a cross-section that has a smallest cross-sectional dimension that is greater than the hollow cathode discharge suppression dimension.

IPC Classes  ?

7.

REMOVING METAL CONTAMINATION FROM SURFACES OF A PROCESSING CHAMBER

      
Application Number 18534027
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-04-04
Owner Lam Research Corporation (USA)
Inventor
  • Yu, Jengyi
  • Tan, Samantha Siamhwa
  • Heo, Seongjun
  • Yuan, Ge
  • Kanakasabapathy, Siva Krishnan

Abstract

A method for cleaning surfaces of a substrate processing chamber includes a) supplying a first gas selected from a group consisting of silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), a hydrocarbon (CxHy where x and y are integers) and molecular chlorine (Cl2), boron trichloride (BCl3), and thionyl chloride (SOCl2); b) striking plasma in the substrate processing chamber to etch the surfaces of the substrate processing chamber; c) extinguishing the plasma and evacuating the substrate processing chamber; d) supplying a second gas including fluorine species; e) striking plasma in the substrate processing chamber to etch the surfaces of the substrate processing chamber; and f) extinguishing the plasma and evacuating the substrate processing chamber.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

8.

MULTI-PLATE ELECTROSTATIC CHUCKS WITH CERAMIC BASEPLATES

      
Application Number 18534182
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-04-04
Owner Lam Research Corporation (USA)
Inventor
  • Wang, Feng
  • Gaff, Keith
  • Kimball, Christopher

Abstract

An electrostatic chuck for a substrate processing system is provided. The electrostatic chuck includes: a top plate configured to electrostatically clamp to a substrate and formed of ceramic; an intermediate layer disposed below the top plate; and a baseplate disposed below the intermediate layer and formed of ceramic. The intermediate layer bonds the top plate to the baseplate.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01J 37/244 - Detectors; Associated components or circuits therefor
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

9.

ATOMIC LAYER DEPOSITION WITH MULTIPLE UNIFORMLY HEATED CHARGE VOLUMES

      
Application Number 18265825
Status Pending
Filing Date 2021-12-14
First Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Kadam, Nitin
  • Miller, Aaron Blake
  • Patil, Naveen
  • Wongsenakhum, Panya
  • Butail, Gorun
  • Thombare, Shruti

Abstract

Multiple charge volumes (CVs) are used to supply a reactant and an inert gas at each processing chamber to perform atomic layer deposition (ALD) on substrates. A series of pulses of the reactant can be supplied at a high flow rate from two CVs during a dose step, which extends dose time. The inert gas can be supplied at an equal starting pressure from first and second CVs at first and second purge steps. A heated pulse valve manifold (PVM) minimizes temperature variations of process gases supplied from the PVM to respective processing chamber during ALD. The PVM preheats the process gases before the process gases enter the respective CVs in the PVM. The PVM includes additional supplemental heaters above and below the CVs to maintain the temperature of the process gases within the CVs. The PVM can be rapidly cooled before performing maintenance, which reduces downtime.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate

10.

PROFILE TWISTING CONTROL IN DIELECTRIC ETCH

      
Application Number 18013493
Status Pending
Filing Date 2022-06-16
First Publication Date 2024-03-28
Owner Lam Research Corporation (USA)
Inventor
  • Mackie, Neil Macaraeg
  • Lai, Kevin
  • Li, Chen
  • Zhang, He

Abstract

A substrate processing apparatus includes a vacuum chamber with upper and lower electrodes and a processing zone for processing a substrate using plasma. The upper electrode includes a surface that is substantially parallel to a surface of the substrate when the substrate is positioned in the chamber. The apparatus includes at least one magnetic field source configured to generate one or more active magnetic fields through the processing zone, and a controller coupled to the at least one magnetic field source and the upper electrode. The controller is configured to apply RF power between the upper and lower electrodes to generate the plasma using a process gas. The controller controls the current through the at least one magnetic field source during the processing of the substrate, where the current is based on a target value corresponding to at least one characteristic of the one or more active magnetic fields.

IPC Classes  ?

11.

HIGH POWER CABLE FOR HEATED COMPONENTS IN RF ENVIRONMENT

      
Application Number 18526215
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-03-28
Owner Lam Reseach Corporation (USA)
Inventor
  • Jafarian-Tehrani, Seyed Jafar
  • Finnegan, Kenneth Walter
  • O'Brien, Sean
  • Tong, Benson Q.

Abstract

A substrate support includes an edge ring, a heater element arranged within the edge ring, a ceramic layer, at least one heating element arranged within the ceramic layer, and a cable configured to provide power from a power source to the heater element and the at least one heating element. The cable includes a first plurality of wires connected to the heater element, a second plurality of wires connected to the at least one heating element, a filter module, and an isolation device connected only to the first plurality of wires between the filter module and the heater element. The first and second pluralities of wires are twisted together within the filter module. The isolation device is configured to compensate for a resonance frequency generated during operation of the heater element and the at least one heating element.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01B 9/00 - Power cables
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H03H 7/01 - Frequency selective two-port networks

12.

CAPACITANCE MEASUREMENT WITHOUT DISCONNECTING FROM HIGH POWER CIRCUIT

      
Application Number 18522090
Status Pending
Filing Date 2023-11-28
First Publication Date 2024-03-21
Owner Lam Research Corporation (USA)
Inventor
  • Kapoor, Sunil
  • Frederick, Thomas

Abstract

Methods and apparatus for measuring capacitance are disclosed.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/52 - Controlling or regulating the coating process
  • G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
  • G01R 13/02 - Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 23/64 - Impedance arrangements

13.

INTEGRATED WAFER BOW MEASUREMENTS

      
Application Number 18525539
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-03-21
Owner Lam Research Corporation (USA)
Inventor
  • Arora, Rajan
  • Souza, Michael
  • Tang, Wayne
  • Kabouzi, Yassine
  • Feng, Ye

Abstract

In some examples, a wafer bow measurement system comprises a measurement unit including: a wafer support assembly to impart rotational movement to a measured wafer supported in the measurement unit; an optical sensor; a calibration standard to calibrate the optical sensor; a linear stage actuator to impart linear direction of movement to the optical sensor; a wafer centering sensor to determine a centering of the measured wafer supported in the measurement unit; and a wafer alignment sensor to determine an alignment of the measured wafer supported in the measurement unit.

IPC Classes  ?

  • G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
  • G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment

14.

SYSTEMS AND METHODS FOR PULSE WIDTH MODULATED DOSE CONTROL

      
Application Number 18526411
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-03-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor Gregor, Mariusch

Abstract

A substrate processing system for treating a substrate includes N manifolds, Y groups of injector assemblies, and a dose controller, where Y and N are integers greater than one. Each of the Y groups of injector assemblies includes N injector assemblies located in a processing chamber. Each of the N injector assemblies in each group of injector assemblies is in fluid communication with one of the N manifolds, respectively, and includes a valve including an inlet and an outlet. The dose controller is configured to control pulse widths output to the Y groups of injector assemblies to provide temporal dosing of the substrate

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • B05B 1/14 - Nozzles, spray heads or other outlets, with or without auxiliary devices such as valves, heating means with strainers in or outside the outlet opening
  • B05B 1/30 - Nozzles, spray heads or other outlets, with or without auxiliary devices such as valves, heating means designed to control volume of flow, e.g. with adjustable passages
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

15.

MACHINE-LEARNING IN MULTI-STEP SEMICONDUCTOR FABRICATION PROCESSES

      
Application Number 18256665
Status Pending
Filing Date 2021-12-14
First Publication Date 2024-03-21
Owner Lam Research Corporation (USA)
Inventor
  • Zhang, Yan
  • Feng, Ye
  • Talukder, Dipongkar
  • Bonde, Jeffrey D.
  • Woo, Weng Foong
  • Thimmavajjula, Karthik
  • Luque, Jorge

Abstract

Methods and systems for using a time-series of spectra to identify endpoint of a multi-step semiconductor fabrication processes such as multi-step deposition and multi-step etch processes. One method includes accessing a virtual carpet (e.g., a machine learning model) that is formed from a time-series of spectra for the multi-step processes collected during a training operation. During production, in-situ time-series of spectra are compared to the virtual carpet as part of end pointing of multi-step fabrication processes.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G06N 20/00 - Machine learning
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

16.

DETERMINATION OF RECIPES FOR MANUFACTURING SEMICONDUCTOR DEVICES

      
Application Number 18385823
Status Pending
Filing Date 2023-10-31
First Publication Date 2024-03-21
Owner Lam Research Corporation (USA)
Inventor
  • Sawlani, Kapil Umesh
  • Basu, Atashi
  • Fried, David Michael
  • Danek, Michal
  • Alden, Emily Ann

Abstract

Methods, systems, and computer programs are presented for determining the recipe for manufacturing a semiconductor with the use of machine learning (ML) to accelerate the definition of recipes. One general aspect includes a method that includes an operation for performing experiments for processing a component, each experiment controlled by a recipe, from a set of recipes, that identifies parameters for manufacturing equipment. The method further includes an operation for performing virtual simulations for processing the component, each simulation controlled by one recipe from the set of recipes. An ML model is obtained by training an ML algorithm using experiment results and virtual results from the virtual simulations. The method further includes operations for receiving specifications for a desired processing of the component, and creating, by the ML model, a new recipe for processing the component based on the specifications.

IPC Classes  ?

  • G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
  • G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
  • G06F 30/337 - Design optimisation

17.

ELECTROCHEMICAL ASSEMBLY FOR FORMING SEMICONDUCTOR FEATURES

      
Application Number 18261485
Status Pending
Filing Date 2022-01-28
First Publication Date 2024-03-14
Owner Lam Research Corporation (USA)
Inventor
  • Mayer, Steven T.
  • Thorkelsson, Kari

Abstract

Methods, apparatuses, and systems for forming deposited features on workpieces are provided herein. Generally, the techniques herein employ a deposition head to define an electrical field that facilitates electrochemical deposition. Other systems and controllers can be employed, which can assist in aligning or positioning the deposition head in proximity to a workpiece and controlling the size and location of the deposited feature.

IPC Classes  ?

  • C25D 7/12 - Semiconductors
  • C25D 5/02 - Electroplating of selected surface areas
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 21/12 - Process control or regulation

18.

ALTERNATING ETCH AND PASSIVATION PROCESS

      
Application Number 18505043
Status Pending
Filing Date 2023-11-08
First Publication Date 2024-03-14
Owner Lam Research Corporation (USA)
Inventor
  • Heo, Seongjun
  • Yu, Jengyi
  • Liang, Chen-Wei
  • Jensen, Alan J.
  • Tan, Samantha S.H.

Abstract

Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.

IPC Classes  ?

  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

19.

SYSTEMS AND METHODS FOR HOMOGENOUS INTERMIXING OF PRECURSORS IN ALLOY ATOMIC LAYER DEPOSITION

      
Application Number 18519290
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-03-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Fisher, Ilanit
  • Humayun, Raashina
  • Danek, Michal
  • Van Cleemput, Patrick
  • Thombare, Shruti

Abstract

A showerhead includes a plurality of plenums and a plurality of through holes positioned in the plurality of plenums. The plenums are stacked in a sequential order in an axial direction perpendicular to a semiconductor substrate. The plenums extend radially fully across the semiconductor substrate. The plenums are disjoint from each other and are configured to respectively supply a first metal precursor, a second metal precursor, and a reactant via the respective plenums without intermixing the first metal precursor, the second metal precursor, and the reactant in the plenums. The through holes of the respective plenums are arranged in a radial direction, which is perpendicular to the axial direction, in the same sequential order as the sequential order of the plenums. The through holes of the plenums open along a flat surface at a bottom of the showerhead. The flat surface extends radially fully across the bottom of the showerhead.

IPC Classes  ?

  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers

20.

SPATIALLY AND DIMENSIONALLY NON-UNIFORM CHANNELLED PLATE FOR TAILORED HYDRODYNAMICS DURING ELECTROPLATING

      
Application Number 18261734
Status Pending
Filing Date 2022-01-19
First Publication Date 2024-03-07
Owner Lam Research Corporation (USA)
Inventor
  • Banik, Ii, Stephen J.
  • Graham, Gabriel Hay
  • Buckalew, Bryan L.
  • Rash, Robert
  • Chua, Lee Peng
  • Wilmot, Frederick Dean
  • Lin, Chien-Chieh

Abstract

An ionically resistive ionically permeable element for use in an electroplating apparatus includes ribs to tailor hydrodynamic environment proximate a substrate during electroplating. In one implementation, the ionically resistive ionically permeable element includes a channeled portion that is at least coextensive with a plating face of the substrate, and a plurality of ribs extending from the substrate-facing surface of the channeled portion towards the substrate. Ribs include a first plurality of ribs of full maximum height and a second plurality of ribs of smaller maximum height than the full maximum height. In one implementation the ribs of smaller maximum height are disposed such that the maximum height of the ribs gradually increases in a direction from one edge of the element to the center of the element.

IPC Classes  ?

  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 3/38 - Electroplating; Baths therefor from solutions of copper
  • C25D 3/60 - Electroplating; Baths therefor from solutions of alloys containing more than 50% by weight of tin
  • C25D 17/06 - Suspending or supporting devices for articles to be coated
  • C25D 21/10 - Agitating of electrolytes; Moving of racks
  • C25D 21/12 - Process control or regulation

21.

EDGE SEAL FOR LOWER ELECTRODE ASSEMBLY

      
Application Number 18377371
Status Pending
Filing Date 2023-10-06
First Publication Date 2024-03-07
Owner Lam Research Corporation (USA)
Inventor
  • Schaefer, David
  • Chhatre, Ambarish
  • Gaff, Keith William
  • Kim, Sung Je
  • Lai, Brooke Mesler

Abstract

An edge seal for sealing an outer surface of a lower electrode assembly configured to support a semiconductor substrate in a plasma processing chamber, the lower electrode assembly including an annular groove defined between a lower member and an upper member of the lower electrode assembly. The edge seal includes an elastomeric band configured to be arranged within the groove, the elastomeric band having an annular upper surface, an annular lower surface, an inner surface, and an outer surface. When the elastomeric band is in an uncompressed state, the outer surface of the elastomeric band is concave. When the upper and lower surfaces are axially compressed at least 1% such that the elastomeric band is in a compressed state, an outward bulging of the outer surface is not greater than a predetermined distance. The predetermined distance corresponds to a maximum outer diameter of the elastomeric band in the uncompressed state.

IPC Classes  ?

  • F16J 15/02 - Sealings between relatively-stationary surfaces
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H02N 13/00 - Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect

22.

PROCESSING PARTS USING SOLID-STATE ADDITIVE MANUFACTURING

      
Application Number 18270481
Status Pending
Filing Date 2022-01-06
First Publication Date 2024-02-22
Owner Lam Research Corporaton (USA)
Inventor
  • Hazarika, Pankaj Jyoti
  • Sarobol, Pylin
  • Schick, Matthew Brian
  • Torbatisarraf, Seyedalireza

Abstract

Semiconductor-processing chamber components and methods for making the components are presented. One component includes a base including a metallic material, a metal matrix composite (MMC) layer, and a dielectric layer. The MMC layer at least partially covers the base, and the MMC layer comprises a metallic material as a continuous phase and a non-metallic material as a disperse phase. Further, the MMC layer is formed on the base using solid-state additive manufacturing (SSAM). The dielectric layer is made of a non-metallic material and is directly on the MMC layer.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • B33Y 80/00 - Products made by additive manufacturing
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

23.

DOPED OR UNDOPED SILICON CARBIDE DEPOSITION AND REMOTE HYDROGEN PLASMA EXPOSURE FOR GAPFILL

      
Application Number 18501395
Status Pending
Filing Date 2023-11-03
First Publication Date 2024-02-22
Owner Lam Research Corporation (USA)
Inventor
  • Yuan, Guangbi
  • Narkeviciute, Ieva
  • Gong, Bo
  • Varadarajan, Bhadri N.

Abstract

A doped or undoped silicon carbide (SiCxOyNz) film can be deposited in one or more features of a substrate for gapfill. After a first thickness of the doped or undoped silicon carbide film is deposited in the one or more features, the doped or undoped silicon carbide film is exposed to a remote hydrogen plasma under conditions that cause a size of an opening near a top surface of each of the one or more features to increase, where the conditions can be controlled by controlling treatment time, treatment frequency, treatment power, and/or remote plasma gas composition. Operations of depositing additional thicknesses of silicon carbide film and performing a remote hydrogen plasma treatment are repeated to at least substantially fill the one or more features. Various time intervals between deposition and plasma treatment may be added to modulate gapfill performance.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01J 37/32 - Gas-filled discharge tubes

24.

CONTROL OF WAFER BOW IN MULTIPLE STATIONS

      
Application Number 18494710
Status Pending
Filing Date 2023-10-25
First Publication Date 2024-02-15
Owner Lam Research Corporation (USA)
Inventor
  • Augustyniak, Edward
  • French, David
  • Kapoor, Sunil
  • Sakiyama, Yukinori
  • Thomas, George

Abstract

A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

25.

SYSTEMS AND TECHNIQUES FOR OPTICAL MEASUREMENT OF THIN FILMS

      
Application Number 18260713
Status Pending
Filing Date 2022-01-04
First Publication Date 2024-02-15
Owner Lam Research Corporation (USA)
Inventor
  • Yang, Liu
  • Li, Mengping
  • Ghongadi, Shantinath
  • Pfau, Andrew James

Abstract

Methods provided herein may include illuminating a region on a wafer within a semiconductor processing tool, the wafer having a layer of a material that is at least semi-transparent to light and has a measurable extinction coefficient, and the region being a first fraction of the wafer's surface, detecting light reflected off the material and off a surface underneath the material using one or more detectors and generating optical data corresponding to the detected light, generating a metric associated with a property of the material on the wafer by applying the optical data to a transfer function that relates the optical data to the metric associated with the property of the material on the wafer, determining an adjustment to one or more processing parameters for a processing module, and performing or modifying a processing operation in the processing module according to the adjusted one or more processing parameters.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01N 21/84 - Systems specially adapted for particular applications

26.

PRECURSORS FOR DEPOSITION OF MOLYBDENUM-CONTAINING FILMS

      
Application Number 18379397
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-02-15
Owner Lam Research Corporation (USA)
Inventor Blakeney, Kyle Jordan

Abstract

Molybdenum-containing films are deposited on semiconductor substrates using reactions of molybdenum-containing precursors in ALD and CVD processes. In some embodiments, the precursors can be used for deposition of molybdenum metal films with low levels of incorporation of carbon and nitrogen. In some embodiments, the films are deposited using fluorine-free precursors in a presence of exposed silicon-containing layers without using etch stop layers. The precursor, in some embodiments, is a compound that includes molybdenum, at least one halogen that forms a bond with molybdenum, and at least one organic ligand that includes an element selected from the group consisting of N, O, and S, that forms a bond with molybdenum. In another aspect, the precursor is a molybdenum compound with at least one sulfur-containing ligand, and preferably no molybdenum-carbon bonds.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds

27.

CARRIER RING DESIGNS FOR CONTROLLING DEPOSITION ON WAFER BEVEL/EDGE

      
Application Number 18494756
Status Pending
Filing Date 2023-10-25
First Publication Date 2024-02-15
Owner Lam Research Corporation (USA)
Inventor
  • Janicki, Michael John
  • Williams, Brian Joseph

Abstract

Various carrier ring designs and configurations to control an amount of deposition at a wafer's front side and bevel edge are provided. The carrier ring designs can control the amount of deposition at various locations of the wafer while deposition is performed on the wafer's back side, with no deposition desired on the front side of the wafer. These locations include front side, edge, and back side of bevel; and front and back side of the wafer. Edge profiles of the carrier rings are designed to control flow of process gases, flow of front side purge gas, and plasma effects. In some designs, through holes are added to the carrier rings to control gas flows. The edge profiles and added features can reduce or eliminate deposition at the wafer's front side and bevel edge.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01J 37/32 - Gas-filled discharge tubes

28.

ADAPTIVE MODEL TRAINING FOR PROCESS CONTROL OF SEMICONDUCTOR MANUFACTURING EQUIPMENT

      
Application Number 18258497
Status Pending
Filing Date 2021-12-13
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor
  • Talukder, Dipongkar
  • Zhang, Yan
  • Feng, Ye
  • Bonde, Jeffrey D.

Abstract

Various embodiments herein relate to systems and methods for adaptive model training. In some embodiments, a computer program product for adaptive model training is provided, the computer program product comprising a non-transitory computer readable medium on which is provided computer-executable instructions for: receiving, from a plurality of process chambers, ex situ data associated with wafers fabricated using the process chambers and in situ measurements, wherein a first machine learning model is used to predict the ex situ data using the in situ measurements; calculating a metric indicating an error associated with the first machine learning model; determining whether to update the first machine learning model; and generating a second machine learning model using the ex situ data and the in situ measurements.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/66 - Testing or measuring during manufacture or treatment

29.

MOLYBDENUM DEPOSITION IN FEATURES

      
Application Number 18258973
Status Pending
Filing Date 2022-01-03
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor
  • Na, Jeong-Seok
  • Thombare, Shruti Vivek
  • Hsieh, Yao-Tsung
  • Mandia, David Joseph
  • Lai, Chiukin Steven

Abstract

Provided are deposition processes including deposition of a thin, protective Mo layer using a molybdenum chloride (MoClx) precursor. This may be followed by Mo deposition to fill the feature using a molybdenum oxyhalide (MoOyXz) precursor. The protective Mo layer enables Mo fill using an MoOyXz precursor without oxidation of the underlying surfaces. Also provided are in-situ clean processes in which a MoClx precursor is used to remove oxidation from underlying surfaces prior to deposition. Subsequent deposition using the MoClx precursor may deposit an initial layer and/or fill a feature.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

30.

REAL-TIME CONTROL OF TEMPERATURE IN A PLASMA CHAMBER

      
Application Number 18488950
Status Pending
Filing Date 2023-10-17
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor Jing, Changyou

Abstract

Systems and methods for real-time control of temperature within a plasma chamber are described. One of the methods includes sensing a voltage in real time of a rail that is coupled to a voltage source. The voltage source supplies a voltage to multiple heater elements of the plasma chamber. The voltage that is sensed is used to adjust one or more duty cycles of corresponding one or more of the heater elements. The adjusted one or more duty cycles facilitate achieving and maintaining a temperature value within the plasma chamber over time.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)

31.

NON-ELASTOMERIC, NON-POLYMERIC, NON-METALLIC MEMBRANE VALVES FOR SEMICONDUCTOR PROCESSING EQUIPMENT

      
Application Number 18489829
Status Pending
Filing Date 2023-10-18
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor
  • Gregor, Mariusch
  • Panagopoulos, Theodoros
  • Lill, Thorsten Bernd

Abstract

Non-elastomeric, non-polymeric, non-metallic membrane valves for use in high-vacuum applications are disclosed. Such valves are functional even when the fluid-control side of the valve is exposed to a sub-atmospheric pressure field which may generally act to collapse/seal traditional elastomeric membrane valves.

IPC Classes  ?

  • F16K 99/00 - Subject matter not provided for in other groups of this subclass

32.

PROTECTIVE COATING FOR ELECTROSTATIC CHUCKS

      
Application Number 18490265
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor
  • Topping, Stephen
  • Burkhart, Vincent E.

Abstract

An ElectroStatic Chuck (ESC) including a chucking surface having at least a portion covered with a coating of silicon oxide (SiO2), silicon nitride (Si3N4) or a combination of both. The coating can be applied in situ a processing chamber of a substrate processing tool and periodically removed and re-applied in situ to create fresh coating.

IPC Classes  ?

  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

33.

REPLACEABLE AND/OR COLLAPSIBLE EDGE RING ASSEMBLIES FOR PLASMA SHEATH TUNING INCORPORATING EDGE RING POSITIONING AND CENTERING FEATURES

      
Application Number 18377141
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor
  • Sanchez, Alejandro
  • Ford, Grayson
  • Ehrlich, Darrell
  • Alwan, Aravind
  • Leung, Kevin
  • Contreras, Anthony
  • Han, Zhumin
  • Casaes, Raphael
  • Wu, Joanna

Abstract

A first edge ring for a substrate support is provided. The first edge ring includes an annular-shaped body and one or more lift pin receiving elements. The annular-shaped body is sized and shaped to surround an upper portion of the substrate support. The annular-shaped body defines an upper surface, a lower surface, a radially inner surface, and a radially outer surface. The one or more lift pin receiving elements are disposed along the lower surface of the annular-shaped body and sized and shaped to receive and provide kinematic coupling with top ends respectively of three or more lift pins.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

34.

SELECTIVE PROCESSING WITH ETCH RESIDUE-BASED INHIBITORS

      
Application Number 18485749
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor
  • Sharma, Kashish
  • Kim, Taeseung
  • Tan, Samantha S.H.
  • Hausmann, Dennis M.

Abstract

Selective deposition of a sacrificial material on a semiconductor substrate, the substrate having a surface with a plurality of regions of substrate materials having different selectivities for the sacrificial material, may be conducted such that substantial deposition of the sacrificial material occurs on a first region of the substrate surface, and no substantial deposition occurs on a second region of the substrate surface. Deposition of a non-sacrificial material may then be conducted on the substrate, such that substantial deposition of the non-sacrificial material occurs on the second region and no substantial deposition of the non-sacrificial material occurs on the first region. The sacrificial material may then be removed such that net deposition of the non-sacrificial material occurs substantially only on the second region.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

35.

CONTROL OF METALLIC CONTAMINATION FROM METAL-CONTAINING PHOTORESIST

      
Application Number 18550733
Status Pending
Filing Date 2022-03-31
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor
  • Peter, Daniel
  • Tan, Samantha Siamhwa
  • Yu, Jengyi
  • Li, Da
  • Xue, Meng
  • Choi, Wook
  • Kim, Ji Yeon
  • Jensen, Alan J.
  • Labib, Shahd Hassan
  • Lee, Younghee
  • Zhao, Hongxiang

Abstract

Various techniques for controlling metal-containing contamination on a semiconductor substrate are provided herein. Such techniques may involve one or more of a post-development bake treatment, a chemical treatment, a plasma treatment, a light treatment, and a backside and bevel edge clean. The techniques may be combined as desired for a particular application. In many cases, the techniques are used to address metal-containing contamination that is generated during a photoresist development operation.

IPC Classes  ?

  • G03F 7/40 - Treatment after imagewise removal, e.g. baking
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma

36.

PROCESS TOOL FOR DRY REMOVAL OF PHOTORESIST

      
Application Number 18377245
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor
  • Dictus, Dries
  • Weidman, Timothy William

Abstract

Dry development or dry removal of metal-containing extreme ultraviolet radiation (EUV) photoresist is performed in atmospheric conditions or performed in process tools without vacuum equipment. Dry removal of the metal-containing EUV photoresist may be performed under atmospheric pressure or over-atmospheric pressure. Dry removal of the metal-containing EUV photoresist may be performed with exposure to an air environment or with non-oxidizing gases. A process chamber or module may be modified or integrated to perform dry removal of the metal-containing EUV photoresist with baking, wafer cleaning, wafer treatment, or other photoresist processing function. In some embodiments, the process chamber for dry removal of the metal-containing EUV photoresist includes a heating assembly for localized heating of a semiconductor substrate and a movable discharge nozzle for localized gas delivery above the semiconductor substrate.

IPC Classes  ?

  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor

37.

ELECTROSTATIC CHUCK FOR USE IN SEMICONDUCTOR PROCESSING

      
Application Number 18481886
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor Gomm, Troy Alan

Abstract

A semiconductor substrate processing apparatus includes a vacuum chamber having a processing zone in which a semiconductor substrate may be processed, a process gas source in fluid communication with the vacuum chamber for supplying a process gas into the vacuum chamber, a showerhead module through which process gas from the process gas source is supplied to the processing zone of the vacuum chamber, and a substrate pedestal module. The substrate pedestal module includes a pedestal made of ceramic material having an upper surface configured to support a semiconductor substrate thereon during processing, a stem made of ceramic material, and coplanar electrodes embedded in the platen, the electrodes including an outer RF electrode and inner electrostatic clamping electrodes, the outer RF electrode including a ring-shaped electrode and a radially extending lead extending from the ring-shaped electrode to a central portion of the platen, wherein the ceramic material of the platen and the electrodes comprise a unitary body made in a single sintering step.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

38.

SYSTEMS AND METHODS FOR REVERSE PULSING

      
Application Number 18480495
Status Pending
Filing Date 2023-10-03
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Long, Maolin
  • Tan, Zhongkui
  • Wu, Ying
  • Fu, Qian
  • Paterson, Alex
  • Drewery, John

Abstract

Systems and methods for reverse pulsing are described. One of the methods includes receiving a digital signal having a first state and a second state. The method further includes generating a transformer coupled plasma (TCP) radio frequency (RF) pulsed signal having a high state when the digital signal is in the first state and having a low state when the digital signal is in the second state. The method includes providing the TCP RF pulsed signal to one or more coils of a plasma chamber, generating a bias RF pulsed signal having a low state when the digital signal is in the first state and having a high state when the digital signal is in the second state, and providing the bias RF pulsed signal to a chuck of the plasma chamber.

IPC Classes  ?

39.

TIN OXIDE THIN FILM SPACERS IN SEMICONDUCTOR DEVICE MANUFACTURING

      
Application Number 18482197
Status Pending
Filing Date 2023-10-06
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Smith, David Charles
  • Wise, Richard
  • Mahorowala, Arpan
  • Van Cleemput, Patrick A.
  • Van Schravendijk, Bart J.

Abstract

Thin tin oxide films can be used in semiconductor device manufacturing. In one implementation, a method of processing a semiconductor substrate includes: providing a semiconductor substrate having a plurality of protruding features residing on an etch stop layer material, and an exposed tin oxide layer in contact with both the protruding features and the etch stop layer material, where the tin oxide layer covers both sidewalls and horizontal surfaces of the protruding features; and then completely removing the tin oxide layer from horizontal surfaces of the semiconductor substrate without completely removing the tin oxide layer residing at the sidewalls of the protruding features. Next, the protruding features can be removed without completely removing the tin oxide layer that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/311 - Etching the insulating layers
  • C23C 16/40 - Oxides
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/56 - After-treatment
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

40.

HIGH SELECTIVITY, LOW STRESS, AND LOW HYDROGEN CARBON HARDMASKS IN LOW-PRESSURE CONDITIONS WITH WIDE GAP ELECTRODE SPACING

      
Application Number 18256893
Status Pending
Filing Date 2021-12-13
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Antony, Abbin
  • Meng, Xin
  • Chen, Xinyi
  • Sonti, Sreeram
  • Reddy, Kapu Sirish

Abstract

Provided herein are methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate by providing a wide gap electrode spacing in low-pressure conditions. A wide gap electrode may facilitate control of parasitic plasmas in low-pressure conditions, thereby enabling formation of high selectivity, low stress, and low-hydrogen AHMs. The AHM may then be used to etch features into underlying layers of the substrate.

IPC Classes  ?

  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/56 - After-treatment
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/26 - Deposition of carbon only

41.

INTEGRATION OF FULLY ALIGNED VIA THROUGH SELECTIVE DEPOSITION AND RESISTIVITY REDUCTION

      
Application Number 18555507
Status Pending
Filing Date 2022-04-15
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Hausmann, Dennis M.
  • Ramnani, Pankaj Ghanshyam
  • Sharma, Kashish
  • Lemaire, Paul C.
  • Mahorowala, Arpan Pravin

Abstract

Methods and apparatuses for an integration scheme for forming a fully aligned via using selective deposition of graphene on metal surfaces and selective deposition of an inhibitor layer on exposed barrier surfaces prior to depositing dielectric material are provided.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C23C 16/26 - Deposition of carbon only
  • B05D 1/00 - Processes for applying liquids or other fluent materials
  • C23C 16/34 - Nitrides
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01J 37/32 - Gas-filled discharge tubes

42.

SACRIFICIAL PROTECTION LAYER FOR ENVIRONMENTALLY SENSITIVE SURFACES OF SUBSTRATES

      
Application Number 17310303
Status Pending
Filing Date 2020-01-28
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Sirard, Stephen M.
  • Limary, Ratchana
  • Pan, Yang
  • Hymes, Diane

Abstract

A method for protecting a surface of a substrate during processing includes a) providing a solution forming a co-polymer having a ceiling temperature; b) dispensing the solution onto a surface of the substrate to form a sacrificial protective layer, wherein the co-polymer is kinetically trapped to allow storage at a temperature above the ceiling temperature; c) exposing the substrate to ambient conditions for a predetermined period; and d) de-polymerizing the sacrificial protective layer by using stimuli selected from a group consisting of ultraviolet (UV) light and heat.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

43.

Clamshell cable guide

      
Application Number 29801355
Grant Number D1012041
Status In Force
Filing Date 2021-07-28
First Publication Date 2024-01-23
Grant Date 2024-01-23
Owner LAM RESEARCH CORPORATION (USA)
Inventor Borth, Andrew

44.

METAL ETCH

      
Application Number 18257085
Status Pending
Filing Date 2021-12-06
First Publication Date 2024-01-18
Owner Lam Research Corporation (USA)
Inventor
  • Fan, Yiwen
  • Yang, Wenbing
  • Lin, Ran
  • Tan, Samantha Siamhwa
  • Weidman, Timothy William
  • Mukherjee, Tamal

Abstract

A method for etching a metal containing material is provided. The metal containing material is exposed to a halogen containing fluid or plasma to convert at least some of the metal containing material into a metal halide material. The metal halide material is exposed to a ligand containing fluid or plasma, wherein at least some of the metal halide material is formed into a metal halide ligand complex. At least some of the metal halide ligand complex is vaporized.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

45.

COATED CONDUCTOR FOR HEATER EMBEDDED IN CERAMIC

      
Application Number 18246849
Status Pending
Filing Date 2021-09-28
First Publication Date 2024-01-18
Owner Lam Research Corporation (USA)
Inventor
  • Hollingsworth, Joel
  • Lingampalli, Ramkishan Rao
  • Hazarika, Pankaj

Abstract

Various embodiments herein relate to techniques for fabricating a platen for use in a semiconductor processing apparatus, as well as the platens and intermediate structures produced by such techniques. For example, such techniques may include depositing a coating on a heater to form a coated heater, where the heater includes a metal wire on which the coating is formed; placing the coated heater in powder; consolidating the powder into a cohesive mass to form a powder-based composite; and sintering the powder-based composite to form the platen, where the platen includes the heater embedded in sintered ceramic material. The coating on the heater may act to protect the heater from chemical attack from carbon- and/or oxygen-containing compounds that may be present during sintering. The platen may be part of a pedestal that, once fabricated, may be installed in a semiconductor processing apparatus.

IPC Classes  ?

  • H05B 3/28 - Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor embedded in insulating material
  • C04B 35/64 - Burning or sintering processes

46.

METHODS AND APPARATUS FOR CONTROLLING PLASMA IN A PLASMA PROCESSING SYSTEM

      
Application Number 18475006
Status Pending
Filing Date 2023-09-26
First Publication Date 2024-01-18
Owner Lam Research Corporation (USA)
Inventor
  • Valcore, Jr., John C.
  • Lyndaker, Bradford J.

Abstract

Methods and apparatus for processing a substrate in a multi-frequency plasma processing chamber are disclosed. The base RF signal pulses between a high power level and a low power level. Each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined power level and a second predefined power level as the base RF signal pulses. Alternatively or additionally, each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined RF frequency and a second predefined RF frequency as the base RF signal pulses. Techniques are disclosed for ascertaining in advance of production time the first and second predefined power levels and/or the first and second predefined RF frequencies for the non-base RF signals.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • B44C 1/22 - Removing surface-material, e.g. by engraving, by etching
  • H03L 5/00 - Automatic control of voltage, current, or power

47.

C-shroud Modification For Plasma Uniformity Without Impacting Mechanical Strength Or Lifetime Of The C-shroud

      
Application Number 18042198
Status Pending
Filing Date 2022-01-14
First Publication Date 2024-01-11
Owner Lam Research Corporation (USA)
Inventor
  • Mankidy, Pratik
  • Kim, Jaewon
  • Singh, Harmeet
  • Li, Ming

Abstract

A confinement ring for use in a plasma processing chamber includes an upper horizontal section, a vertical section, and a lower horizontal section. The upper horizontal section extends between an upper inner radius and an outer radius of the confinement ring, The lower horizontal section extends between an lower inner radius and the outer radius of the confinement ring, and includes an extension section that extends to the lower inner radius. A top surface of the lower horizontal section provides for an angle down toward the lower inner radius. The vertical section is disposed between the outer radius and an inside radius of the confinement ring. The vertical section connects the upper horizontal section to the lower horizontal section of the confinement ring.

IPC Classes  ?

48.

COLLABORATIVE ROBOT SYSTEM ON A MOBILE CART WITH A CHAMBER DOCKING SYSTEM

      
Application Number 17908235
Status Pending
Filing Date 2021-03-02
First Publication Date 2024-01-11
Owner Lam Research Corporation (USA)
Inventor
  • Brand, Vitali
  • Gadepally, Kamesh Venkata
  • Zhao, Jiawei
  • Marohl, Dan
  • Vaghela, Niraj
  • Liu, Heng
  • Walker, Alexander James
  • Blum, Zachary Jake
  • Clark, Matthew Christopher
  • Kim, Jessica Jeana

Abstract

A robot system for servicing a semiconductor tool includes a cart frame. An arm support frame is fixed to the cart frame and is coupled to a robot arm. An arm frame is connected by hinges to the arm support frame at a first end and to a fixture connect interface at a second end. The fixture connect interface connects to a docking fixture of the semiconductor tool. An arm locking mechanism is attached to the arm support frame for locking the arm frame, when rotated, to an extended position or a folded position. The fixture connect interface connects the cart frame to the semiconductor tool, when the arm frame is locked in the extended position.

IPC Classes  ?

  • B25J 11/00 - Manipulators not otherwise provided for
  • B25J 5/00 - Manipulators mounted on wheels or on carriages
  • B25J 9/16 - Programme controls

49.

LOW RESISTANCE PULSED CVD TUNGSTEN

      
Application Number 18253196
Status Pending
Filing Date 2021-11-16
First Publication Date 2024-01-04
Owner Lam Research Corporation (USA)
Inventor
  • Pan, Yu
  • Hsieh, Yao-Tsung
  • Ba, Xiaolan
  • Gao, Juwen

Abstract

Provided herein are methods of depositing tungsten (W) films without depositing a nucleation layer. In certain embodiments, the methods involve depositing a conformal layer of boron (B) on a substrate. The substrate generally includes a feature to be filled with tungsten with the boron layer conformal to the topography of the substrate including the feature. The reducing agent layer is then exposed to a continuous flow of hydrogen and pulses of fluorine-containing tungsten precursor in a pulsed CVD process. The conformal boron layer is converted to a conformal tungsten layer.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C23C 16/14 - Deposition of only one other metal element
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

50.

PRECURSOR DISPENSING SYSTEMS WITH LINE CHARGE VOLUME CONTAINERS FOR ATOMIC LAYER DEPOSITION

      
Application Number 18037146
Status Pending
Filing Date 2021-12-01
First Publication Date 2024-01-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sangplug, Saangrut
  • Durbin, Aaron
  • Murugaiyan, Murthi
  • Miller, Aaron Blake
  • Qiu, Huatan
  • Bhimarasetti, Gopinath
  • Rai, Vikrant
  • Wilson, Vincent

Abstract

A precursor dispensing system includes a source, an ampoule, a first valve, a second valve, a line charge volume container and a controller. The source supplies a liquid precursor. The ampoule receives the liquid precursor from the source. The first valve adjusts flow of the liquid precursor from the source to the ampoule. The second valve adjusts flow of a precursor vapor from the ampoule to a showerhead of a substrate processing chamber. The line charge volume container is connected to a conduit and stores a charge of the precursor vapor, where the conduit extends from the ampoule to the second valve. The controller: opens the first valve and closes the second valve to precharge the line charge volume container; and during a dose operation, open the second valve to dispense a bulk amount of the precursor vapor from the line charge volume container and into the substrate processing chamber.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

51.

BACKSIDE DEPOSITION AND LOCAL STRESS MODULATION FOR WAFER BOW COMPENSATION

      
Application Number 18255287
Status Pending
Filing Date 2021-11-19
First Publication Date 2024-01-04
Owner Lam Research Corporation (USA)
Inventor
  • Huang, Yanhui
  • Chandrasekar, Vignesh
  • Bapat, Shriram Vasant
  • Vintila, Adriana

Abstract

In A bow compensation layer deposited on a backside of a bowed semiconductor substrate may modulate stress to mitigate asymmetric bowing. In some implementations, the bow compensation layer may be formed by varying precursor concentration adjacent to the backside according to a non-linear mass flow profile along the bowed semiconductor substrate. Precursor flow may be varied in a manner to match or substantially match a parabolic or polynomial function. In some implementations, a showerhead pedestal may vary precursor flow along the bowed semiconductor substrate, where the showerhead pedestal is divided into multiple zones for delivering a first gas to a first zone of a plenum volume and a second gas to a second zone of the plenum volume.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01J 37/32 - Gas-filled discharge tubes

52.

PEDESTAL INCLUDING SEAL

      
Application Number 18035200
Status Pending
Filing Date 2021-11-09
First Publication Date 2023-12-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor Gage, Christopher

Abstract

A pedestal assembly for a substrate processing system includes a pedestal including a pedestal plate with a plurality of gas through holes and a stem extending downwardly from the pedestal plate. The plurality of gas through holes extend from a first surface of the pedestal plate to a second surface of the pedestal plate at a location radially outside of the stem. A collar is arranged around the stem of the pedestal and openings of the plurality of gas through holes are located on the second surface of the pedestal. The collar defines an annular volume between the collar and the stem of the pedestal. An upwardly facing surface of the collar makes a surface-to-surface seal with the second surface of the pedestal.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

53.

REFLECTOMETER TO MONITOR SUBSTRATE MOVEMENT

      
Application Number 18244905
Status Pending
Filing Date 2023-09-11
First Publication Date 2023-12-28
Owner Lam Research Corporation (USA)
Inventor
  • Pape, Eric A.
  • Opaits, Dmitry
  • Luque, Jorge
  • Bonde, Jeffrey D.
  • Tian, Siyuan

Abstract

Various embodiments include a reflectometer and a reflectometry system for monitoring movements of a substrate, such as a silicon wafer. In one embodiment, a reflectometry system monitors and controls conditions associated with a substrate disposed within a process chamber. The process chamber includes a substrate-holding device having an actuator mechanism to control movement of the substrate with respect to the substrate-holding device. The reflectometry system includes a light source configured to emit a beam of light directed at the substrate, collection optics configured to receive light reflected from the substrate by the beam of light directed at the substrate and output a signal related to one or more conditions associated with the substrate, and a processor configured to process the signal and direct the actuator mechanism to control the movement of the substrate with respect to the substrate-holding device based on the signal. Other devices and methods are disclosed.

IPC Classes  ?

  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • G01S 17/48 - Active triangulation systems, i.e. using the transmission and reflection of electromagnetic waves other than radio waves
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • G01N 21/956 - Inspecting patterns on the surface of objects
  • G01B 21/24 - Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for testing the alignment of axes for testing the alignment of axes
  • G01B 21/12 - Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring diameters of objects while moving

54.

PHOTORESIST DEVELOPMENT WITH ORGANIC VAPOR

      
Application Number 18254787
Status Pending
Filing Date 2021-12-03
First Publication Date 2023-12-28
Owner Lam Research Corporation (USA)
Inventor
  • Dictus, Dries
  • Wu, Chenghao
  • Hansen, Eric Calvin
  • Weidman, Timothy William

Abstract

Development of resists are useful, for example, to form a patterning mask in the context of high-resolution patterning. Development can be accomplished using an organic vapor such as a carboxylic acid. In some implementations, the organic vapor is trifluoroacetic acid. In some implementations, the organic vapor is hexafluoro-acetylacetone. A metal-containing resist film such as an EUV-sensitive organo-metal oxide may be deposited on a semiconductor substrate using a dry or wet deposition technique. The metal-containing resist film on the semiconductor substrate may be developed using the organic vapor, or residue of metal-containing resist material formed on surfaces of a process chamber may be removed using the organic vapor.

IPC Classes  ?

  • C09K 13/08 - Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
  • G03F 7/004 - Photosensitive materials
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

55.

TOOL FOR PREVENTING OR SUPPRESSING ARCING

      
Application Number 18463647
Status Pending
Filing Date 2023-09-08
First Publication Date 2023-12-28
Owner Lam Research Corporation (USA)
Inventor
  • Sakiyama, Yukinori
  • Leeser, Karl Frederick
  • Burkhart, Vincent

Abstract

A tool that suppresses or altogether eliminates arcing between a substrate pedestal and substrate is disclosed. The tool includes a processing chamber, a substrate pedestal for supporting a substrate within the processing chamber, and shower head positioned within the processing chamber. The shower head is arranged to dispense gas that is turned into a plasma, which develops a DC self-bias potential on the substrate surface. The tool also includes a bias control system configured to induce a DC potential to the substrate at a deliberate target electrical potential.

IPC Classes  ?

  • C23C 16/52 - Controlling or regulating the coating process
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

56.

APPARATUSES AND METHODS FOR AVOIDING ELECTRICAL BREAKDOWN FROM RF TERMINAL TO ADJACENT NON-RF TERMINAL

      
Application Number 18465113
Status Pending
Filing Date 2023-09-11
First Publication Date 2023-12-28
Owner Lam Research Corporation (USA)
Inventor
  • Kim, Hyungjoon
  • Kapoor, Sunil
  • Leeser, Karl
  • Burkhart, Vince

Abstract

An isolation system includes an input junction coupled to one or more RF power supplies via a match network for receiving radio frequency (RF) power. The isolation system further includes a plurality of channel paths connected to the input junction for distributing the RF power among the channel paths. The isolation system includes an output junction connected between each of the channel paths and to an electrode of a plasma chamber for receiving portions of the distributed RF power to output combined power and providing the combined RF power to the electrode. Each of the channel paths includes bottom and top capacitors for blocking a signal of the different type than that of the RF power. The isolation system avoids a risk of electrical arcing created by a voltage difference between an RF terminal and a non-RF terminal when the terminals are placed proximate to each other.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

57.

MULTI-LAYER AND MULTI-RINGED SEALS FOR PREVENTING PERMEATION AND LEAK-BY OF FLUID

      
Application Number 18031206
Status Pending
Filing Date 2021-10-18
First Publication Date 2023-12-28
Owner LAM RESEACH CORPORATION (USA)
Inventor
  • Leeser, Karl Frederick
  • Streng, Bradley Taylor
  • Linebager, Jr., Nick Ray

Abstract

A seal to prevent fluid through a first interface between the seal and a first body, includes first and second band members and a bridge member. The first band member defines a first band seal surface on first side of the first band member. The first band member is configured to provide a first fluid seal with the first body when compressed to the first body. The second band member defines a second band seal surface on a first side of the second band member. The second band member is configured to provide a second fluid seal with the first body when compressed to the first body. The first band member and the second band member at least partially define a cavity between the first band member and the second band member. The bridge member extends through the cavity and connects the first band member to the second band member.

IPC Classes  ?

  • F16J 15/00 - Sealings
  • F16J 15/10 - Sealings between relatively-stationary surfaces with solid packing compressed between sealing surfaces with non-metallic packing

58.

MULTl-STATION TOOL WITH ROTATABLE TOP PLATE ASSEMBLY

      
Application Number 18250510
Status Pending
Filing Date 2021-10-26
First Publication Date 2023-12-28
Owner Lam Research Corporation (USA)
Inventor
  • Leeser, Karl Frederick
  • Lavoie, Adrien

Abstract

Semiconductor processing tools with multi-station processing chambers are provided that include a rotational bearing mechanism that allows a top plate assembly thereof to be rotated during maintenance and service operations. In some implementations, a vertical displacement mechanism may be provided that may be used to transition the top plate assembly between a first configuration and a second configuration, with the top plate assembly being rotatable in at least the second configuration.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

59.

CERAMIC COMPONENT WITH CHANNELS

      
Application Number 18034635
Status Pending
Filing Date 2021-11-01
First Publication Date 2023-12-21
Owner Lam Research Corporation (USA)
Inventor
  • Kerns, John Michael
  • Wetzel, David Joseph
  • Xu, Lin
  • Hazarika, Pankaj
  • Detert, Douglas
  • Liu, Lei
  • Pape, Eric A.

Abstract

A method for forming a component for a plasma processing chamber is provided. An internal mold is provided. An external mold is provided around the internal mold. The external mold is filled with a ceramic powder, wherein the ceramic powder surrounds the internal mold. The ceramic powder is sintered to form a solid part. The solid part is removed from the external mold.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C04B 41/00 - After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
  • C04B 35/01 - Shaped ceramic products characterised by their composition; Ceramic compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides

60.

PROCESS KIT DE-BUBBLING

      
Application Number 18037537
Status Pending
Filing Date 2021-11-30
First Publication Date 2023-12-21
Owner Lam Research Corporation (USA)
Inventor
  • Fortner, James Isaac
  • Mayer, Steven T.
  • Banik, Stephen J.

Abstract

In some examples, an electroplating apparatus is provided for depositing a metal layer on a substrate. An example electroplating apparatus comprises a plating cell to receive a plating solution, an electrode, a counter electrode, a substrate holding fixture, a resistive element, and a de-bubbler device supportable rotatably adjacent the resistive element to generate or direct a flow of plating solution through the resistive element to release trapped bubbles.

IPC Classes  ?

  • C25D 21/04 - Removal of gases or vapours
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating

61.

CARRIER RING FOR FLOATING TCP CHAMBER GAS PLATE

      
Application Number 18026785
Status Pending
Filing Date 2021-09-14
First Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Peng, Gordon
  • Chhatre, Ambarish
  • Rosslee, Craig
  • Marohl, Dan
  • Setton, David

Abstract

A gas distribution assembly for a processing chamber in a substrate processing system includes a gas plate including a plurality of holes configured to supply a gas mixture into an interior of the processing chamber and a carrier ring configured to support the gas plate. The carrier ring includes an annular body and a radially inwardly projecting portion. The radially inwardly projecting portion has a first inner diameter and the annular body has a second inner diameter greater than the first inner diameter, the radially inwardly projecting portion defines a ledge, and the gas plate is arranged on the ledge of the carrier ring. A dielectric window is arranged on the gas plate above the gas plate and the carrier ring such that the gas plate is supported between the carrier ring and the dielectric window.

IPC Classes  ?

62.

SUBSTRATE PROCESSING SYSTEM TOOLS FOR MONITORING, ASSESSING AND RESPONDING BASED ON HEALTH INCLUDING SENSOR MAPPING AND TRIGGERED DATALOGGING

      
Application Number 18034834
Status Pending
Filing Date 2021-11-03
First Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Freese, Bridget Hill
  • Baldwin, Scott
  • Tang, Justin
  • Chau, Raymond
  • Raabe, Thor Andreas
  • Steger, Robert J.
  • Zhu, Lin

Abstract

A health monitoring, assessing and response system includes an interface and a controller. The interface is configured to receive a signal from a sensor disposed in a substrate processing system. The controller includes a health index module. The health index module is configured to perform an algorithm including: obtaining a window and a boundary threshold; monitoring the signal output from the sensor; determining whether the signal has crossed the boundary threshold; updating a health index component, where the health index component is a binary value and transitioned between HIGH and LOW values in response to the signal crossing the boundary threshold; and generating a health index value based on the health index component and decreasing the health index value from 100% to 0% over a duration of at least the window. The controller is configured to perform a countermeasure based on the health index value.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G05B 23/02 - Electric testing or monitoring
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

63.

LOCALIZED PLASMA ARC PREVENTION VIA PURGE RING

      
Application Number 18250349
Status Pending
Filing Date 2021-10-22
First Publication Date 2023-12-14
Owner Lam Research Corporation (USA)
Inventor
  • Leeser, Karl Frederick
  • Baker, Bradley John
  • Keshavamurthy, Arun
  • Roham, Sassan

Abstract

A purge ring including a supply port configured for receiving gas. An outer channel is connected to the supply port. An outlet network is configured for an exit flow of the gas proximate to an inner diameter of the purge ring. The purge ring includes a plurality of channels configured for flow of the gas in a radial direction from the outer channel to the outlet network. The purge ring includes a plurality of passageways configured for reduced flow of the gas in the radial direction between the outer channel and the outlet network. The plurality of channels and the plurality of passageways are configured for providing a uniform pressure of the exit flow of the gas across the outlet network circumference.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

64.

PREDICTIVE MAINTENANCE FOR SEMICONDUCTOR MANUFACTURING EQUIPMENT

      
Application Number 18251977
Status Pending
Filing Date 2021-11-09
First Publication Date 2023-12-14
Owner Lam Research Corporation (USA)
Inventor
  • Guo, Jian
  • Roham, Sassan
  • Sawlani, Kapil
  • Jin, Xiaoqiang
  • Danek, Michal
  • Williams, Brian Joseph
  • Solomon, Natan

Abstract

Various embodiments herein relate to systems and methods for predictive maintenance for semiconductor manufacturing equipment. In some embodiments, a predictive maintenance system includes a processor that is configured to: receive offline data that indicates historical operating conditions and historical manufacturing information corresponding to manufacturing equipment that conducts a manufacturing process; calculate predicted equipment health status information by using a trained model that takes the offline data as an input; receive real-time data that indicates current operating conditions of the manufacturing equipment; calculate estimated equipment health status information by using the trained model that takes the real-time data as an input; calculate adjusted equipment health status information by combining the predicted equipment health status information and the estimated equipment health status information; and present the adjusted equipment health status information that includes an expected remaining useful life (RUL) of at least one component of the manufacturing equipment.

IPC Classes  ?

65.

SUBLIMATION CONTROL USING DOWNSTREAM PRESSURE SENSING

      
Application Number 18035456
Status Pending
Filing Date 2021-11-17
First Publication Date 2023-12-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Brees, Marvin Clayton
  • Sharma, Davinder
  • Wongsenakhum, Panya

Abstract

A system to control gas flow includes an ampoule to store a solid precursor. A heater is to heat the ampoule and to sublimate the solid precursor into a gaseous precursor. A mass flow controller is to regulate a flow of gaseous precursor from the ampoule to a substrate processing chamber. A pressure sensor is to measure a pressure of the gaseous precursor input to the mass flow controller. A controller is to apply power to the electric heater using closed loop control based on the pressure and a pressure setpoint.

IPC Classes  ?

  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 14/54 - Controlling or regulating the coating process

66.

COLD EDGE LOW TEMPERATURE ELECTROSTATIC CHUCK

      
Application Number 18032154
Status Pending
Filing Date 2021-09-09
First Publication Date 2023-12-07
Owner Lam Research Corporation (USA)
Inventor
  • Chhatre, Ambarish
  • Chung, Patrick
  • Marohl, Dan
  • Rosslee, Craig A.
  • Setton, David A.
  • Shaik, Mohammad Sohail

Abstract

An electrostatic chuck is provided. In one example, the electrostatic chuck includes a base plate, a bond layer disposed over the base plate, a ceramic plate, and a heater. The ceramic plate includes a bottom surface disposed over the bond layer and a raised top surface for supporting a substrate. The raised top surface includes an outer diameter. The heater is disposed between the bottom surface of the ceramic plate and the bond layer. The heater element includes an inner heating element and an outer heating element. The inner heating element is arranged in a central circular area adjacent to the bottom surface of the ceramic plate and the outer heating element is arranged in an annular area that surrounds the central circular area and is adjacent to the bottom surface of the ceramic plate. An outer diameter of the outer heating element is inset from an annual heater setback region of the ceramic plate. The annular heater setback region is between the outer diameter of the raised top surface and the outer diameter of the outer heating element. The base plate includes a plurality of cooling channels. The plurality of cooling channels is disposed below the inner heating element, below the outer heating element, and below the annular heater setback region. Each of plurality of the cooling channels are configured to flow a cooling fluid to cause thermally conductive cooling in the annular heater setback region of the ceramic plate.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

67.

AUTO-CALIBRATION TO A STATION OF A PROCESS MODULE THAT SPINS A WAFER

      
Application Number 18448871
Status Pending
Filing Date 2023-08-11
First Publication Date 2023-12-07
Owner Lam Research Corporation (USA)
Inventor
  • Hiester, Jacob L.
  • Blank, Richard
  • Thaulad, Peter
  • Konkola, Paul

Abstract

A method for calibration including determining a temperature induced offset in a pedestal of a process module under a temperature condition for a process. The method includes delivering a wafer to the pedestal of the process module by a robot, and detecting an entry offset. The method includes rotating the wafer over the pedestal by an angle. The method includes removing the wafer from the pedestal by the robot and measuring an exit offset. The method includes determining a magnitude and direction of the temperature induced offset using the entry offset and exit offset.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/66 - Testing or measuring during manufacture or treatment

68.

AXIALLY COOLED METAL SHOWERHEADS FOR HIGH TEMPERATURE PROCESSES

      
Application Number 18026431
Status Pending
Filing Date 2021-06-02
First Publication Date 2023-11-30
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Yap, Lipyeow
  • Vikraman, Nivin
  • Wongsenakhum, Panya
  • Lind, Gary B.

Abstract

A base portion of a showerhead is made of a first metallic material, has a first surface including a gas inlet and a second surface, and includes passages. A faceplate is made of a second metallic material and has side surfaces attached to the second surface and has a bottom surface that along with the second surface define a plenum. The faceplate includes walls that extend from the bottom surface upwards through the plenum and that contact the second surface, and outlets arranged along the walls. A heater is disposed in a groove along a periphery of the base portion. A cooling plate is arranged on the first surface and includes a conduit for a coolant. A plate is made of a third material having a lower thermal conductivity than the first and second metallic materials and is arranged between the cooling plate and the base portion.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

69.

OXIDATION RESISTANT PROTECTIVE LAYER IN CHAMBER CONDITIONING

      
Application Number 18447199
Status Pending
Filing Date 2023-08-09
First Publication Date 2023-11-30
Owner Lam Research Corporation (USA)
Inventor
  • Lai, Fengyuan
  • Gong, Bo
  • Yuan, Guangbi
  • Hsu, Chen-Hua
  • Varadarajan, Bhadri

Abstract

In some examples, a method for conditioning a wafer processing chamber comprises setting a pressure in the chamber to a predetermined pressure range, setting a temperature of the chamber to a predetermined temperature, and supplying a process gas mixture to a gas distribution device within the chamber. A plasma is struck within the chamber and a condition in the chamber is monitored. Based on a detection of the monitored condition meeting or transgressing a threshold value, a chamber conditioning operation is implemented. The chamber conditioning operation may include depositing a preconditioning film onto an internal surface of the chamber, depositing a silicon oxycarbide (SiCO) film onto the preconditioning film, and depositing a protective layer onto the SiCO film.

IPC Classes  ?

  • C23C 16/40 - Oxides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

70.

SELECTIVE DEPOSITION OF METAL OXIDES USING SILANES AS AN INHIBITOR

      
Application Number 18245939
Status Pending
Filing Date 2021-09-23
First Publication Date 2023-11-30
Owner Lam Research Corporation (USA)
Inventor
  • Sharma, Kashish
  • Lemaire, Paul C.
  • Hausmann, Dennis M.

Abstract

The present disclosure relates to methods and apparatuses for selective deposition on a surface. In particular, a silicon-containing inhibitor can be used to selectively bind to a first region, thus inhibiting deposition of a material on that first region.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • C23C 16/40 - Oxides
  • C23C 16/34 - Nitrides
  • C23C 16/02 - Pretreatment of the material to be coated
  • H01J 37/32 - Gas-filled discharge tubes

71.

COMPACT MODULAR GAS DISTRIBUTION PLUMBING AND HEATING SYSTEM FOR MULTI-STATION DEPOSITION MODULES

      
Application Number 18027288
Status Pending
Filing Date 2021-09-24
First Publication Date 2023-11-23
Owner LAM RESEARCH CORPORATION (USA)
Inventor Bamford, Thadeous

Abstract

A gas distribution arrangement to provide gas mixtures to processing stations in a substrate processing system comprises a first and second valve inlet blocks to supply first and second precursor gas mixtures. The first valve inlet block is arranged above the processing stations and comprises a first housing that encloses a first plurality of valves in fluid communication with the processing stations and a first precursor gas manifold, a first co-flow gas manifold, and a first divert outlet manifold in fluid communication with the first plurality of valves. The second valve inlet block is arranged above the first valve inlet block and comprises a second housing that encloses a second plurality of valves in fluid communication with the processing stations and a second precursor gas manifold, a second co-flow gas manifold, and a second divert outlet manifold in fluid communication with the second plurality of valves.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

72.

SHOWERHEAD WITH INTEGRAL DIVERT FLOW PATH

      
Application Number 18029963
Status Pending
Filing Date 2021-09-30
First Publication Date 2023-11-23
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Bhimarasetti, Gopinath
  • Miller, Aaron Blake
  • Batzer, Rachel E.

Abstract

A showerhead for a processing chamber comprises a body having upper, lower, and side surfaces defining a plenum; and a plurality of through holes provided on the lower surface of the body. The plurality of through holes are in fluid communication with the plenum and the processing chamber. The showerhead comprises an inlet provided on one of the upper and side surfaces of the body and a first passage provided in the body. The first passage connects the inlet to the plenum. The showerhead comprises an outlet provided on one of the upper and side surfaces of the body and a second passage provided in the body. The second passage connects the outlet to the plenum.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

73.

VAPOR DELIVERY DEVICE

      
Application Number 18030308
Status Pending
Filing Date 2021-10-05
First Publication Date 2023-11-23
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Bamford, Thadeous
  • Reyes, Jorgr
  • Draper, Emile

Abstract

An evaporator assembly for a processing chamber in a substrate processing system comprises a canister configured to store and heat precursor liquid and an evaporator valve block mounted the canister. The evaporator valve block comprises a body, a plurality of valves mounted on the body, a carrier gas inlet in fluid communication with the canister, a precursor liquid inlet in fluid communication with the canister, a vapor port in fluid communication with the canister, and a vapor outlet in fluid communication with the processing chamber. Each of the plurality of valves is in fluid communication with respective flow paths contained within the evaporator valve block.

IPC Classes  ?

  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

74.

HIGH PRECISION EDGE RING CENTERING FOR SUBSTRATE PROCESSING SYSTEMS

      
Application Number 17912990
Status Pending
Filing Date 2020-03-23
First Publication Date 2023-11-16
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Han, Hui Ling
  • Ramachandran, Seetharaman
  • Estoque, Marc

Abstract

An edge ring centering system for a plasma processing system includes a processing chamber including a substrate support and R edge ring lift pins, where R is an integer greater than or equal to 3. An edge ring includes P grooves located on a bottom surface thereof, where P is an integer greater than or equal to R. A robot arm includes an end effector. A controller is configured to cause the optical sensor to sense a first position of the edge ring on the end effector; cause the robot arm to deliver the edge ring to a first center location on the edge ring lift pins; retrieve the edge ring from the edge ring lift pins; and cause the optical sensor to sense a second position of the edge ring on the end effector.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment

75.

PROFILE OPTIMIZATION FOR HIGH ASPECT RATIO MEMORY USING AN ETCH FRONT METAL CATALYST

      
Application Number 18011465
Status Pending
Filing Date 2021-12-08
First Publication Date 2023-11-16
Owner Lam Research Corporation (USA)
Inventor
  • Belau, Leonid
  • Hudson, Eric

Abstract

A method for etching features in a silicon containing stack below a patterned mask in an etch chamber is provided. The stack is partially etched by providing a halogen containing etch gas and forming the halogen containing etch gas into a halogen containing plasma, wherein the halogen containing plasma partially etches features into the stack, wherein the features have an etch front. A metal catalyst containing layer is deposited on the etch front of the features by providing a metal catalyst containing gas, forming the metal catalyst containing gas into a metal catalyst containing plasma, and selectively depositing more of the metal catalyst containing layer on the etch front and bottoms of the features than tops of the features. The features are further etched by providing a fluorine containing etch gas and forming the fluorine containing etch gas into a fluorine containing plasma, wherein the fluorine containing plasma selectively etches sidewalls adjacent to the etch front of the features with respect to sidewalls adjacent to tops of the features.

IPC Classes  ?

76.

HIGH TEMPERATURE PEDESTAL WITH EXTENDED ELECTROSTATIC CHUCK ELECTRODE

      
Application Number 18028689
Status Pending
Filing Date 2021-09-28
First Publication Date 2023-11-16
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Bi, Feng
  • Sakiyama, Yukinori
  • Rana, Niraj
  • Zhang, Pengyi
  • Shah, Simran
  • Thomas, Timothy Scott
  • French, David
  • Burkhart, Vincent

Abstract

A substrate support configured to support a substrate having a diameter D comprises a first inner electrode and a second inner electrode that are each D-shaped, define a first outer diameter that is less than D, and are configured to be connected to an electrostatic chuck voltage to clamp the substrate to the substrate support. An outer electrode comprises a ring-shaped outer portion that surrounds the first inner electrode and the second inner electrode and a center portion that pass between the first inner electrode and the second inner electrode to connect to opposite sides of an inner diameter of the ring-shaped outer portion. The inner diameter of the ring-shaped outer portion is greater than the diameter D such that the inner diameter of the ring-shaped outer portion and intersections between the center portion and the ring-shaped outer portion are located radially outside of the diameter D of the substrate.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

77.

FACELESS SHOWERHEAD

      
Application Number 18029641
Status Pending
Filing Date 2021-10-08
First Publication Date 2023-11-16
Owner Lam Research Corporation (USA)
Inventor
  • Bapat, Shriram Vasant
  • Ramnani, Pankaj Ghanshyam
  • Williams, Brian Joseph
  • Jones, Christopher Matthew
  • Bailey, Curtis W.
  • Draper, Emile
  • Shankar, Nagraj

Abstract

In some examples, a faceless showerhead comprises a body including a backing plate, the body devoid of a faceplate or plenum; a gas supply stem to admit gas into the showerhead; and a baffle supported adjacent the backing plate or the gas supply stem. The faceless showerhead may further comprise at least one support element for supporting the baffle in a baffle cavity in the backing plate or the gas supply stem.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

78.

MOVEABLE EDGE RINGS FOR PLASMA PROCESSING SYSTEMS

      
Application Number 18029708
Status Pending
Filing Date 2021-09-29
First Publication Date 2023-11-16
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Kimball, Christopher
  • Ehrlich, Darrell
  • Ohkura, Yuma

Abstract

A moveable edge ring system for a substrate processing system includes a top moveable ring including a first annular body arranged around a substrate support. The top moveable ring is exposed to plasma during substrate processing. A moveable support ring is arranged below the top moveable ring and radially outside of a baseplate of the substrate support and includes a second annular body. A shield ring is arranged radially outside of the moveable support ring and includes a third annular body. A cover ring includes a fourth annular body arranged above a radially outer edge of the top moveable ring. An actuator and a lift pin are configured to adjust a position of the top moveable ring and the moveable support ring relative to the shield ring and the cover ring.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

79.

SYSTEMS AND METHODS FOR METASTABLE ACTIVATED RADICAL SELECTIVE STRIP AND ETCH USING DUAL PLENUM SHOWERHEAD

      
Application Number 18217696
Status Pending
Filing Date 2023-07-03
First Publication Date 2023-11-16
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Yang, Dengliang
  • Fang, Haoquan
  • Cheung, David
  • Amburose, Gnanamani
  • Ko, Eunsuk
  • Luo, Weiyi
  • Zhang, Dan

Abstract

Several designs of a gas distribution device for a substrate processing system are provided. The gas distribution device includes a dual plenum showerhead. Additionally, designs for a light blocking structure used with the showerheads are also provided.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/311 - Etching the insulating layers

80.

Wear Compensating Confinement Ring

      
Application Number 18250740
Status Pending
Filing Date 2020-10-30
First Publication Date 2023-11-16
Owner Lam Research Corporation (USA)
Inventor
  • Mace, Adam Christopher
  • Memaran, Shahriar
  • Charatan, Robert
  • Jang, Siwon

Abstract

A confinement ring for use in a plasma processing chamber includes a lower horizontal section, a vertical section, and a upper horizontal section. The lower horizontal section extends between an inner lower radius and an outer radius of the confinement ring, and includes an extension section that extends vertically downward at the inner lower radius. A plurality of slots is defined in the lower horizontal section, wherein each slot extends radially from an inner diameter to an outer diameter along the lower horizontal section. An inner slot radius of each slot at the inner diameter is defined to be less than an outer slot radius at the outer diameter. The upper horizontal section extends between an inner upper radius and the outer radius of the confinement ring, and the vertical section integrally continues the lower horizontal section to the upper horizontal section at the outer radius of the confinement ring.

IPC Classes  ?

81.

HEAT-TRANSFERRING VALVE FLEXURE AND METHODS

      
Application Number 18026322
Status Pending
Filing Date 2021-08-30
First Publication Date 2023-11-16
Owner LAM RESEARCH CORPORATION (USA)
Inventor Leeser, Karl Frederick

Abstract

In some examples, a valve flexure for a flow control valve is provided. An example valve flexure comprises a first diaphragm; a second diaphragm, the second diaphragm directly or indirectly connected to the first diaphragm about a peripheral portion of the valve flexure, the connected first and second diaphragms enclosing an inner volume of the valve flexure; and a heat transfer medium disposed within the inner volume of the valve flexure.

IPC Classes  ?

  • F16K 49/00 - Means in or on valves for heating or cooling
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • F16K 7/17 - Diaphragm cut-off apparatus, e.g. with a member deformed, but not moved bodily, to close the passage with flat, dished, or bowl-shaped diaphragm arranged to be deformed against a flat seat the diaphragm being actuated by fluid pressure

82.

PREPLATING EDGE DRY

      
Application Number 18028638
Status Pending
Filing Date 2021-09-29
First Publication Date 2023-11-16
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Thorkelsson, Kari
  • Banik, Stephen J.
  • Buckalew, Bryan

Abstract

A chamber in a substrate processing system comprises a substrate holder configured to support a substrate, a nozzle arranged above the substrate, the nozzle configured to inject a pre-wetting liquid onto a surface of the substrate during a pre-wetting period, and at least one gas injector arranged radially outward of the nozzle. The at least one gas injector is configured to inject gas toward an edge of the substrate for a drying period subsequent to the pre-wetting period to remove the pre-wetting liquid from the edge of the substrate.

IPC Classes  ?

83.

ROBUST ASHABLE HARD MASK

      
Application Number 18245950
Status Pending
Filing Date 2021-09-23
First Publication Date 2023-11-09
Owner Lam Research Corporation (USA)
Inventor
  • Weimer, Matthew Scott
  • Puthenkovilakam, Ragesh
  • Reddy, Kapu Sirish

Abstract

Provided herein are methods and related apparatuses for forming an ashable hard mask (AHM). In particular instances, use of a halogen-containing precursor can provide an AHM having improved etch resistance.

IPC Classes  ?

  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
  • C23C 16/56 - After-treatment
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/26 - Deposition of carbon only
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

84.

DEPOSITION RATE ENHANCEMENT OF AMORPHOUS CARBON HARD MASK FILM BY PURELY CHEMICAL MEANS

      
Application Number 18247060
Status Pending
Filing Date 2021-09-27
First Publication Date 2023-11-09
Owner Lam Research Corporation (USA)
Inventor
  • Weimer, Matthew Scott
  • Puthenkovilakam, Ragesh
  • Reddy, Kapu Sirish
  • Hsu, Chin-Jui

Abstract

Provided herein are methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate at high temperatures using an additive that reduces a competing etch process. Sulfur hexafluoride may be used to improve the deposition rate of the AHM with minimal changes to the properties of the resulting film.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

85.

RF PULSING WITHIN PULSING FOR SEMICONDUCTOR RF PLASMA PROCESSING

      
Application Number 18348320
Status Pending
Filing Date 2023-07-06
First Publication Date 2023-11-09
Owner Lam Research Corporation (USA)
Inventor
  • Long, Maolin
  • Wang, Yuhou
  • Wu, Ying
  • Paterson, Alex

Abstract

A system and method for generating a radio frequency (RF) waveform are described. The method includes defining a train of on-off pulses separated by an off state having no on-off pulses. The method further includes applying a multi-level pulse waveform that adjusts a magnitude of each of the on-off pulses to generate an RF waveform. The method includes sending the RF waveform to an electrode.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H03K 4/92 - Generating pulses having essentially a finite slope or stepped portions having a waveform comprising a portion of a sinusoid

86.

HIGH-CONDUCTANCE VACUUM VALVES FOR WAFER PROCESSING SYSTEMS

      
Application Number 18006531
Status Pending
Filing Date 2021-07-23
First Publication Date 2023-11-09
Owner Lam Research Corporation (USA)
Inventor
  • Pioux, Gabriel
  • Ronne, Allan

Abstract

A semiconductor processing chamber performs various wafer processing operations that involve at least one of pumping the chamber to high vacuum states and regulating a vacuum (e.g., during introduction of process gases, as gas infiltrates the chamber, as reactions emit gases, as a wafer off-gases, etc.). A vacuum valve may be fluidically coupled between a vacuum pumping system and at least a portion of the semiconductor processing chamber. The vacuum valve may be a high-conductance multi-stage poppet valve enabling a relatively high gas flow rate and/or low pressure drop. In an open state, the multi-stage design of the poppet valve may have larger cross-sectional openings, in aggregate, than a comparable single-stage poppet valve could achieve, thereby increasing conductance.

IPC Classes  ?

87.

MULTI-STATION PROCESSING TOOLS WITH STATION-VARYING SUPPORT FEATURES FOR BACKSIDE PROCESSING

      
Application Number 18002289
Status Pending
Filing Date 2021-06-21
First Publication Date 2023-11-02
Owner Lam Research Corporation (USA)
Inventor
  • Linebarger, Jr., Nick Ray
  • Shaikh, Fayaz A.
  • Dhas, Arul N.

Abstract

Multi-station processing tools with station-varying support features for backside processing are provided. The support features in a first station may hold a wafer at a first set of points during backside deposition, blocking backside deposition, etching, or other processing at those points. The support features in a second station may hold a wafer at a second set of points that don’t overlap with the first set of points.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes

88.

SYSTEMS FOR CONTROLLING PLASMA DENSITY DISTRIBUTION PROFILES INCLUDING MULTI-RF ZONED SUBSTRATE SUPPORTS

      
Application Number 18013145
Status Pending
Filing Date 2021-10-12
First Publication Date 2023-11-02
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Shoeb, Juline
  • Paterson, Alexander Miller

Abstract

A substrate processing system includes a substrate support, N RF sources and a controller. The substrate support is arranged in a processing chamber, supports a substrate on an upper surface thereof, and includes: a baseplate made of electrically conductive material and M electrodes disposed in the baseplate. Each of the N RF sources supplies a respective RF signal to one or more of the M electrodes, where: M and N are integers greater than or equal to two; each of the respective RF signals is supplied to a different set of the M electrodes; and each of the sets includes a different one or more of the M electrodes. The controller causes one or more coils to strike and maintain plasma in the processing chamber independently of the N RF sources and separately controls voltage outputs of the N RF sources to adjust the plasma in the processing chamber.

IPC Classes  ?

89.

LOW TEMPERATURE MANIFOLD ASSEMBLY FOR SUBSTRATE PROCESSING SYSTEMS

      
Application Number 18013699
Status Pending
Filing Date 2022-05-05
First Publication Date 2023-11-02
Owner LAM RESEARCH CORPORATION (USA)
Inventor Soto, Gabriel De Jesus

Abstract

A manifold assembly for a processing chamber in a substrate processing system includes a manifold. The manifold includes a first valve assembly configured to flow a liquid coolant at a first temperature from a first channel of a coolant assembly to the processing chamber. The first valve assembly is configured to flow the liquid coolant at a cryogenic temperature. The manifold further includes a first weldment block including tubing associated with the first valve assembly, a second valve assembly configured to flow the liquid coolant at a second temperature greater than the first temperature from a second channel of the coolant assembly to the processing chamber, and a second weldment block including tubing associated with the second valve assembly. An insulative housing enclosing the first valve assembly, the first weldment block, and the second weldment block. The insulative housing is comprised of a plurality of layers of an insulative material.

IPC Classes  ?

90.

MATCHLESS PLASMA SOURCE FOR SEMICONDUCTOR WAFER FABRICATION

      
Application Number 18340437
Status Pending
Filing Date 2023-06-23
First Publication Date 2023-11-02
Owner Lam Research Corporation (USA)
Inventor
  • Long, Maolin
  • Wang, Yuhou
  • Marsh, Ricky
  • Paterson, Alex

Abstract

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

IPC Classes  ?

  • H05H 1/46 - Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
  • H03F 3/217 - Class D power amplifiers; Switching amplifiers
  • H01J 37/32 - Gas-filled discharge tubes

91.

PLASMA-EXCLUSION-ZONE RINGS FOR PROCESSING NOTCHED WAFERS

      
Application Number 17913935
Status Pending
Filing Date 2021-03-26
First Publication Date 2023-11-02
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Hua, Xuefeng
  • Chen, Jack
  • Amburose, Gnanamani
  • Zhang, Dan
  • Huang, Chang-Wei
  • Lin, Chia-Shin

Abstract

A plasma-exclusion-zone ring for a substrate processing system that is configured to process a substrate includes a ring-shaped body, an upper portion of the ring-shaped body, a base and a plasma-exclusion-zone ring notch. The upper portion of the ring-shaped body defines a radially inner surface and a top surface. The base of the ring-shaped body defines a radially outer surface, a first bottom surface extending radially inward from the radially outer surface, and a second bottom surface extending radially inward from the first bottom surface. The plasma-exclusion-zone ring notch is proportional to an alignment notch of the substrate. The first bottom surface is tapered and extends at an acute angle from the second bottom surface to the radially outer surface. The first bottom surface is configured to extend over and oppose a periphery of the substrate.

IPC Classes  ?

92.

ADDITIVE MANUFACTURING OF SILICON COMPONENTS

      
Application Number 17923155
Status Pending
Filing Date 2021-04-26
First Publication Date 2023-11-02
Owner
  • LAM RESEARCH CORPORATION (USA)
  • SILFEX, INC. (USA)
Inventor
  • Torbatisarraf, Seyedalireza
  • Rao, Abhinav Shekhar
  • Chen, Jihong
  • Song, Yi
  • Hubacek, Jerome
  • Nithiananthan, Vijay

Abstract

A method of performing 3D printing of a silicon component includes adding powdered silicon to a 3D printing tool. For each the powdered silicon, forming a layer of the powder bed to a pre-determined thickness, directing a high-powered beam in a pre-determined pattern into the powder-bed to melt the powdered silicon. After no further layers are needed, the silicon component is cooled at a pre-determined temperature ramp-down rate. In a fully dense printing method, buffer layers of silicon are initially printed on a steel substrate, and then layers of silicon for the actual component are printed on top of the buffer layers using a double printing method. In a fully dense and crack free printing method, one or more heaters and thermal insulation are used to minimize temperature gradient during Si printing, in-situ annealing, and cooling.

IPC Classes  ?

  • C03B 19/01 - Other methods of shaping glass by progressive fusion of powdered glass onto a shaping substrate, i.e. accretion
  • B33Y 70/00 - Materials specially adapted for additive manufacturing
  • B33Y 10/00 - Processes of additive manufacturing
  • B33Y 30/00 - ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING - Details thereof or accessories therefor

93.

ELECTROHYDRODYNAMIC EJECTION PRINTING AND ELECTROPLATING FOR PHOTORESIST-FREE FORMATION OF METAL FEATURES

      
Application Number 17759673
Status Pending
Filing Date 2021-01-27
First Publication Date 2023-10-26
Owner Lam Research Corporation (USA)
Inventor
  • Mayer, Steven T.
  • Thorkelsson, Kari

Abstract

Methods, inks, apparatus, and systems for forming metal features on semiconductor substrates are provided herein. Advantageously, the techniques herein do not require the use of photoresist, and can be accomplished without many of the processes and apparatuses used in the conventional process flow. Instead, electrohydrodynamic ejection printing is used to deposit an ink that includes an electroplating additive such as accelerator or inhibitor. The printed substrate can then be electroplated in a preferential deposition process that achieves a first deposition rate on areas of the substrate where the ink is present and a second deposition rate on areas of the substrate where the ink is absent, the first and second deposition rates being different from one another. After electroplating, chemical etching may be used to spatially isolate the preferentially grown metal features from one another.

IPC Classes  ?

  • C25D 7/12 - Semiconductors
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C25D 5/48 - After-treatment of electroplated surfaces
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • C25D 5/10 - Electroplating with more than one layer of the same or of different metals
  • C25D 5/02 - Electroplating of selected surface areas
  • C25D 21/12 - Process control or regulation
  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
  • C25D 3/38 - Electroplating; Baths therefor from solutions of copper

94.

ACCURATE DETERMINATION OF RADIO FREQUENCY POWER THROUGH DIGITAL INVERSION OF SENSOR EFFECTS

      
Application Number 18002733
Status Pending
Filing Date 2021-06-22
First Publication Date 2023-10-26
Owner Lam Research Corporation (USA)
Inventor
  • Saurabh, Ashish
  • Leeser, Karl Frederick

Abstract

An apparatus may include one or more measurement sensors, which may measure power coupled to one or more process stations of the apparatus. The apparatus may additionally include one or more analog-to-digital converters coupled to an output port of a corresponding one of the one or more measurement sensors, which may provide a digital representation of a RF signal measured by the one or more measurement sensors. A processor, coupled to a memory, may determine a crossing of the digital representation of the signal with a reference signal level and may thus determine a frequency content of the RF signal and the characteristic, which may permit the nulling out of phase lag of the one or more measurement sensors.

IPC Classes  ?

  • G01R 23/163 - Spectrum analysis; Fourier analysis adapted for measuring in circuits having distributed constants
  • G01R 19/252 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques using analogue/digital converters of the type with conversion of voltage or current into frequency and measuring of this frequency
  • G01R 23/12 - Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into phase shift

95.

ANODIZATION FOR METAL MATRIX COMPOSITE SEMICONDUCTOR PROCESSING CHAMBER COMPONENTS

      
Application Number 18011103
Status Pending
Filing Date 2021-08-23
First Publication Date 2023-10-26
Owner Lam Research Corporation (USA)
Inventor
  • Das, Debanjan
  • Samulon, Eric
  • Ehrlich, Darrell

Abstract

A component of a semiconductor processing chamber formed of a metal matrix component having an anodized layer on a surface thereof. The anodized layer comprises an aluminum oxide layer and is formed over an AlSic component. The anodized layer provides the component with protection against corrosion due to plasma processing gases, as the anodized layer provides a protective coating. A layer of aluminum is plated over a surface of the component and the aluminum layer is subsequently anodized to form the protective layer.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01J 37/32 - Gas-filled discharge tubes

96.

MULTI-LAYER HARDMASK FOR DEFECT REDUCTION IN EUV PATTERNING

      
Application Number 17759896
Status Pending
Filing Date 2021-02-23
First Publication Date 2023-10-26
Owner
  • Lam Research Corporation (USA)
  • International Business Machines Corporation (USA)
Inventor
  • Nagabhirava, Bhaskar
  • Friddle, Phillip
  • De Silva, Ekimini Anuja
  • Church, Jennifer
  • Metzler, Dominik
  • Felix, Nelson

Abstract

Various embodiments herein relate to methods, apparatus, and systems that utilize a multi-layer hardmask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multi-layer hardmask includes (1) an upper layer that includes a metal-containing material such as a metal oxide, a metal nitride, or a metal oxynitride, and (2) a lower layer that includes an inorganic dielectric silicon-containing material. Together, these layers of the multi-layer hardmask provide excellent etch selectivity and reduce formation of defects such as microbridges and line breaks. Certain embodiments relate to deposition of the multi-layer hardmask. Other embodiments relate to etching of the multi-layer hardmask. Some embodiments involve both deposition and etching of the multi-layer hardmask.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/311 - Etching the insulating layers
  • H01J 37/32 - Gas-filled discharge tubes

97.

REMOTE PLASMA ARCHITECTURE FOR TRUE RADICAL PROCESSING

      
Application Number 18245623
Status Pending
Filing Date 2021-09-21
First Publication Date 2023-10-19
Owner Lam Research Corporation (USA)
Inventor
  • Varadarajan, Bhadri
  • Durbin, Aaron
  • Qiu, Huatan
  • Gong, Bo
  • Batzer, Rachel E.
  • Bhimarasetti, Gopinath
  • Miller, Aaron Blake
  • Breiling, Patrick G.
  • Hohn, Geoffrey

Abstract

A showerhead comprises first, second, and third components. The first component includes a disc-shaped portion and a cylindrical portion extending perpendicularly from the disc-shaped portion. The disc-shaped portion includes first and second sets of holes having first and second diameters, respectively, that extend from a center of the disc-shaped portion to an inner diameter of the cylindrical portion. The second component is disc-shaped and is attached to the disc-shaped portion of the first component, defines a plenum that is in fluid communication with the second set of holes, and includes a pair of arc-shaped grooves along a periphery and on opposite ends of the top surface and a plurality of grooves extending between the pair of arc-shaped grooves. The third component is disc-shaped, is attached to the second component, and includes a gas inlet connected to the plenum, and fluid inlet and outlet connected to the arc-shaped grooves.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes

98.

PASSIVATION CHEMISTRY FOR PLASMA ETCHING

      
Application Number 18003138
Status Pending
Filing Date 2021-09-17
First Publication Date 2023-10-19
Owner Lam Research Corporation (USA)
Inventor Hudson, Eric A.

Abstract

Various embodiments herein relate to methods and apparatus for etching a recessed feature in a material on a substrate. For example, the methods may include (a) flowing a gas mixture into a processing chamber, where the gas mixture includes an etch component and a passivation component, and where the passivation component includes particular elements and/or species and/or is provided under particular conditions; (b) generating a plasma from the gas mixture in the processing chamber; and (c) exposing the substrate to the plasma and etching the recessed feature in the material on the substrate. In many cases, the material being etched on the substrate includes dielectric material and/or an electrically conductive material.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

99.

COMPUTATIONAL REPRESENTATION OF DEPOSITION PROCESSES

      
Application Number 18006639
Status Pending
Filing Date 2021-07-26
First Publication Date 2023-10-19
Owner Lam Research Corporation (USA)
Inventor
  • Wang, Qing Peng
  • Chen, Yu De
  • Huang, Shi Hao
  • Bao, Rui
  • Ervin, Joseph

Abstract

A system, method, and/or non-transitory computer readable medium may implement or be configured to implement the following computational operations associated with electrochemical or vapor phase deposition: (a) defining an interface of a substrate where deposition of a deposited material is to occur or is occurring; (b) using a computational model of the deposition to determine a local deposition rate of the deposited material at multiple locations on the interface, where the computational model of the deposition computes the local deposition rate as a function of one or more geometric parameters of the one or more recessed or protruding features; and (c) computationally adjusting the location of the interface to produce an adjusted interface.

IPC Classes  ?

  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C25D 21/12 - Process control or regulation
  • C25D 5/02 - Electroplating of selected surface areas

100.

SPARK PLASMA SINTERED COMPONENT FOR PLASMA PROCESSING CHAMBER

      
Application Number 18247724
Status Pending
Filing Date 2021-11-03
First Publication Date 2023-10-19
Owner Lam Research Corporation (USA)
Inventor
  • Xu, Lin
  • Singh, Harmeet
  • Hazarika, Pankaj
  • Srinivasan, Satish
  • Koshy, Robin

Abstract

A method for making a component for use in a plasma processing chamber is provided. A non-oxide silicon containing powder composition is placed in a mold, wherein the non-oxide silicon containing powder composition consists essentially of a non-oxide silicon containing powder and at least one of a B or B4C dopant. The non-oxide silicon containing powder composition is subjected to spark plasma sintering (SPS) to form a spark plasma sintered component. The spark plasma sintered component is machined into a plasma processing chamber component.

IPC Classes  ?

  • C04B 35/565 - Shaped ceramic products characterised by their composition; Ceramic compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxides based on carbides based on silicon carbide
  • H01J 37/32 - Gas-filled discharge tubes
  • C04B 35/64 - Burning or sintering processes
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