Lam Research Corporation

United States of America

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H01J 37/32 - Gas-filled discharge tubes 1,037
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components 597
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber 482
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 423
H01L 21/311 - Etching the insulating layers 269
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1.

WAFER LEVEL UNIFORMITY CONTROL IN REMOTE PLASMA FILM DEPOSITION

      
Application Number 18327558
Status Pending
Filing Date 2023-06-01
First Publication Date 2023-09-28
Owner Lam Research Corporation (USA)
Inventor
  • Hohn, Geoffrey
  • Qiu, Huatan
  • Batzer, Rachel E.
  • Yuan, Guangbi
  • Gui, Zhe

Abstract

An assembly for use in a process chamber for depositing a film on a wafer. The assembly includes a pedestal having a pedestal top surface extending from a central axis of the pedestal to an outer edge, the pedestal top surface having a plurality of wafer supports for supporting a wafer. A pedestal step having a step surface extending from a step inner diameter towards the outer edge of the pedestal. A focus ring rests on the step surface and having a mesa extending from an outer diameter of the focus ring to a mesa inner diameter. A shelf steps downwards from a mesa surface at the mesa inner diameter, and extends between the mesa inner diameter and an inner diameter of the focus ring. The shelf is configured to support at least a portion of a wafer bottom surface of the wafer at a process temperature.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

2.

REDUCING INTRALEVEL CAPACITANCE IN SEMICONDUCTOR DEVICES

      
Application Number 18003145
Status Pending
Filing Date 2021-06-28
First Publication Date 2023-09-28
Owner Lam Research Corporation (USA)
Inventor
  • Abel, Joseph R.
  • Van Schravendijk, Bart J.
  • Curtin, Ian John
  • Agnew, Douglas Walter
  • Austin, Dustin Zachary
  • Gupta, Awnish

Abstract

Methods of forming air gaps in hole and trench structures are disclosed. The methods may be used to form buried voids, i.e., voids for which the top is below the top of the adjacent features. The methods include inhibition of the hole or trench structures and selective deposition at the top of the structure forming an air gap within the structures. In some embodiments, the methods are to reduce intra-level capacitance in semiconductor devices.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

3.

SUBTRACTIVE COPPER ETCH

      
Application Number 18010422
Status Pending
Filing Date 2021-08-12
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Yang, Wenbing
  • Lin, Ran
  • Tan, Samantha Siamhwa
  • Brouri, Mohand
  • Pan, Yang

Abstract

A method for atomic layer etching copper or copper alloy over a substrate in a plasma processing chamber comprising a plurality of cycles is provided. Each cycle of the plurality of cycles comprises a copper modification phase and an activation phase. The copper modification phase comprises flowing a modification gas into the plasma processing chamber, transforming the modification gas into a modification plasma, and exposing the copper or copper alloy to the modification plasma, wherein at least a part of the copper or copper alloy is modified. The activation phase comprises flowing an activation gas into the plasma processing chamber, wherein the activation gas, comprises a hydrogen containing gas, transforming the activation gas into an activation plasma, and exposing the modified copper or copper alloy to the activation plasma, wherein at least a volatile copper or copper alloy complex is formed.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

4.

THIN SHADOW RING FOR LOW-TILT TRENCH ETCHING

      
Application Number 18017208
Status Pending
Filing Date 2021-07-30
First Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Setton, David
  • Chhatre, Ambarish
  • Canniff, Justin Charles
  • Marohl, Dan
  • Rosslee, Craig

Abstract

A thin shadow ring for a substrate processing system includes an annular body having an inner diameter and an outer diameter. The inner diameter and the outer diameter define a cross-sectional width of the annular body between the inner diameter and the outer diameter. At least two tabs extend radially outward from the annular body. The cross-sectional width of the annular body between the inner diameter and the outer diameter is less than 1.0 inch.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

5.

COPPER ELECTRODEPOSITION SEQUENCE FOR THE FILLING OF COBALT LINED FEATURES

      
Application Number 18202062
Status Pending
Filing Date 2023-05-25
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Velmurugan, Jeyavel
  • Buckalew, Bryan L.
  • Ponnuswamy, Thomas A.

Abstract

In one example, an electroplating system comprises a bath reservoir, an anode in the bath reservoir, and a direct-current power supply. The bath reservoir initially contains a first-electrolyte solution that includes an alkaline copper-complexed solution. The bath reservoir is arranged to be drained of the first-electrolyte solution and replaced with and contain a second-electrolyte solution. The second-electrolyte solution includes an acidic-copper plating solution. The direct-current power supply generates a first direct current between the clamp and the anode to electroplate a first copper layer on the cobalt layer of the substrate submerged in the first-electrolyte solution. The direct-current power supply then generates a second direct current between the clamp and the anode to electroplate a second copper layer on the first copper layer of the substrate submerged in the second electrolyte solution. Other systems and methods are also described.

IPC Classes  ?

  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
  • C25D 3/38 - Electroplating; Baths therefor from solutions of copper
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 17/06 - Suspending or supporting devices for articles to be coated
  • C25D 5/10 - Electroplating with more than one layer of the same or of different metals
  • C25D 5/34 - Pretreatment of metallic surfaces to be electroplated
  • H01L 21/321 - After-treatment
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C25D 5/18 - Electroplating using modulated, pulsed or reversing current

6.

LOW CEILING TEMPERATURE HOMOPOLYMERS AS SACRIFICIAL PROTECTION LAYERS FOR ENVIRONMENTALLY SENSITIVE SUBSTRATES

      
Application Number 18006552
Status Pending
Filing Date 2021-07-23
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Sirard, Stephen M.
  • Blachut, Gregory
  • Limary, Ratchana
  • Hymes, Diane
  • Pan, Yang

Abstract

The present disclosure relates to a stimulus responsive polymer (SRP) that includes a homopolymer. Methods, films, and formulations employing an SRP are also described herein.

IPC Classes  ?

  • C08L 61/18 - Condensation polymers of aldehydes or ketones with aromatic hydrocarbons or their halogen derivatives only
  • B05D 1/00 - Processes for applying liquids or other fluent materials
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material

7.

ELECTRON EXCITATION ATOMIC LAYER ETCH

      
Application Number 18187342
Status Pending
Filing Date 2023-03-21
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Berry, Iii, Ivan L.
  • Lill, Thorsten
  • Fischer, Andreas

Abstract

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

8.

COMBINED SELF-FORMING BARRIER AND SEED LAYER BY ATOMIC LAYER DEPOSITION

      
Application Number 18041391
Status Pending
Filing Date 2021-08-10
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Blakeney, Kyle Jordan
  • Dordi, Yezdi

Abstract

An electrically conductive structure in an integrated circuit (IC) includes recessed features in a dielectric layer filled with metal. The recessed features include a conformal, self-forming diffusion barrier and seed layer to limit oxidation of the metal into ions that will diffuse through the dielectric. The self-forming diffusion barrier and seed layer may also form a surface oxide layer that can be removed by an acidic solution

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 28/02 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and only coatings of metallic material
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C25D 5/02 - Electroplating of selected surface areas
  • C25D 7/12 - Semiconductors

9.

OPTIMIZING EDGE RADICAL FLUX IN A DOWNSTREAM PLASMA CHAMBER

      
Application Number 18010423
Status Pending
Filing Date 2021-12-14
First Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Bravo, Andrew Stratton
  • Park, Pilyeon
  • Kosche, Serge
  • Monbeig, Julien Augustin
  • Kawaguchi, Mark
  • Whitten, Stephen
  • Kon, Shih-Chung

Abstract

A showerhead for a processing chamber in a substrate processing system includes an upper portion having a lower surface and an upper surface and a faceplate. A lower surface of the faceplate is below the lower surface of the upper portion such that the showerhead extends into an interior volume of the processing chamber and the faceplate includes a plurality of holes arranged in a pattern to provide fluid communication between a remote plasma source above the showerhead and the interior volume of the processing chamber. A sidewall extends upward from an outer edge of the faceplate between the faceplate and the upper portion and the upper portion extends radially outward from the sidewall of the showerhead and is configured to be mounted on a sidewall of the processing chamber. A heater is embedded in the upper portion of the showerhead.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H05B 1/02 - Automatic switching arrangements specially adapted to heating apparatus

10.

METAL OXIDE WITH LOW TEMPERATURE FLUORINATION

      
Application Number 18017246
Status Pending
Filing Date 2021-07-06
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Pape, Eric A.
  • Koshy, Robin

Abstract

A method for providing a component for using in a plasma processing chamber is provided, wherein the component has a plasma facing surface. A metal oxide layer is provided on the plasma facing surface of the component. The metal oxide layer is exposed to a fluorine containing gas at a temperature of less than 600° C. for at least 2 hours at a partial pressure of at least 0.1 bar.

IPC Classes  ?

  • C23C 16/40 - Oxides
  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C23C 16/56 - After-treatment

11.

Systems and Methods for Extracting Process Control Information from Radiofrequency Supply System of Plasma Processing System

      
Application Number 18011830
Status Pending
Filing Date 2021-06-28
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Bhowmick, Ranadeep
  • Marakhtanov, Alexei
  • Kozakevich, Felix Leib
  • Holland, John

Abstract

A first radiofrequency signal generator is set to generate a low frequency signal. A second radiofrequency signal generator is set to generate a high frequency signal. An impedance matching system has a first input connected to an output of the first radiofrequency signal generator and a second input connected to an output of the second radiofrequency signal generator. The impedance matching system controls impedances at the outputs of the first and second radiofrequency signal generators. An output of the impedance matching system is connected to a radiofrequency supply input of a plasma processing system. A control module monitors reflected voltage at the output of the second radiofrequency signal generator. The control module determines when the reflected voltage indicates a change in impedance along a transmission path of the high frequency signal that is indicative of a particular process condition and/or event within the plasma processing system.

IPC Classes  ?

12.

ULTRATHIN ATOMIC LAYER DEPOSITION FILM ACCURACY THICKNESS CONTROL

      
Application Number 18188325
Status Pending
Filing Date 2023-03-22
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Qian, Jun
  • Kang, Hu
  • Lavoie, Adrien
  • Matsuyama, Seiji
  • Kumar, Purushottam

Abstract

Methods for depositing ultrathin films by atomic layer deposition with reduced wafer-to-wafer variation are provided. Methods involve exposing the substrate to soak gases including one or more gases used during a plasma exposure operation of an atomic layer deposition cycle prior to the first atomic layer deposition cycle to heat the substrate to the deposition temperature.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/40 - Oxides

13.

SELF-LIMITING GROWTH

      
Application Number 18310523
Status Pending
Filing Date 2023-05-01
First Publication Date 2023-09-14
Owner Lam Research Corporation (USA)
Inventor
  • Collins, Joshua
  • Kennedy, Griffin John
  • Bamnolker, Hanna
  • Danek, Michal
  • Thombare, Shruti Vivek
  • Van Cleemput, Patrick A.
  • Butail, Gorun

Abstract

Provided herein are methods and apparatuses for forming metal films such as tungsten (W) and molybdenum (Mo) films on semiconductor substrates. The methods involve forming a reducing agent layer, then exposing the reducing agent layer to a metal precursor to convert the reducing agent layer to a layer of the metal. In some embodiments, the reducing agent layer is a silicon- (Si-) and boron- (B-) containing layer. The methods may involve forming the reducing agent layer at a first substrate temperature, raising the substrate temperature to a second substrate temperature, and then exposing the reducing agent layer to 10 the metal precursor at the second substrate temperature. The methods may be used to form fluorine-free tungsten or molybdenum films in certain embodiments. Apparatuses to perform the methods are also provided.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

14.

DISTRIBUTED PLASMA SOURCE ARRAY

      
Application Number 17927328
Status Pending
Filing Date 2021-05-10
First Publication Date 2023-09-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Benjamin, Neil M. P.
  • Patrick, Roger

Abstract

A substrate processing system includes a processing chamber including a window. A substrate support is arranged inside the processing chamber to support a substrate during plasma processing. A first array including E inductive coils arranged adjacent to and outside of the processing chamber, where E is an integer greater than three. A second array includes D RF direct drive circuits configured to output RF power to the first array, where D is an integer greater than three, and to generate plasma inside of the processing chamber.

IPC Classes  ?

15.

LOW RESISTANCE GATE OXIDE METALLIZATION LINER

      
Application Number 18003137
Status Pending
Filing Date 2020-07-29
First Publication Date 2023-09-14
Owner Lam Research Corporation (USA)
Inventor
  • Schloss, Lawrence
  • Chandrashekar, Anand
  • Gao, Juwen
  • Sawant-Goubert, Stephanie Noelle Sandra
  • Pan, Yu

Abstract

Methods and apparatuses for forming low resistivity tungsten using tungsten nitride barrier layers are provided herein. Methods involve depositing extremely thin tungsten nitride barrier layers prior to depositing tungsten nucleation and bulk tungsten layers. Methods are applicable for fabricating tungsten word lines in 3D NAND fabrication as well as for fabricating tungsten-containing components of DRAM and logic fabrication. Apparatus included processing stations with multiple charge volumes to pressurize gases in close vicinity to a showerhead of a processing chamber for processing semiconductor substrates.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • C23C 16/34 - Nitrides
  • C23C 16/14 - Deposition of only one other metal element
  • C23C 16/56 - After-treatment
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

16.

PHOTORESISTS CONTAINING TANTALUM

      
Application Number 18005328
Status Pending
Filing Date 2021-07-16
First Publication Date 2023-09-14
Owner Lam Research Corporation (USA)
Inventor
  • Hansen, Eric Calvin
  • Wu, Chenghao
  • Weidman, Timothy William

Abstract

The present disclosure relates to a film formed with a tantalum-based precursor, as well as methods for forming and employing such films. The film can be employed as a photopatternable film or a radiation-sensitive film. In non-limiting embodiments, the radiation can include extreme ultraviolet (EUV) or deep ultraviolet (DUV) radiation.

IPC Classes  ?

  • G03F 7/004 - Photosensitive materials
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/32 - Liquid compositions therefor, e.g. developers
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
  • G03F 7/40 - Treatment after imagewise removal, e.g. baking
  • G03F 7/20 - Exposure; Apparatus therefor

17.

INTEGRATED DRY PROCESSES FOR PATTERNING RADIATION PHOTORESIST PATTERNING

      
Application Number 18184545
Status Pending
Filing Date 2023-03-15
First Publication Date 2023-09-14
Owner Lam Research Corporation (USA)
Inventor
  • Yu, Jengyi
  • Tan, Samantha S.H.
  • Alvi, Mohammed Haroon
  • Wise, Richard
  • Pan, Yang
  • Gottscho, Richard Alan
  • Lavoie, Adrien
  • Kanakasabapathy, Sivananda Krishnan
  • Weidman, Timothy William
  • Lin, Qinghuang
  • Hubacek, Jerome S.

Abstract

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G03F 7/38 - Treatment before imagewise removal, e.g. prebaking
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/004 - Photosensitive materials
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma

18.

SUBSTRATE PROCESSING SYSTEMS INCLUDING GAS DELIVERY SYSTEM WITH REDUCED DEAD LEGS

      
Application Number 18196605
Status Pending
Filing Date 2023-05-12
First Publication Date 2023-09-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Chandrasekharan, Ramesh
  • Xavier, Antonio
  • Pasquale, Frank Loren
  • Blaquiere, Ryan
  • Petraglia, Jennifer Leigh
  • Mamunuru, Meenakshi

Abstract

A gas delivery system includes a 2-port valve including a first valve located between a first port and a second port. A 4-port valve includes a first node connected to a first port and a second port. A bypass path is located between the third port and the fourth port. A second node is located along the bypass path. A second valve is located between the first node and the second node. A manifold block defines gas flow channels configured to connect the first port of the 4-port valve to a first inlet, configured to connect the second port of the 4-port valve to the first port of the 2-port valve, the third port of the 4-port valve to a second inlet, the second port of the 2-port valve to a first outlet, and the fourth port of the 4-port valve to a second outlet.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

19.

REMOVABLE SHOWERHEAD FACEPLATE FOR SEMICONDUCTOR PROCESSING TOOLS

      
Application Number 18000635
Status Pending
Filing Date 2021-06-04
First Publication Date 2023-09-07
Owner Lam Research Corporation (USA)
Inventor
  • Shankarnarayana, Manjesh
  • Luo, Bin
  • Lenz, Eric H.

Abstract

Showerheads for semiconductor processing operations are disclosed that have removable faceplates and various features that provide additional benefit in the context of removable faceplates.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

20.

Systems and Methods for Analyzing and Intelligently Collecting Sensor Data

      
Application Number 18011445
Status Pending
Filing Date 2021-08-31
First Publication Date 2023-09-07
Owner Lam Research Corporation (USA)
Inventor
  • Valcore, Jr., John C.
  • Wong, Travis Joseph
  • Wu, Ying
  • Mudunuri, Sandeep
  • Pust, Bostjan
  • Dash, Shreeram Jyoti

Abstract

A method for controlling a plasma tool is described. The method includes receiving, by a processor, a first set of metric data from a plasma tool. The method further includes analyzing the first set of metric data to determine a first location and a first time window for capturing of a second set of metric data. The method includes providing, by the processor, the first location and the first time window to a data processing system of the plasma tool. The method also includes receiving the second set of metric data captured at the first location and for the first time window. The method includes analyzing the second set of metric data to generate variable data and controlling the plasma tool according to the variable data.

IPC Classes  ?

21.

MAGNETIC FIELD CONTROL SYSTEM

      
Application Number 18013489
Status Pending
Filing Date 2022-05-17
First Publication Date 2023-09-07
Owner Lam Research Corporation (USA)
Inventor
  • Griffin, Alecia Chantalle
  • De La Llera, Anthony
  • Phillips, Peter Bradley
  • Ji, Bing

Abstract

A substrate processing apparatus includes a vacuum chamber with a processing zone for processing a substrate using plasma and at least one magnetic field source configured to generate one or more active magnetic fields through the processing zone. The apparatus also includes a magnetic field sensor configured to detect a signal representing the one or more active magnetic fields, and a controller coupled to the magnetic field sensor, and the at least one magnetic field source. The controller is configured to detect a target value corresponding to at least one characteristic of the one or more active magnetic fields, set an initial current through the at least one magnetic field source, the initial current corresponding to the target value; and adjust a subsequent current through the at least one magnetic field source based on the detected signal representing the one or more active magnetic fields.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01J 37/34 - Gas-filled discharge tubes operating with cathodic sputtering

22.

REMOTE PLASMA SOURCE SHOWERHEAD ASSEMBLY WITH ALUMINUM FLUORIDE PLASMA EXPOSED SURFACE

      
Application Number 18011582
Status Pending
Filing Date 2021-06-24
First Publication Date 2023-09-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Pape, Eric A.
  • Kon, Shih-Chung
  • Hazarika, Pankaj
  • Xu, Lin

Abstract

A component of a processing chamber in a substrate processing system includes a base material comprising aluminum, the base material having one or more surfaces, a diffusion barrier layer formed on the surfaces of the base material, wherein the diffusion barrier layer includes magnesium and fluorine (F), and a coating formed on the surfaces. The diffusion barrier layer is arranged between the surfaces and the coating and the coating includes fluorine.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides

23.

PULSING RF COILS OF A PLASMA CHAMBER IN REVERSE SYNCHRONIZATION

      
Application Number 18015708
Status Pending
Filing Date 2021-07-01
First Publication Date 2023-09-07
Owner Lam Research Corporation (USA)
Inventor
  • Shoeb, Juline
  • Kamp, Tom A.
  • Paterson, Alexander Miller

Abstract

Systems and methods for pulsing radio frequency (RF) coils are described. One of the methods includes supplying a first RF signal to a first impedance matching circuit coupled to a first RF coil, supplying a second RF signal to a second impedance matching circuit coupled to a second RF coil, and pulsing the first RF signal between a first parameter level and a second parameter level. The method includes pulsing the second RF signal between a third parameter level and a fourth parameter level in reverse synchronization with the pulsing of the first RF signal.

IPC Classes  ?

24.

SYNCHRONIZATION OF RF GENERATORS

      
Application Number 18012212
Status Pending
Filing Date 2021-09-24
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Wu, Ying
  • Drewery, John Stephen
  • Paterson, Alexander Miller
  • Zhou, Xiang
  • Wang, Zhuoxian
  • Kimura, Yoshie

Abstract

Systems and methods for synchronization of radio frequency (RF) generators are described. One of the methods includes receiving, by a first RF generator, a first recipe set, which includes information regarding a first plurality of pulse blocks for operating the first RF generator. The method further includes receiving, by a second RF generator, a second recipe set, which includes information regarding a second plurality of pulse blocks for operating a second RF generator. Upon receiving a digital pulsed signal, the method includes executing the first recipe set and executing the second recipe set. The method further includes outputting a first one of the pulse blocks of the first plurality based on the first recipe set in synchronization with a synchronization signal. The method includes outputting a first one of the pulse blocks of the second plurality based on the second recipe set in synchronization with the synchronization signal.

IPC Classes  ?

25.

AUTOMATED SHOWERHEAD TILT ADJUSTMENT

      
Application Number 18012224
Status Pending
Filing Date 2021-06-10
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Tehrani, Sam Jafarian
  • Cmelak, Bryan Anthony
  • Hiester, Jacob Lee
  • Luo, Bin
  • Wiltse, John

Abstract

In some examples, an automated tilting system is provided for adjusting an orientation of a component in a substrate processing chamber. The automated tilting system comprises at least one tilt adjustment motor arranged to cooperate with the component and be connected to a portion of the component by a coupling. The coupling is configured such that automated rotational motion by the at least one tilt adjustment motor imparts corresponding axial movement, relative to the at least one tilt adjustment motor or a datum structure, to the connected portion of the component to adjust the orientation of the component in the processing chamber.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

26.

SUBSTRATE SUPPORTS WITH MULTILAYER STRUCTURE INCLUDING COUPLED HEATER ZONES WITH LOCAL THERMAL CONTROL

      
Application Number 18013445
Status Pending
Filing Date 2021-08-02
First Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Singh, Harmeet
  • Mitrovic, Slobodan
  • Ehrlich, Darrell
  • Wu, Benny

Abstract

A substrate support assembly for supporting a substrate includes a baseplate, a ceramic plate arranged on the baseplate, and N resistive heaters arranged in X rows and Y columns and coupled to the ceramic plate. X, Y, and N are integers greater than 1, and N is less than or equal to X*Y. Each of the N resistive heaters have a first terminal and a second terminal. The ceramic plate includes Y conductors arranged in a first layer of the ceramic plate, and X conductors arranged in a second layer of the ceramic plate. The first terminals of each resistive heater in one of the X rows are directly connected to the Y conductors, respectively, by first vias. Second terminals of each resistive heater in the one of the X rows are directly connected to one of the X conductors by second vias.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H05B 3/28 - Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor embedded in insulating material

27.

ATOMIC LAYER ETCHING OF A SEMICONDUCTOR, A METAL, OR A METAL OXIDE WITH SELECTIVITY TO A DIELECTRIC

      
Application Number 18002788
Status Pending
Filing Date 2021-08-20
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Lill, Thorsten Bernd
  • Fischer, Andreas
  • Routzahn, Aaron Lynn

Abstract

Semiconductor processing methods and apparatuses are provided. Some methods include providing a substrate to a processing chamber, the substrate having a semiconductor portion and a dielectric portion, modifying the semiconductor portion of the substrate selective to the dielectric portion of the substrate by flowing a first process gas comprising a first halogen species onto the substrate and providing a first activation energy to cause the first halogen species to preferentially adsorb on the semiconductor portion relative to the dielectric portion to form a first halogenated semiconductor, and removing the first halogenated semiconductor by flowing a second process gas comprising a second halogen species onto the substrate and providing a second activation energy, without providing a plasma, to cause the second halogen species to react with the first halogenated semiconductor and cause the first halogenated semiconductor to desorb from the substrate.

IPC Classes  ?

28.

ETCHING OF INDIUM GALLIUM ZINC OXIDE

      
Application Number 18003257
Status Pending
Filing Date 2022-03-15
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Routzahn, Aaron Lynn
  • Fischer, Andreas
  • Lill, Thorsten Bernd

Abstract

Indium gallium zinc oxide can be etched by providing a wafer having a layer of indium gallium zinc oxide to a processing chamber, heating the wafer to a first temperature, flowing a first chemical species comprising a fluoride to create a layer of indium gallium zinc oxyfluoride, and removing the layer of indium gallium zinc oxyfluoride by flowing a second chemical species comprising an alkyl aluminum halide, an aluminum alkalide, an organoaluminium compound, a diketone, silicon halide, silane, halogenated silane, or alkyl silicon halide.

IPC Classes  ?

  • H01L 21/465 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

29.

PEDESTAL THERMAL PROFILE TUNING USING MULTIPLE HEATED ZONES AND THERMAL VOIDS

      
Application Number 18008273
Status Pending
Filing Date 2021-06-04
First Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lind, Gary B.
  • Mahadeva, Alok

Abstract

A substrate support includes a body and a thermal void. The body is configured to support a substrate during processing of the substrate. The body includes plates including a top plate, a first intermediate plate, a second intermediate plate and a bottom plate. The plates are arranged to form a stack. The first intermediate plate is disposed on the second intermediate plate. The thermal void is defined by an upper surface of the second intermediate plate and at least one of a lower surface of the first intermediate plate or a lower surface of the top plate. The thermal void is annular-shaped.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

30.

LOW FREQUENCY RF GENERATOR AND ASSOCIATED ELECTROSTATIC CHUCK

      
Application Number 18011062
Status Pending
Filing Date 2021-11-05
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Marakhtanov, Alexei M.
  • Kozakevich, Felix Leib
  • Ji, Bing
  • Bhowmick, Ranadeep
  • Holland, John Patrick
  • Matyushkin, Alexander

Abstract

A system having the low frequency RF generator is described. The low frequency RF has an operating frequency range between 10 kilohertz (kHz) and 330 kHz. The low frequency RF generator generates an RF signal. The system further includes an impedance matching circuit coupled to the low frequency RF generator for receiving the RF signal. The impedance matching circuit modifies an impedance of the RF signal to output a modified RF signal. The system includes a plasma chamber coupled to the RF generator for receiving the modified RF signal. The plasma chamber includes a chuck having a dielectric layer and a base metal layer. The dielectric layer is located on top of the base metal layer. The dielectric layer has a bottom surface, and the base metal layer has a top surface. The base metal layer has a porous plug and the bottom surface of the dielectric layer has a portion that is in contact with the porous plug.

IPC Classes  ?

31.

CONTROLLING TEMPERATURE PROFILES OF PLASMA CHAMBER COMPONENTS USING STRESS ANALYSIS

      
Application Number 18013475
Status Pending
Filing Date 2021-08-11
First Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor Drewery, John

Abstract

A system for estimating stress on a component of a processing chamber during a process includes a plurality of sensors configured to sense temperatures at a plurality of locations of the component during the process and a controller a controller configured to interpolate the temperatures to estimate a temperature distribution across the component and to estimate the stress on the component during the process. A method of estimating stress on a component of a processing chamber during a process includes sensing temperatures at a plurality of locations of the component during the process, interpolating the temperatures to estimate a temperature distribution across the component, and estimating the stress on the component during the process.

IPC Classes  ?

32.

ADJUSTABLE GEOMETRY TRIM COIL

      
Application Number 18013477
Status Pending
Filing Date 2021-06-24
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor Bailey, Iii, Andrew D.

Abstract

Methods, systems, apparatuses, and computer programs are presented for controlling etch rate and plasma uniformity using magnetic fields. A substrate processing apparatus includes a vacuum chamber including a processing zone for processing a substrate. The apparatus further includes a magnetic field sensor configured to detect a signal representing a residual magnetic field associated with the vacuum chamber. At least one magnetic field source is configured to generate one or more supplemental magnetic fields through the processing zone of the vacuum chamber. A magnetic field controller is coupled to the magnetic field sensor and the at least one magnetic field source. The magnetic field controller is configured to adjust at least one characteristic of the one or more supplemental magnetic fields, causing the one or more supplemental magnetic fields to reduce the residual magnetic field to a pre-determined value.

IPC Classes  ?

33.

SOLENOID BANK WITH STANDBY SOLENOID VALVES FOR CONTROLLING PNEUMATIC VALVES OF A SUBSTRATE PROCESSING SYSTEM

      
Application Number 18020302
Status Pending
Filing Date 2021-08-17
First Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Panchangam, Swajeeth Pilot
  • Gulabal, Vinayakaraddy
  • Saghi, Yeshwanth
  • Gowdaru, Keerthi

Abstract

A fluid control system for a substrate processing system includes (M + N) inlets configured to fluidly connect to (M) solenoid valves and (N) standby solenoid valves, respectively, where (M) and (N) are integers greater than zero. (M) outputs are configured to be fluidly connected to (M) pneumatic valves. A valve switching system is configured to selectively block (1) to (N) of the M inlets corresponding to (1) to (N) failed ones of (M) solenoid valves, respectively, and supply fluid from (1) to (N) of the (N) standby solenoid valves to (1) to (N) of the (M) outputs corresponding to the (1) to (N) failed ones of (M) solenoid valves, respectively.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

34.

COOLING FOR A PLASMA-BASED REACTOR

      
Application Number 18142570
Status Pending
Filing Date 2023-05-02
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Drewery, John Stephen
  • Benjamin, Neil Martin Paul

Abstract

In one embodiment, the disclosed apparatus is a heat-pipe cooling system that includes a conical structure having an upper portion that is configured to be formed above a dielectric window with the conical structure being configured to condense vapor from a heat-transfer fluid placed or incorporated within a volume formed between the dielectric window and the conical structure. At least one cooling coil is formed on an exterior portion of the conical structure. Other apparatuses and systems are disclosed.

IPC Classes  ?

35.

VACUUM-INTEGRATED HARDMASK PROCESSES AND APPARATUS

      
Application Number 18297989
Status Pending
Filing Date 2023-04-10
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Marks, Jeffrey
  • Antonelli, George Andrew
  • Gottscho, Richard A.
  • Hausmann, Dennis M.
  • Lavoie, Adrien
  • Knisley, Thomas Joseph
  • Reddy, Sirish K.
  • Varadarajan, Bhadri N.
  • Kolics, Artur

Abstract

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

IPC Classes  ?

  • G03F 1/76 - Patterning of masks by imaging
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/18 - Pretreatment of the material to be coated
  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F 7/26 - Processing photosensitive materials; Apparatus therefor
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 18/14 - Decomposition by irradiation, e.g. photolysis, particle radiation

36.

METAL CHELATORS FOR DEVELOPMENT OF METAL-CONTAINING PHOTORESIST

      
Application Number 18005571
Status Pending
Filing Date 2021-07-16
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Hansen, Eric Calvin
  • Weidman, Timothy William
  • Wu, Chenghao
  • Gu, Kevin Li
  • Dictus, Dries

Abstract

The present disclosure relates to use of a metal chelator to treat an exposed photoresist film. In particular embodiments, the metal chelator is employed to remove an interfacial area that is disposed between exposed and unexposed areas or disposed within an exposed area, thereby enhancing patterning quality.

IPC Classes  ?

  • G03F 7/32 - Liquid compositions therefor, e.g. developers
  • G03F 7/20 - Exposure; Apparatus therefor
  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/38 - Treatment before imagewise removal, e.g. prebaking

37.

SELECTIVE SILICON TRIM BY THERMAL ETCHING

      
Application Number 18004051
Status Pending
Filing Date 2022-01-21
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Musselwhite, Nathan
  • Zhu, Ji
  • Melaet, Gerome Michel Dominique
  • Kawaguchi, Mark Naoshi

Abstract

Methods and apparatuses for precise trimming of silicon-containing materials are provided. Methods involve oxidizing silicon-containing materials and thermally removing the oxidized silicon-containing materials at particular temperatures for a self-limiting etch process. Methods also involve a surface reaction limited process using a halogen source and modulated temperature and exposure duration to etch small amounts of silicon-containing materials. Apparatuses are capable of flowing multiple oxidizers at particular temperature ranges to precisely etch substrates.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/321 - After-treatment

38.

PHOTORESISTS FROM SN(II) PRECURSORS

      
Application Number 18005594
Status Pending
Filing Date 2021-07-16
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Hansen, Eric Calvin
  • Wu, Chenghao
  • Weidman, Timothy William

Abstract

The present disclosure relates to a film formed with an organotin(II) compound, as well as methods for forming and employing such films. The film can be employed as a photopatternable film or a radiation-sensitive film. In non-limiting embodiments, the radiation can include extreme ultraviolet (EUV) or deep ultraviolet (DUV) radiation

IPC Classes  ?

39.

IN-SITU HYDROCARBON-BASED LAYER FOR NON-CONFORMAL PASSIVATION OF PARTIALLY ETCHED STRUCTURES

      
Application Number 18012194
Status Pending
Filing Date 2022-06-13
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Hudson, Eric
  • Reddy, Kapu Sirish
  • Puthenkovilakam, Ragesh
  • Deshmukh, Shashank
  • Kumar, Prabhat
  • Gopaladasu, Prabhakara
  • Yun, Seokmin
  • Zhang, Xin

Abstract

A method for selectively etching at least one feature in a first region with respect to a second region of a stack is provided. The first region is selectively etched with respect to the second region to form at least one partial feature in the first region, the at least one partial feature having a depth with respect to a surface of the second region. An in-situ a fluorine-free, non-conformal, carbon-containing mask is deposited over the first region and the second region, wherein the carbon-containing mask is selectively deposited on the second region at a second thickness with respect to the first region at a first thickness, the second thickness being greater than the first thickness. The first region is further etched in-situ to etch the at least one partial feature and wherein the carbon-containing mask acts as an etch mask for the second region.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

40.

VACUUM-INTEGRATED HARDMASK PROCESSES AND APPARATUS

      
Application Number 18298003
Status Pending
Filing Date 2023-04-10
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Marks, Jeffrey
  • Antonelli, George Andrew
  • Gottscho, Richard A.
  • Hausmann, Dennis M.
  • Lavoie, Adrien
  • Knisley, Thomas Joseph
  • Reddy, Sirish K.
  • Varadarajan, Bhadri N.
  • Kolics, Artur

Abstract

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

IPC Classes  ?

  • G03F 1/76 - Patterning of masks by imaging
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/18 - Pretreatment of the material to be coated
  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F 7/26 - Processing photosensitive materials; Apparatus therefor
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 18/14 - Decomposition by irradiation, e.g. photolysis, particle radiation

41.

INTEGRATION OF VAPOR DEPOSITION PROCESS INTO PLASMA ETCH REACTOR

      
Application Number 18003139
Status Pending
Filing Date 2021-10-22
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Hudson, Eric A.
  • Serino, Andrew Clark
  • Nicholson, Thad
  • Chandrasekharan, Ramesh
  • Schoepp, Alan M.

Abstract

Various embodiments herein relate to methods and systems for integrating a vapor deposition process and an etch process in a single reactor. The vapor deposition process involves delivery of at least one deposition vapor in the absence of plasma. The etch process is a plasma etch process. Various features may be combined as desired to promote high quality deposition and etching results.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/56 - After-treatment
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

42.

PLASMA DISCHARGE UNIFORMITY CONTROL USING MAGNETIC FIELDS

      
Application Number 18013480
Status Pending
Filing Date 2021-08-30
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Panagopoulos, Theodoros
  • Marakhtanov, Alexei M.
  • Ji, Bing
  • De La Llera, Anthony
  • Holland, John P.
  • Paeng, Dong Woo

Abstract

Methods, systems, apparatuses, and computer programs are presented for controlling plasma discharge uniformity using magnetic fields. A substrate processing apparatus includes a vacuum chamber with a processing zone for processing a substrate. The apparatus further includes a magnetic field sensor to detect a first signal representing an axial magnetic field and a second signal representing a radial magnetic field associated with the vacuum chamber. The apparatus includes at least two magnetic field sources to generate an axial supplemental magnetic field and a radial supplemental magnetic field through the processing zone of the vacuum chamber. The apparatus includes a magnetic field controller coupled to the magnetic field sensor and the at least two magnetic field sources. The magnetic field controller adjusts at least one characteristic of one or more of the axial supplemental magnetic field and the radial supplemental magnetic field based on the first signal and the second signal.

IPC Classes  ?

  • H01J 37/34 - Gas-filled discharge tubes operating with cathodic sputtering
  • H01L 21/311 - Etching the insulating layers

43.

METHODS TO IMPROVE WAFER WETTABILITY FOR PLATING - ENHANCEMENT THROUGH SENSORS AND CONTROL ALGORITHMS

      
Application Number 17998255
Status Pending
Filing Date 2021-05-03
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Hur, Hyungjun
  • Tilak, Pooja
  • Ghongadi, Shantinath
  • Sweeney, Cian

Abstract

Various embodiments include methods and apparatuses to moisturize a substrate prior to an electrochemical deposition process. In one embodiment, a method to control substrate wettability includes placing a substrate in a humidification environment, controlling the humidification environment to moisturize a surface of the substrate; and placing the substrate into a plating cell. Other methods and systems are disclosed.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C25D 7/12 - Semiconductors
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 21/12 - Process control or regulation

44.

METAL OXIDE DIFFUSION BARRIERS

      
Application Number 17999442
Status Pending
Filing Date 2021-06-25
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Brogan, Lee J.
  • Van Cleemput, Patrick A.
  • Huie, Matthew Martin
  • Blakeney, Kyle Jordan
  • Liu, Yi Hua

Abstract

Various embodiments herein relate to methods, apparatus, and systems for forming an interconnect structure, or a portion thereof, on a substrate. In one example, the method includes receiving the substrate in a processing chamber, the substrate having dielectric material exposed within recessed features formed therein; exposing the substrate to plasma to thereby modify a top surface of the dielectric material; forming a metal oxide barrier layer on the modified top surface of the dielectric material, wherein the metal oxide barrier layer is formed through atomic layer deposition and/or chemical vapor deposition. In certain implementations, one or more additional step may be taken to improve processing results, for example to promote nucleation and/or adhesion of relevant layers.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • C23C 16/34 - Nitrides
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01J 37/32 - Gas-filled discharge tubes

45.

CONCENTRATION CONTROL USING A BUBBLER

      
Application Number 18001587
Status Pending
Filing Date 2021-07-21
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Chandrasekharan, Ramesh
  • Srinivasan, Easwar
  • Pohl, Erica Sakura Strandberg
  • Borth, Andrew
  • Altecor, Aleksey V.

Abstract

The present disclosure relates, in part, to an apparatus for controlling the concentration of a component within a gas mixture. In particular embodiments, the component is a vaporized liquid component, such as a vaporized stabilizer or a vaporized precursor. Also described are systems thereof and methods for such control.

IPC Classes  ?

  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C23C 16/26 - Deposition of carbon only
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/52 - Controlling or regulating the coating process

46.

CHEMISTRY FOR HIGH ASPECT RATIO ETCH FOR 3D-NAND

      
Application Number 18003146
Status Pending
Filing Date 2022-05-24
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Dole, Nikhil
  • Yanagawa, Takumi

Abstract

Various embodiments herein relate to methods and apparatus for etching a memory hole in a stack of materials on a substrate. In some cases, the stack includes alternating layers of silicon oxide and silicon nitride. In other cases, the stack includes alternating layers of silicon oxide and polysilicon. In either case, three or more sets of processing conditions are used to etch the substrate. Various processing conditions such as the composition of a reactant mixture, pressure, substrate temperature, and/or plasma generation conditions are varied between the three or more sets of processing conditions to produce high quality etching results with high selectivity, a highly vertical etch profile, and a low degree of bowing.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C09K 13/00 - Etching, surface-brightening or pickling compositions

47.

DRY DEPOSITED PHOTORESISTS WITH ORGANIC CO-REACTANTS

      
Application Number 18005169
Status Pending
Filing Date 2021-07-16
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Hansen, Eric Calvin
  • Weidman, Timothy William
  • Wu, Chenghao
  • Lin, Qinghuang
  • Blakeney, Kyle Jordan

Abstract

The present disclosure relates to a film formed with a precursor and an organic co-reactant, as well as methods for forming and employing such films. The film can be employed as a photopatternable film or a radiation-sensitive film. In particular embodiments, the carbon content within the film can be tuned by decoupling the sources of the radiation-sensitive metal elements and the radiation-sensitive organic moieties during deposition. In non-limiting embodiments, the radiation can include extreme ultraviolet (EUV) or deep ultraviolet (DUV) radiation.

IPC Classes  ?

  • G03F 7/004 - Photosensitive materials
  • G03F 7/20 - Exposure; Apparatus therefor
  • G03F 7/16 - Coating processes; Apparatus therefor
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

48.

EXCLUSION RING FOR SUBSTRATE PROCESSING

      
Application Number 18013749
Status Pending
Filing Date 2021-07-13
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Gulabal, Vinayakaraddy
  • Vellanki, Ravi
  • Dhawade, Eashan Raju
  • Mahadeva, Alok
  • Chen, Erica Maxine
  • Ba, Xiaolan

Abstract

In some examples, an exclusion ring locates a substrate on a substrate-support assembly in a processing chamber. An example exclusion ring comprises an inner edge portion to cover an edge of a substrate in the processing chamber and an outer edge portion to support the exclusion ring on the substrate support assembly in the processing chamber. The outer edge portion may include an outer edge of the exclusion ring. A separation zone extending between the inner edge portion and the outer edge of the exclusion ring includes an undercut in an undersurface of the exclusion ring. In some examples, a cooling gas is directed at the exclusion ring while the exclusion ring is located at a station or during an indexing operation performed by the exclusion ring within a processing tool.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/28 - Deposition of only one other non-metal element
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

49.

Selected Reject Band Non-Radiofrequency-Coupling Tile and Associated Methods and Systems

      
Application Number 18017381
Status Pending
Filing Date 2021-08-04
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Kapoor, Sunil
  • Madsen, Eric
  • Marohl, Dan

Abstract

A selected reject band non-RF-coupling tile includes a ground plate disposed on a first side of a printed circuit board. The selected reject band non-RF-coupling tile also includes a planar inductor disposed on a second side of the printed circuit board. The selected reject band non-RF-coupling tile also includes a conductive via structure extending through the printed circuit board. The conductive via structure electrically connects to both the ground plate and the planar inductor at a location near an interior end of the planar inductor. The selected reject band non-RF-coupling tile is used to shield enclosure walls and/or other electrical circuitry from RF fields. The selected reject band non-RF-coupling tile is also used to encapsulate an RF carrying component to block RF fields that emanate from the RF carrying component.

IPC Classes  ?

  • H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 1/02 - Printed circuits - Details
  • H01F 27/28 - Coils; Windings; Conductive connections

50.

ELECTROSTATIC CHUCKS WITH COOLANT GAS ZONES AND CORRESPONDING GROOVE AND MONOPOLAR ELECTROSTATIC CLAMPING ELECTRODE PATTERNS

      
Application Number 18139660
Status Pending
Filing Date 2023-04-26
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Matyushkin, Alexander
  • Comendant, Keith Laurence
  • Holland, John Patrick

Abstract

An electrostatic chuck for a substrate processing system is provided and includes a baseplate, an intermediate layer disposed on the baseplate, and a top plate. The top plate is bonded to the baseplate via the intermediate layer and is configured to electrostatically clamp to a substrate. The top plate includes a monopolar clamping electrode and seals. The monopolar clamping electrode includes a groove opening pattern with coolant gas groove opening sets. The seals separate coolant gas zones. The coolant gas zones include four or more coolant gas zones. Each of the coolant gas zones includes distinct coolant gas groove sets. The top plate includes the distinct coolant gas groove sets. Each of the distinct coolant gas groove sets has one or more coolant gas supply holes and corresponds to a respective one of the coolant gas groove opening sets.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

51.

UNIFORMITY CONTROL CIRCUIT FOR IMPEDANCE MATCH

      
Application Number 18010194
Status Pending
Filing Date 2021-11-02
First Publication Date 2023-08-10
Owner Lam Research Corporation (USA)
Inventor
  • Marakhtanov, Alexei M.
  • Kozakevich, Felix Leib
  • Ji, Bing
  • Holland, John P.

Abstract

An impedance match housing is described. The impedance match housing includes an impedance matching circuit having an input that is coupled to a radio frequency (RF) generator. The impedance matching circuit has an output that is coupled to a first RF strap. The impedance match housing includes a uniformity control circuit coupled in parallel to a portion of the first RF strap to modify uniformity in a processing rate of a substrate when the substrate is processed within a plasma chamber.

IPC Classes  ?

52.

Systems and Methods for Radiofrequency Signal Generator-Based Control of Impedance Matching System

      
Application Number 18012962
Status Pending
Filing Date 2021-11-09
First Publication Date 2023-08-10
Owner Lam Research Corporation (USA)
Inventor
  • Lyndaker, Bradford J.
  • Marakhtanov, Alexei
  • Kozakevich, Felix Leib
  • Hopkins, David

Abstract

An RF signal supply system for plasma generation includes an RF signal generator, an impedance matching system, and a control module. The RF signal generator includes a control system. The impedance matching system has an input connected to an output of the RF signal generator, an output connected to a plasma processing system, a gamma control capacitor, and a frequency control capacitor. The control module is connected in data communication with each of the RF signal generator and the impedance matching system. The control module is programmed to transmit control signals to the impedance matching system based on corresponding data received from the control system of the RF signal generator, where the control signals direct control of the gamma control capacitor and the frequency control capacitor. The control module is also programmed to transmit data received from the impedance matching system to the control system of the RF signal generator.

IPC Classes  ?

53.

SUBSTRATE TRANSFER DOOR ASSEMBLIES WITH RADIATING ELEMENTS FOR SUBSTRATE PROCESSING CHAMBERS

      
Application Number 18013161
Status Pending
Filing Date 2021-08-23
First Publication Date 2023-08-10
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Drewery, John
  • Inori, David
  • Desepte, Andre
  • Kinsler, Michael Julius

Abstract

A substrate transfer door assembly includes a body, one or more radiating elements, a member, and at least one lifting coupler. The body includes a central portion. At least the central portion of the body operates as a substrate transfer door and covers at least one of an opening of a liner or an opening of a chamber wall of a substrate processing chamber. The one or more radiating elements radiating heat away from the body. The member extends from the body. The at least one lifting coupler is connected to the member and movable in a vertical direction between an open position and a closed position to cover the at least one of the opening of the liner or the opening of the chamber wall with the central portion of the body.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

54.

SEAL VENTING IN A SUBSTRATE PROCESSING CHAMBER

      
Application Number 18013737
Status Pending
Filing Date 2021-06-30
First Publication Date 2023-08-10
Owner Lam Research Corporation (USA)
Inventor
  • Han, Hui Ling
  • Kinsler, Michael Julius
  • Madsen, Steven James
  • Pioux, Gabriel

Abstract

In some examples, a double seal arrangement for a substrate processing chamber comprises a radially inner barrier seal disposed within a barrier seal gland. The barrier seal gland includes an inner toe and an outer toe. A radially outer vacuum seal is disposed within a vacuum seal gland. The vacuum seal gland includes at least an inner toe. A first venting pathway is provided between the inner toe of the vacuum seal gland and the outer toe of the barrier seal gland, and a second venting pathway is provided between the outer toe of the barrier seal gland and the inner toe of the barrier seal gland. A third venting pathway is in communication at least with the inner toe of the barrier seal gland, and a vacuum source connected to at least one of the first, second, and third venting pathways.

IPC Classes  ?

55.

FRICTION STIR PROCESSING FOR CORROSION RESISTANCE

      
Application Number 18013742
Status Pending
Filing Date 2021-06-30
First Publication Date 2023-08-10
Owner Lam Research Corporation (USA)
Inventor
  • Martin, Keith Joseph
  • Linebarger, Jr., Nick Ray

Abstract

In some examples, techniques for enhancing a corrosion resistance of a component are provided. In some examples, the component includes a granular metallic material. A friction stir processing operation is performed on the material. The friction stir processing operation comprises passing a rotating head of a friction stir welding tool through a surface thickness of the granular metallic material in a treatment path.

IPC Classes  ?

  • C22F 3/00 - Changing the physical structure of non-ferrous metals or alloys by special physical methods, e.g. treatment with neutrons
  • C22F 1/04 - Changing the physical structure of non-ferrous metals or alloys by heat treatment or by hot or cold working of aluminium or alloys based thereon

56.

SUBSTRATE SUPPORT WITH UNIFORM TEMPERATURE ACROSS A SUBSTRATE

      
Application Number 18013768
Status Pending
Filing Date 2021-11-16
First Publication Date 2023-08-10
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Smith, Jeremy George
  • Matyushkin, Alexander
  • Samulon, Eric
  • Comendant, Keith
  • Yu, Yixuan

Abstract

A substrate support for a substrate processing system includes a baseplate and a spray coat layer arranged on the baseplate. The spray coat layer has a first thickness and a first thermal conductivity. A bond layer is arranged on the spray coat layer. The bond layer has a second thickness and a second thermal conductivity. A ceramic layer is arranged on the bond layer. At least one of the first thickness and the second thickness varies in at least one of a radial direction and an azimuthal direction such that a third thermal conductivity between the ceramic layer and the baseplate varies in the at least one of the radial direction and the azimuthal direction.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

57.

METHOD OF MOUNTING WIRES TO SUBSTRATE SUPPORT CERAMIC

      
Application Number 18010322
Status Pending
Filing Date 2021-07-12
First Publication Date 2023-08-10
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Mikhnenko, Oleksandr
  • Chau, Quan

Abstract

A substrate support assembly includes a baseplate, a ceramic plate arranged on the baseplate, and a plurality of wires. The ceramic plate includes a plurality of slots arranged on a side facing the baseplate and a plurality of electrically conducting terminals disposed in the plurality of slots, respectively. Each of the terminals includes a base portion connected to the ceramic plate, a second portion extending from the base portion towards the baseplate, and an opening in the second portion extending from an end of the second portion adjacent to the base portion to a distal end of the second portion. Each of the wires passes through the opening of the respective terminal and is braided around the distal end of the second portion of the respective terminal.

IPC Classes  ?

58.

Systems and Methods for Controlling Substrate Approach Toward a Target Horizontal Plane

      
Application Number 18295666
Status Pending
Filing Date 2023-04-04
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Hill, Douglas
  • Sweeney, Cian
  • Ranjan, Manish

Abstract

A determination is made of a real-time azimuthal position of a notch alignment feature located on a support surface of a substrate holder relative to a fixed reference ray extending perpendicularly away from a rotational axis of the substrate holder as the substrate holder rotates about the rotational axis. A determination is made of an approach initiation azimuthal position of the notch alignment feature relative to the fixed reference ray at which vertical movement of the substrate holder should initiate in order to have the notch alignment feature located at a prescribed azimuthal position relative to the fixed reference ray when the substrate holder reaches a prescribed vertical position. A determination is made of a time delay required to have the notch alignment feature located at the approach initiation azimuthal position. Vertical movement of the substrate holder is initiated in accordance with the determined time delay.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 21/12 - Process control or regulation
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C25D 17/06 - Suspending or supporting devices for articles to be coated

59.

Filter for a Plasma Plume

      
Application Number 18298853
Status Pending
Filing Date 2023-04-11
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Dekkers, Jan Matthijn
  • Bohm, Kristiaan Hendrikus Aloysius
  • Hopman, Willem Cornelis Lambert
  • Heuver, Jeroen Aaldert
  • Janssens, Jan Arnaud

Abstract

A filter for a pulsed laser deposition device includes a housing with two pass-through openings arranged in the housing wall and forming a pass-through channel for passing at least part of the plasma plume through the housing, which pass-through channel extends from one side of the housing to an opposite side of the housing, at least one primary blade arranged at a distance from and rotatable around a rotation axis, with the path of the at least one primary blade intersecting with the pass-through channel and with the at least one primary blade having a contact surface for contact with the plasma plume, and a drain channel connecting to a drain opening arranged in the housing wall.

IPC Classes  ?

  • B01D 45/14 - Separating dispersed particles from gases or vapours by gravity, inertia, or centrifugal forces by centrifugal forces generated by rotating vanes, discs, drums or brushes
  • C23C 14/28 - Vacuum evaporation by wave energy or particle radiation

60.

CONFORMAL THERMAL CVD WITH CONTROLLED FILM PROPERTIES AND HIGH DEPOSITION RATE

      
Application Number 18003098
Status Pending
Filing Date 2021-07-21
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Gupta, Awnish
  • Van Schravendijk, Bart J.
  • Pasquale, Frank Loren
  • Lavoie, Adrien
  • Varnell, Jason Alexander
  • Ramasagaram, Praneeth
  • Abel, Joseph R.
  • Petraglia, Jennifer Leigh
  • Austin, Dustin Zachary

Abstract

Methods and apparatuses for depositing dielectric films into features on semiconductor substrates are described herein. Methods involve depositing dielectric films by using controlled thermal chemical vapor deposition, with periodic passivation operations and densification to modulate film properties.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • C23C 16/56 - After-treatment
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
  • C23C 16/34 - Nitrides
  • C23C 16/40 - Oxides
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

61.

Protection System for Switches in Direct Drive Circuits of Substrate Processing Systems

      
Application Number 18009575
Status Pending
Filing Date 2021-06-10
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Long, Maolin
  • Wang, Yuhou
  • Martin, Michael John
  • Paterson, Alexander Miller

Abstract

A direct drive system for providing RF power to a component of a substrate processing system includes a direct drive circuit including a switch and configured to supply RF power to the component. A switch protection module is configured to monitor a load current and a load voltage in a processing chamber, calculate load resistance based on the load current and the load voltage, compare the load resistance to a first predetermined load resistance, and adjust at least one of an RF power limit and an RF current limit of the direct drive circuit based on the comparison.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • G01R 27/08 - Measuring resistance by measuring both voltage and current

62.

Voltage Transient Detector and Current Transient Detector

      
Application Number 18011188
Status Pending
Filing Date 2021-09-29
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Pease, John
  • Drewery, John

Abstract

A voltage transient detector includes circuitry for transmitting electrical current through a light emitting diode and a fuse that is serially connected between the light emitting diode and a reference potential, such that the light emitting diode is illuminated when the fuse is not blown. The voltage transient detector also includes circuitry for transmitting a controlled amount of electrical current through the fuse in conjunction with an occurrence of a voltage transient at a voltage measurement location, where the voltage transient exceeds a set transient threshold voltage. The controlled amount of electrical current transmitted through the fuse causing the fuse to blow and the light emitting diode to turn off, thereby indicating occurrence of the voltage transient at the voltage measurement location.

IPC Classes  ?

  • H02H 1/00 - EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS - Details of emergency protective circuit arrangements
  • H02H 3/04 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection - Details with warning or supervision in addition to disconnection, e.g. for indicating that protective apparatus has functioned
  • H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage

63.

SYSTEMS AND METHODS FOR CONTROLLING A PLASMA SHEATH CHARACTERISTIC

      
Application Number 18011826
Status Pending
Filing Date 2022-03-15
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Marakhtanov, Alexei M.
  • Caron, James Eugene
  • Holland, John Patrick
  • Kozakevich, Felix Leib
  • Bhowmick, Ranadeep
  • Ji, Bing

Abstract

Systems and methods for controlling a plasma sheath characteristic are described. One of the methods includes determining a first value of the plasma sheath characteristic of a plasma sheath formed within a plasma chamber. The method further includes determining whether the first value of the plasma sheath characteristic is within a predetermined range from a preset value of the plasma sheath characteristic. The method also includes modifying a variable of a radio frequency (RF) generator coupled to the plasma chamber via an impedance matching circuit upon determining that the first value is not within the predetermined range from the preset value. The operation of modifying the variable of the RF generator is performed until it is determined that the first value of the plasma sheath characteristic is within the predetermined range from the preset value.

IPC Classes  ?

64.

DELIVERY OF HIGH CONCENTRATIONS OF MOLECULAR HYDROGEN AND OTHER GASES TO SUBSTRATE PROCESSING SYSTEMS

      
Application Number 18013347
Status Pending
Filing Date 2022-06-15
First Publication Date 2023-08-03
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Ricci, Anthony John
  • Buan, Ramon Liwanag
  • Richter, Wayne Edward
  • Pena, Christopher J.
  • Amaya, Marissa Elena Ortiz

Abstract

A gas delivery system for substrate processing tool includes a first gas box configured to supply a first gas mixture including one or more gases selected from a first set of N gases to a first substrate processing chamber, where N is an integer greater than one. A second gas box is configured to selectively supply a second gas mixture including one or more gases selected from a second set of M gases to a second substrate processing chamber, where M is an integer greater than one. A third gas box is configured to supply a third gas to the first substrate processing chamber at a first concentration and to supply the third gas to the second substrate processing chamber at a second concentration. The third gas is incompatible with one or more gases in the first set of N gases and with one or more gas in the second set of M gases.

IPC Classes  ?

65.

MOVABLE DISK WITH APERTURE FOR ETCH CONTROL

      
Application Number 18013429
Status Pending
Filing Date 2022-05-17
First Publication Date 2023-08-03
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lin, Chih-Min
  • Huang, Shuogang
  • Yun, Seokmin
  • Chang, Chih-Yang
  • Chang, Chih-Ming
  • Cheng, Shih-Yuan

Abstract

A processing chamber includes a grid and a first disk. The grid includes a plurality of holes arranged in the processing chamber. The grid partitions the processing chamber into a first chamber in which plasma is generated and a second chamber in which a pedestal is configured to support a substrate. The first disk is arranged in the second chamber. The first disk is movable between the grid and the substrate when supported on the pedestal.

IPC Classes  ?

66.

SHOWERHEAD FACEPLATES WITH ANGLED GAS DISTRIBUTION PASSAGES FOR SEMICONDUCTOR PROCESSING TOOLS

      
Application Number 18001697
Status Pending
Filing Date 2021-06-14
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Mankidy, Pratik
  • Holland, John
  • De La Llera, Anthony
  • Dorai, Rajesh

Abstract

Showerhead faceplates for semiconductor processing chambers are provided that include one or more sets of gas distribution passages therethrough that extend at least partially along axes that are at an oblique angle to the showerhead faceplate center axis. Such angled gas distribution passages may be used to tailor the gas flow characteristics of such showerhead faceplates to produce various desired gas flow behaviors in the gas that is delivered to the wafer via such showerhead faceplates.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes

67.

SELECTIVE DEPOSITION USING GRAPHENE AS AN INHIBITOR

      
Application Number 18002043
Status Pending
Filing Date 2021-06-17
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Narkeviciute, Ieva
  • Varadarajan, Bhadri N.
  • Sharma, Kashish

Abstract

Graphene is selectively deposited on a metal layer relative to a dielectric layer of a semiconductor substrate. Dielectric material is selectively deposited on the dielectric layer relative to the metal layer of the semiconductor substrate. The graphene is a high-quality graphene film that serves as an inhibitor during deposition of the dielectric material. In some implementations, the dielectric material may be a metal oxide. In some implementations, the dielectric material may be a low-k dielectric material. The graphene remains throughout semiconductor integration processes. In some implementations, the graphene may be subsequently modified by to permit deposition on the surface of the graphene or the graphene may be subsequently removed.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/26 - Deposition of carbon only
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/56 - After-treatment
  • C23C 16/40 - Oxides

68.

HYBRID LIQUID/AIR COOLING SYSTEM FOR TCP WINDOWS

      
Application Number 18013736
Status Pending
Filing Date 2022-02-07
First Publication Date 2023-08-03
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Alberti, Andrea
  • Sriraman, Saravanapriyan
  • Drewery, John
  • Paterson, Alexander Miller

Abstract

A dielectric window assembly for a substrate processing system includes a dielectric window, a Faraday shield that is one of adjacent to the dielectric window, embedded within the dielectric window, and arranged in a recess in an upper surface of the dielectric window, and cooling channels arranged within the Faraday shield. The cooling channels are configured to flow coolant throughout the Faraday shield.

IPC Classes  ?

69.

SYSTEMS AND METHODS FOR PROVIDING SHUNT CANCELLATION OF PARASITIC COMPONENTS IN A PLASMA REACTOR

      
Application Number 18131341
Status Pending
Filing Date 2023-04-05
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Rangineni, Yaswanth
  • Kapoor, Sunil
  • Augustyniak, Edward
  • Sakiyama, Yukinori

Abstract

Systems and methods for negating an impedance associated with parasitic capacitance are described. One of the systems includes a plasma chamber having a housing. The housing includes a pedestal, a showerhead situated above the pedestal to face the pedestal, and a ceiling located above the showerhead. The system further includes a radio frequency (RF) transmission line coupled to the plasma chamber for transferring a modified RF signal to the showerhead. The system includes a shunt circuit coupled within a pre-determined distance from the ceiling. The shunt circuit is coupled to the RF transmission line for negating the impedance associated with the parasitic capacitance within the housing.

IPC Classes  ?

  • H03H 7/38 - Impedance-matching networks
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

70.

MODULAR RECIPE CONTROLLED CALIBRATION (MRCC) APPARATUS USED TO BALANCE PLASMA IN MULTIPLE STATION SYSTEM

      
Application Number 18174585
Status Pending
Filing Date 2023-02-24
First Publication Date 2023-08-03
Owner Lam Research Corporation (USA)
Inventor
  • Juco, Eller Y.
  • Leeser, Karl Frederick
  • French, David
  • Kapoor, Sunil
  • Bingham, Aaron
  • Metz, David Alan
  • Herzig, Brett
  • Hiester, Jacob L.
  • Knight, Brian

Abstract

A circuit tuning radio frequency (RF) power. The circuit includes a low to mid frequency (LF/HF) tuning circuit including a variable LF/MF capacitor coupled in series with an LF/MF inductor. The LF/MF tuning circuit is coupled between ground and a common node configured to receive an RF input. The circuit includes a high frequency (HF) tuning circuit coupled in parallel to the LF/MF tuning circuit between ground and the common node. The HF tuning circuit includes a variable HF capacitor coupled in series with an HF inductor. Cross parallel isolation occurs between the LF/MF inductor of the LF/MF tuning circuit and the HF inductor of the HF tuning circuit when adjusting the variable LF/MF capacitor or variable HF capacitor.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

71.

MECHANICAL SUPPRESSION OF PARASITIC PLASMA IN SUBSTRATE PROCESSING CHAMBER

      
Application Number 18129370
Status Pending
Filing Date 2023-03-31
First Publication Date 2023-07-27
Owner Lam Research Corporation (USA)
Inventor
  • Keil, Douglas
  • Augustyniak, Edward J.
  • Leeser, Karl Frederick
  • Sabri, Mohamed

Abstract

A system includes an electrode. The electrode includes a showerhead having a first stem portion and a head portion. A plurality of dielectric layers is vertically stacked between the electrode and a first surface of a conducting structure. The plurality of dielectric layers includes M dielectric layers arranged adjacent to the head portion and P dielectric portions arranged around the first stem portion. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap, and the third gap are selected to prevent parasitic plasma between the first surface and the electrode.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

72.

GAS BOX WITH CROSS-FLOW EXHAUST SYSTEM

      
Application Number 18002619
Status Pending
Filing Date 2021-11-15
First Publication Date 2023-07-27
Owner Lam Research Corporation (USA)
Inventor
  • Spyropoulos, Evangelos T.
  • Shareef, Iqbal A.

Abstract

Gas boxes for providing semiconductor processing gases are provided that incorporate a cross-flow ventilation system that may effectively remove potentially leaking gases from within the gas box at significantly lower volumetric flow rates than are possible with conventional gas box ventilation systems.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

73.

ADVANCED SELF ALIGNED MULTIPLE PATTERNING USING TIN OXIDE

      
Application Number 18002627
Status Pending
Filing Date 2021-07-21
First Publication Date 2023-07-27
Owner Lam Research Corporation (USA)
Inventor
  • Singhal, Akhil
  • Kanakasabapathy, Sivananda Krishnan

Abstract

Methods and apparatuses for performing spacer on spacer multiple patterning schemes using an exhumable first spacer material and a complementary second spacer material. Certain embodiments involve using a tin oxide spacer material for one of the spacer materials in spacer on spacer self aligned multiple patterning.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

74.

CARRIER RINGS WITH RADIALLY-VARIED PLASMA IMPEDANCE

      
Application Number 18002614
Status Pending
Filing Date 2021-06-21
First Publication Date 2023-07-27
Owner Lam Research Corporation (USA)
Inventor
  • Linebarger, Jr., Nick Ray
  • Shaikh, Fayaz A.
  • Lee, Kang Il

Abstract

Carrier rings with radially-varied plasma impedance are provided herein. In some embodiments, a carrier ring may include an outer ring that holds a removable inner ring. The outer ring may be formed of a dielectric material such as ceramic. The inner ring may be formed of a metal such as aluminum to provide a desired impedance. In some other embodiments, a carrier ring is formed from a single piece with radially-varying impedances.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

75.

SHOWERHEAD WITH REDUCED INTERIOR VOLUMES

      
Application Number 18002616
Status Pending
Filing Date 2021-07-22
First Publication Date 2023-07-27
Owner Lam Research Corporation (USA)
Inventor Morgan, Joseph Edgar

Abstract

Additively manufactured showerheads for semiconductor processing operations are disclosed that may have various features enabled by the use of such manufacturing techniques. In some implementations, such showerheads may have multiple independent flow paths featuring transverse passages arranged to form a rhombic lattice pattern and gas distribution ports and/or riser passages that are located at various intersections between such transverse passages. Such showerheads may also include features that improve their manufacturability while providing desired gas flow performance. For example, the cross-sections of the transverse passages may be designed such that they are generally triangular or pentagonal in shape, which may allow for more efficient use of available material volume within the showerhead for the purposes of providing gas flow passages while also providing geometries that take into account the limitations of typical additive manufacturing processes that may be used.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes

76.

TOOL AND METHOD FOR CHANDELIER SHOWERHEAD INSTALLATION

      
Application Number 18013731
Status Pending
Filing Date 2021-06-24
First Publication Date 2023-07-27
Owner Lam Research Corporation (USA)
Inventor Altecor, Aleksey V.

Abstract

An alignment device is provided to draw two components together in an aligned configuration. An example alignment device comprises a planetary gear set including a ring gear and at least two planetary gears and one or more side plates for supporting the gears. Each of the planetary gears includes an aperture sized to receive a threaded fastener for engagement with a respective threaded rod that is engaged with one of the two components, wherein rotation of the ring gear imparts rotational movement to the threaded fasteners to cause synchronized advancement of the alignment device along the threaded rods.

IPC Classes  ?

  • F16H 25/24 - Elements essential to such mechanisms, e.g. screws, nuts
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

77.

ELECTROFILL FROM ALKALINE ELECTROPLATING SOLUTIONS

      
Application Number 17995243
Status Pending
Filing Date 2021-04-06
First Publication Date 2023-07-20
Owner Lam Research Corporation (USA)
Inventor
  • Brogan, Lee J.
  • Huie, Matthew Martin
  • Liu, Yi Hua
  • Reid, Jonathan David

Abstract

Disclosed are alkaline electrodeposition solutions and apparatus and methods for using such solutions to electroplate metal. During electroplating, the solutions may produce superconformal fill of metal in features such as features having a critical dimension of about 20 nm or less. The metal electroplating process may be used during integrated circuit fabrication. For example, it may be used to fill trenches and vias in partially fabricated integrated circuits. The electroplated metal may be copper. The copper may be electroplated on a substrate material that is less noble than copper.

IPC Classes  ?

  • C25D 3/38 - Electroplating; Baths therefor from solutions of copper
  • C25D 21/10 - Agitating of electrolytes; Moving of racks
  • C25D 5/34 - Pretreatment of metallic surfaces to be electroplated
  • C25D 21/12 - Process control or regulation

78.

METHOD FOR CLEANING A CHAMBER

      
Application Number 18008069
Status Pending
Filing Date 2021-06-08
First Publication Date 2023-07-20
Owner Lam Research Corporation (USA)
Inventor
  • Lin, Ran
  • Yang, Wenbing
  • Mukherjee, Tamal
  • Yu, Jengyi
  • Tan, Samantha Siamhwa
  • Pan, Yang
  • Fan, Yiwen

Abstract

A method for cleaning a plasma processing chamber comprising one or more cycles is provided. Each cycle comprises performing an oxygen containing plasma cleaning phase, performing a volatile chemistry type residue cleaning phase, and performing a fluorine containing plasma cleaning phase.

IPC Classes  ?

79.

PROCESS CONTROL FOR ION ENERGY DELIVERY USING MULTIPLE GENERATORS AND PHASE CONTROL

      
Application Number 18010204
Status Pending
Filing Date 2021-07-06
First Publication Date 2023-07-20
Owner Lam Research Corporation (USA)
Inventor
  • Bhowmick, Ranadeep
  • Kozakevich, Felix
  • Marakhtanov, Alexei
  • Holland, John
  • Hudson, Eric

Abstract

A method for applying RF power in a plasma process chamber is provided, including: generating a first RF signal; generating a second RF signal; generating a third RF signal; wherein the first, second, and third RF signals are generated at different frequencies; combining the first, second and third RF signals to generate a combined RF signal, wherein a wave shape of the combined RF signal is configured to approximate a sloped square wave shape; applying the combined RF signal to a chuck in the plasma process chamber.

IPC Classes  ?

80.

SURFACE MODIFICATION FOR METAL-CONTAINING PHOTORESIST DEPOSITION

      
Application Number 17998354
Status Pending
Filing Date 2021-05-25
First Publication Date 2023-07-20
Owner Lam Research Corporation (USA)
Inventor
  • Yu, Jengyi
  • Li, Da
  • Lee, Younghee
  • Tan, Samantha S.H.
  • Jensen, Alan J.
  • Xue, Jun
  • Manumpil, Mary Anne

Abstract

Techniques described herein relate to methods, apparatus, and systems for promoting adhesion between a substrate and a metal-containing photoresist. For instance, the method may include receiving the substrate in a reaction chamber, the substrate having a first material exposed on its surface, the first material including a silicon-based material and/or a carbon-based material; generating a plasma from a plasma generation gas source that is substantially free of silicon, where the plasma includes chemical functional groups; exposing the substrate to the plasma to modify the surface of the substrate by forming bonds between the first material and chemical functional groups from the plasma; and depositing the metal-containing photoresist on the modified surface of the substrate, where the bonds between the first material and the chemical functional groups promote adhesion between the substrate and the metal-containing photoresist.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • G03F 7/09 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers
  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/11 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers

81.

ELECTRO-OXIDATIVE METAL REMOVAL ACCOMPANIED BY PARTICLE CONTAMINATION MITIGATION IN SEMICONDUCTOR PROCESSING

      
Application Number 17998415
Status Pending
Filing Date 2021-05-05
First Publication Date 2023-07-20
Owner Lam Research Corporation (USA)
Inventor
  • Thorkelsson, Kari
  • Banik, Ii, Stephen J.
  • Buckalew, Bryan L.
  • Mayer, Steven T.

Abstract

During electro-oxidative metal removal on a semiconductor substrate, the substrate having a metal layer is anodically biased and the metal is electrochemically dissolved into an electrolyte. Metal particles (e.g., copper particles when the dissolved metal is copper) can inadvertently form on the surface of the substrate during electrochemical metal removal and cause defects during subsequent semiconductor processing. Contamination with such particles can be mitigated by preventing particle formation and/or by dissolution of particles. In one implementation, mitigation involves using an electrolyte that includes an oxidizer, such as hydrogen peroxide, during the electrochemical metal removal. An electrochemical metal removal apparatus in one embodiment has a conduit for introducing an oxidizer to the electrolyte and a sensor for monitoring the concentration of the oxidizer in the electrolyte.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • C25F 3/12 - Etching of semiconducting materials

82.

REMOVAL OF TIN OXIDE IN CHAMBER CLEANING

      
Application Number 18001590
Status Pending
Filing Date 2021-06-10
First Publication Date 2023-07-20
Owner Lam Research Corporation (USA)
Inventor
  • Ha, Jeongseok
  • Liu, Pei-Chi

Abstract

Process chambers are cleaned from tin oxide deposits by a method that includes a step of forming a volatile tin-containing compound by exposing the tin oxide to a mixture of hydrogen (H2) and a hydrocarbon in a plasma, followed by a step that removes a carbon-containing polymer that formed as a result of the hydrocarbon exposure. The carbon-containing polymer can be removed by exposing the carbon-containing polymer to an oxygen-containing reactant (e.g., to O2 in a plasma), or to H2 in an absence of a hydrocarbon. These steps are repeated as many times as necessary to clean the process chamber. The method can be used to clean ALD, CVD, and PVD process chambers and is particularly useful for cleaning at a relatively low temperature of less than about 120° C.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • H01L 21/311 - Etching the insulating layers

83.

SYNCHRONIZATION OF RF PULSING SCHEMES AND OF SENSOR DATA COLLECTION

      
Application Number 18009978
Status Pending
Filing Date 2021-10-15
First Publication Date 2023-07-20
Owner Lam Research Corporation (USA)
Inventor
  • Drewery, John Stephen
  • Wu, Ying
  • Paterson, Alexander Miller
  • Albarede, Luc

Abstract

Systems and methods for synchronization of radio frequency (RF) pulsing schemes and of sensor data collection are described. One of the methods includes receiving, by an RF generator, a first set of one or more variable levels and one or more duty cycles of an RF signal. The method further includes receiving, by the RF generator from a pulse controller, a synchronization signal having a plurality of pulses. The method also includes generating, during a clock cycle of a clock signal, multiple instances of a first plurality of states of the RF signal in synchronization with the plurality of pulses of the synchronization signal. Each of the first plurality of states of the RF signal has a corresponding one of the one or more variable levels of the first set and a corresponding one of the one or more duty cycles of the first set.

IPC Classes  ?

84.

INTERMITTENT STAGNANT FLOW

      
Application Number 18010990
Status Pending
Filing Date 2021-06-30
First Publication Date 2023-07-20
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Keil, Douglas L.
  • Hollister, Alice G.
  • Leeser, Karl Frederick

Abstract

A method for removing residue deposits from a reaction chamber includes supplying a cleaning gas into the reaction chamber via direct delivery from a remote plasma source (RPS). The cleaning gas forms a plurality of gas flow streamlines within the reaction chamber. Each of the streamlines originates at an injection point for receiving the cleaning gas and terminates at a chamber pump port coupled to a fore line for evacuating the cleaning gas. A flow characteristic of the cleaning gas is modified to redirect at least a portion of the gas flow streamlines to circulate in proximity to an inner perimeter of the reaction chamber to remove the residue deposits or to enhance the diffusion of cleaning species to surfaces to be cleaned. The inner perimeter is disposed along one or more vertical surfaces of the reaction chamber that are orthogonal to a horizontal surface including the injection point.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

85.

CONTROL OF MASK CD

      
Application Number 18011477
Status Pending
Filing Date 2022-02-25
First Publication Date 2023-07-20
Owner Lam Research Corporation (USA)
Inventor
  • Jiang, Beibei
  • Ozel, Taner
  • Chen, Chen
  • Pi, Shuang
  • Agarwal, Daksh
  • Xu, Qing
  • Wong, Merrett
  • Mukhopadhyay, Amit

Abstract

A method for controlling a critical dimension of a mask layer is described. The method includes receiving a first primary parameter level, a second primary parameter level, a first secondary parameter level, a second secondary parameter level, and a third secondary parameter level. The method also includes generating a primary signal having the first primary parameter level, and transitioning the primary signal from the first primary parameter level to the second primary parameter level. The method further includes generating a secondary radio frequency (RF) signal having the first secondary parameter level, and transitioning the secondary RF signal from the first secondary parameter level to the second secondary parameter level. The method includes transitioning the secondary RF signal from the second secondary parameter level to the third secondary parameter level.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/66 - Testing or measuring during manufacture or treatment

86.

REMOTE-PLASMA CLEAN (RPC) DIRECTIONAL-FLOW DEVICE

      
Application Number 18177293
Status Pending
Filing Date 2023-03-02
First Publication Date 2023-07-13
Owner Lam Research Corporation (USA)
Inventor
  • Janicki, Michael John
  • Lee, James Forest

Abstract

Various embodiments include apparatuses, systems, and methods for using a remote-plasma cleaning system with a directional-flow device for concurrently cleaning multiple processing stations in a processing tool used in the semiconductor and allied fields. In one example, an apparatus used to perform a remote-plasma clean (RPC) in a multi-station process chamber is disclosed and includes an RPC directional-flow device that is to be coupled between an RPC reactor and the process chamber. The RPC directional-flow device includes a number of ramped gas-diversion areas to direct at least a radical species generated by the RPC reactor to a separate one of the processing stations. An incoming cleaning-gas diversion hub is to receive the radical species and distribute at least the species substantially-uniformly to each of the of the ramped gas-diversion areas. Other apparatuses, systems, and methods are disclosed.

IPC Classes  ?

  • G05B 19/4097 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by using design data to control NC machines, e.g. CAD/CAM
  • H01J 37/32 - Gas-filled discharge tubes

87.

AUTOMATED VISUAL-INSPECTION SYSTEM

      
Application Number 17927661
Status Pending
Filing Date 2021-05-26
First Publication Date 2023-07-13
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Anderson, Collin Michael
  • Mosely, Roderick

Abstract

Various examples include systems, apparatuses, and methods to perform an automated visual-inspection of components undergoing various stages of fabrication. In one example, an inspection system includes a number of robots, each having a camera, to inspect a component for defects at various stages of fabrication. Generally, each of the cameras is located at a different geographical location corresponding to the various stages in the fabrication of the component. At least some of the cameras are arranged to inspect all surfaces of the component that are not facing a table upon which the component is mounted. The system also includes a respective data-collection station electronically coupled to each the number of robots and an associated one of the cameras. A master data-collection station is electronically coupled to each of the data-collection stations. Other systems, apparatuses, and methods are disclosed.

IPC Classes  ?

88.

INERT GAS IMPLANTATION FOR HARD MASK SELECTIVITY IMPROVEMENT

      
Application Number 17997697
Status Pending
Filing Date 2021-04-22
First Publication Date 2023-07-13
Owner Lam Research Corporation (USA)
Inventor
  • Rigsby, Daniela Anjos
  • Puthenkovilakam, Ragesh
  • Hollister, Alice G.
  • Zhao, Lie

Abstract

An amorphous carbon hard mask is formed having low hydrogen content and low sp3 carbon bonding but high modulus and hardness. The amorphous carbon hard mask is formed by depositing an amorphous carbon layer at a low temperature in a plasma deposition chamber and treating the amorphous carbon layer to a dual plasma-thermal treatment. The dual plasma-thermal treatment includes exposing the amorphous carbon layer to inert gas plasma for implanting an inert gas species in the amorphous carbon layer and exposing the amorphous carbon layer to a high temperature. The amorphous carbon hard mask has high etch selectivity relative to underlying materials.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/311 - Etching the insulating layers
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/26 - Deposition of carbon only
  • C23C 16/56 - After-treatment

89.

IN-FEATURE WET ETCH RATE RATIO REDUCTION

      
Application Number 18000562
Status Pending
Filing Date 2021-06-01
First Publication Date 2023-07-13
Owner Lam Research Corporation (USA)
Inventor
  • Gupta, Awnish
  • Curtin, Ian John
  • Agnew, Douglas Walter
  • Pasquale, Frank Loren
  • Jeon, Eli
  • Lavoie, Adrien

Abstract

Various embodiments herein relate to methods and apparatus for depositing silicon oxide using thermal ALD or thermal CVD. In one aspect of the disclosed embodiments, a method for depositing silicon oxide is provided, the method including: (a) receiving the substrate in a reaction chamber; (b) introducing a first flow of a first reactant into the reaction chamber and exposing the substrate to the first reactant, where the first reactant includes a silicon-containing reactant; (c) introducing a second flow of a second reactant into the reaction chamber to cause a reaction between the first reactant and the second reactant, (i) where the second reactant includes hydrogen (H2) and an oxygen-containing reactant, (ii) where the reaction deposits silicon oxide on the substrate, and (iii) where the reaction is initiated when a pressure in the reaction chamber is greater than 10 Torr and equal to or less than about 40 Torr.

IPC Classes  ?

  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

90.

FLAT BOTTOM SHADOW RING

      
Application Number 18009254
Status Pending
Filing Date 2021-06-10
First Publication Date 2023-07-13
Owner Lam Research Corporation (USA)
Inventor
  • Wei, Lai
  • Kim, Ji Soo
  • Miller, Alan Jeffrey
  • Thie, William
  • Lin, Frank Yun
  • Han, Jun Hee Hee
  • Liu, Jie
  • Chiang, Conan
  • Martin, Michael John

Abstract

In some examples, a flat Bottom Shadow Ring (fBSR) is provided for processing a substrate in a processing chamber. An example fBSR comprises an overhang for covering an edge of the substrate in the processing chamber. The overhang includes a fiat zone that extends radially outward over the outer edge of the substrate.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/3065 - Plasma etching; Reactive-ion etching

91.

CONTROL OF PULSING FREQUENCIES AND DUTY CYCLES OF PARAMETERS OF RF SIGNALS

      
Application Number 18009308
Status Pending
Filing Date 2021-06-08
First Publication Date 2023-07-13
Owner Lam Research Corporation (USA)
Inventor
  • Kamp, Tom A.
  • Wang, Yuhou
  • Martin, Michael John

Abstract

A method for pulsing is described. The method includes generating a first radio frequency (RF) signal, and pulsing a parameter of the first RF signal between a first parameter level and a second parameter level at a pulsing frequency during a cycle of a digital pulsed signal. The method further includes generating a second RF signal, and pulsing a parameter of the second RF signal at a higher pulsing frequency than the pulsing frequency of the parameter of the first RF signal during the cycle. During the cycle, a start time of pulsing the parameter of the first RF signal is synchronized with a start time of pulsing the parameter of the second RF signal and an end time of pulsing the parameter of the first RF signal is synchronized with an end time of pulsing the parameter of the second RF signal.

IPC Classes  ?

92.

INCREASING PLASMA UNIFORMITY IN A RECEPTACLE

      
Application Number 17997802
Status Pending
Filing Date 2021-04-30
First Publication Date 2023-07-13
Owner Lam Research Corporation (USA)
Inventor
  • Guo, Tongtong
  • Batzer, Rachel E.
  • Qiu, Huatan
  • Chen, Lee
  • Gong, Bo
  • Gui, Zhe

Abstract

An apparatus for forming a plasma may include one or more coupling ports to accept and RF current. The apparatus may additionally include a receptacle to accommodate one or more gases, in which the receptacle is oriented along a first axis. The apparatus may additionally include an RF coupling structure, oriented in a plane and substantially surrounding the receptacle, the RF coupling structure can be configured to conduct an RF current to bring about formation of the plasma within the receptacle. The apparatus may further include one or more linkages, coupled to the RF coupling structure, which may permit the plane of the RF coupling structure to pivot about a second axis so as to tilt the plane of the RF coupling structure toward the first axis.

IPC Classes  ?

93.

PULSING REMOTE PLASMA FOR ION DAMAGE REDUCTION AND ETCH UNIFORMITY IMPROVEMENT

      
Application Number 18008761
Status Pending
Filing Date 2021-06-11
First Publication Date 2023-07-13
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Luo, Wei Yi
  • Hsu, Chih-Hsun
  • Shiau, Huai-Suen
  • Wang, Tianqi

Abstract

A method of performing pulsed remote plasma etching includes arranging a substrate in a processing chamber configured to perform pulsed remote plasma etching, setting at least one process parameter of the processing chamber, supplying at least one gas mixture to an upper chamber region of the processing chamber, supplying, in an ON period, a first voltage to coils arranged around the upper chamber region to energize the at least one gas mixture and generate plasma within the upper chamber region of the processing chamber, turning off the first voltage in an OFF period to discontinue generating plasma within the upper chamber region of the processing chamber, and alternating between supplying the first voltage in the ON period and turning off the first voltage in the OFF period to generate pulsed remote plasma within the upper chamber region of the processing chamber.

IPC Classes  ?

94.

MATCHED CHEMISTRY COMPONENT BODY AND COATING FOR SEMICONDUCTOR PROCESSING CHAMBER

      
Application Number 18009903
Status Pending
Filing Date 2021-06-16
First Publication Date 2023-07-13
Owner Lam Research Corporation (USA)
Inventor
  • Pape, Eric A.
  • Detert, Douglas

Abstract

A component for use in a semiconductor processing chamber is provided. A component body of a dielectric material has a semiconductor processing facing surface. A coating of a dielectric material is on at least the semiconductor processing facing surface, wherein the dielectric material of the component body has a same stoichiometry as the dielectric material of the coating.

IPC Classes  ?

95.

PLASMA UNIFORMITY CONTROL USING A PULSED MAGNETIC FIELD

      
Application Number 18010453
Status Pending
Filing Date 2021-11-02
First Publication Date 2023-07-13
Owner Lam Research Corporation (USA)
Inventor
  • Marakhtanov, Alexei
  • Ji, Bing
  • Lucchesi, Ken
  • Holland, John

Abstract

In some implementations, a method for performing a plasma process in a chamber is provided, including: supplying a process gas to the chamber; applying pulsed RF power to the process gas in the chamber, the pulsed RF power being provided at a predefined frequency, wherein the applying of the pulsed RF power to the process gas generates a plasma in the chamber; during the applying of the RF power, applying a pulsed DC current to a magnetic coil that is disposed over the chamber, wherein the pulsed DC current is provided at the predefined frequency.

IPC Classes  ?

96.

SUBSTRATE PEDESTAL INCLUDING BACKSIDE GAS-DELIVERY TUBE

      
Application Number 18123153
Status Pending
Filing Date 2023-03-17
First Publication Date 2023-07-13
Owner Lam Research Corporation (USA)
Inventor
  • Gomm, Troy Alan
  • Linebarger, Jr., Nick Ray

Abstract

A semiconductor substrate processing apparatus includes a vacuum chamber having a processing zone in which a semiconductor substrate may be processed, a process gas source in fluid communication with the vacuum chamber for supplying a process gas into the vacuum chamber, a showerhead module through which process gas from the process gas source is supplied to the processing zone of the vacuum chamber, and a substrate pedestal module. The substrate pedestal module includes a platen made of ceramic material having an upper surface configured to support a semiconductor substrate thereon during processing, a stem made of ceramic material having an upper stem flange that supports the platen, and a backside gas tube made of ceramic material that is located in an interior of the stem. The backside gas tube includes an upper gas tube flange that is located between a lower surface of the platen and an upper surface of the upper stem flange wherein the backside gas tube is in fluid communication with at least one backside gas passage of the platen and the backside gas tube is configured to supply a backside gas to a region below a lower surface of a semiconductor substrate that is to be supported on the upper surface of the platen during processing.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • B32B 37/10 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the pressing technique, e.g. using direct action of vacuum or fluid pressure
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • C23C 16/52 - Controlling or regulating the coating process
  • H01J 37/32 - Gas-filled discharge tubes

97.

SEALING SURFACES OF COMPONENTS USED IN PLASMA ETCHING TOOLS USING ATOMIC LAYER DEPOSITION

      
Application Number 18009238
Status Pending
Filing Date 2021-06-15
First Publication Date 2023-07-06
Owner Lam Research Corporation (USA)
Inventor
  • Koshy, Robin
  • Xu, Lin
  • Daugherty, John

Abstract

Sealing various machined component parts used in plasma etching chambers using an Atomic Layer Deposition (ALD) coating. By sealing the component parts with the ALD layer, surface erosion/etch caused by repeated exposure to plasma during workpiece fabrication is eliminated or significantly mitigated. As a result, unwanted particle generation, caused by erosion, is eliminated or significantly reduced, preventing contamination within the plasma etching chamber.

IPC Classes  ?

98.

Arcing Reduction in Wafer Bevel Edge Plasma Processing

      
Application Number 18010760
Status Pending
Filing Date 2021-08-12
First Publication Date 2023-07-06
Owner Lam Research Corporation (USA)
Inventor
  • Hua, Xuefeng
  • Luo, Wei Yi
  • Chen, Jack

Abstract

Methods and systems for processing a bevel edge of a wafer in a bevel plasma chamber. The method includes receiving a pulsed mode setting for a RF generator of the bevel plasma chamber. The method includes identifying a duty cycle for the pulsed mode, the duty cycle defining an ON time and an OFF time during each cycle of power delivered by the generator. The method includes calculating or accessing a compensation factor to an input RF power setting of the generator. The compensation factor is configured to add an incremental amount of power to the input power setting to account for a loss in power attributed to the duty cycle to be run in the pulsed mode. The method is configured to run the generator in the pulse mode with the duty cycle and the pulsing frequency. The generator is configured to generate the input power in pulsing mode that includes incremental amount of power to achieve an effective power in the bevel plasma chamber to achieve a target bevel processing throughput, while reducing charge build-up that causes arcing damage.

IPC Classes  ?

99.

DUTY CYCLE CONTROL TO ACHIEVE UNIFORMITY

      
Application Number 18011131
Status Pending
Filing Date 2021-12-23
First Publication Date 2023-07-06
Owner Lam Research Corporation (USA)
Inventor
  • Marakhtanov, Alexei M.
  • Kozakevich, Felix Leib
  • Ji, Bing
  • Holland, John P.
  • Bhowmick, Ranadeep

Abstract

A method for achieving a first uniformity level in a processing rate across a surface of a substrate is described. The method includes receiving the first uniformity level to be achieved across the surface of the substrate and identifying a first plurality of duty cycles associated with a first plurality of states based on the first uniformity level. The first plurality of states are of a variable of a first radio frequency (RF) signal. The method further includes controlling an RF generator to generate the first RF signal having the first plurality of duty cycles.

IPC Classes  ?

100.

SURFACE PRETREATMENT FOR ELECTROPLATING NANOTWINNED COPPER

      
Application Number 17998886
Status Pending
Filing Date 2021-05-12
First Publication Date 2023-07-06
Owner Lam Research Corporation (USA)
Inventor
  • Oberst, Justin
  • Buckalew, Bryan L.
  • Ponnuswamy, Thomas Anand
  • Mayer, Steven T.
  • Banik, Ii, Stephen J.

Abstract

Nanotwinned copper and non-nanotwinned copper may be electroplated to form mixed crystal structures such as 2-in-1 copper via and RDL structures or 2-in-1 copper via and pillar structures. Nanotwinned copper may be electroplated on a non-nanotwinned copper layer by pretreating a surface of the non-nanotwinned copper layer with an oxidizing agent or other chemical reagent. Alternatively, nanotwinned copper may be electroplated to partially fill a recess in a dielectric layer, and non-nanotwinned copper may be electroplated over the nanotwinned copper to fill the recess. Copper overburden may be subsequently removed.

IPC Classes  ?

  • C25D 5/02 - Electroplating of selected surface areas
  • C25D 5/34 - Pretreatment of metallic surfaces to be electroplated
  • C25D 3/38 - Electroplating; Baths therefor from solutions of copper
  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
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