Lam Research Corporation

United States of America

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H01J 37/32 - Gas-filled discharge tubes 1,114
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components 638
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber 520
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 441
H01L 21/311 - Etching the insulating layers 280
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1.

MULTI-STATE RF PULSING IN CYCLING RECIPES TO REDUCE CHARGING INDUCED DEFECTS

      
Application Number 18689825
Status Pending
Filing Date 2022-08-12
First Publication Date 2024-07-18
Owner Lam Research Corporation (USA)
Inventor
  • Zhang, He
  • Li, Chen
  • Lai, Kevin
  • Mackie, Neil Macaraeg

Abstract

A method for etching in plasma processing in a plasma chamber, including continually rotating between a first etch cycle and a second etch cycle for a period of time to etch a feature in a masked substrate. The method including performing the first etch cycle on the masked substrate using a first etching chemistry for a first sub-period. The first etch cycle is continually rotated between a first state configured for passivation, a second state, and third state configured for etching the masked substrate. During the second state of the first etch cycle, a first tuning step is performed by tuning the first etching chemistry, a high frequency RF power and a low frequency RF power to provide extended passivation to the feature in the masked substrate. The method including performing the second etch cycle on the masked substrate using a second etching chemistry for a second sub-period. The second etch cycle is continually rotated between the first state configured for electrical discharge, a fourth state, and the third state configured for etching the feature in the masked substrate. During the fourth state of the second etch cycle, a second tuning step is performed by tuning the second etching chemistry, the high frequency RF power, and the low frequency RF power to provide punch-through etching to the feature in the masked substrate.

IPC Classes  ?

2.

DYNAMIC PRECURSOR DOSING FOR ATOMIC LAYER DEPOSITION

      
Application Number 18622472
Status Pending
Filing Date 2024-03-29
First Publication Date 2024-07-18
Owner Lam Research Corporation (USA)
Inventor
  • Kumar, Purushottam
  • Lavoie, Adrien
  • Qian, Jun
  • Kang, Hu
  • Karim, Ishtak
  • Ou, Fung Suong

Abstract

Methods and apparatuses for controlling precursor flow in a semiconductor processing tool are disclosed. A method may include flowing gas through a gas line, opening an ampoule valve(s), before a dose step, to start a flow of precursor from the ampoule to a process chamber through the gas line, closing the ampoule valve(s) to stop the precursor from flowing out of the ampoule, opening a process chamber valve, at the beginning of the dose step, to allow the flow of precursor to enter the process chamber, and closing the process chamber valve, at the end of the dose step, to stop the flow of precursor from entering the process chamber. A controller may include at least one memory and at least one processor and the at least one memory may store instructions for controlling the at least one processor to control precursor flow in a semiconductor processing tool.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

3.

DEPOSITING A CARBON HARDMASK BY HIGH POWER PULSED LOW FREQUENCY RF

      
Application Number 18493614
Status Pending
Filing Date 2023-10-24
First Publication Date 2024-07-11
Owner Lam Research Corporation (USA)
Inventor
  • Weimer, Matthew Scott
  • Subramonium, Pramod
  • Puthenkovilakam, Ragesh
  • Bai, Rujun
  • French, David

Abstract

Methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate include pulsing a low frequency radio frequency component at a high power. Pulsing low frequency power may be used to increase the selectivity or reduce the stress of an AHM. The AHM may then be used to etch features into underlying layers of the substrate.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/517 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using a combination of discharges covered by two or more of groups
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

4.

APPARATUSES FOR THERMAL MANAGEMENT OF A PEDESTAL AND CHAMBER

      
Application Number 18563666
Status Pending
Filing Date 2022-05-26
First Publication Date 2024-07-11
Owner Lam Research Corporation (USA)
Inventor
  • Miller, Aaron Blake
  • Durbin, Aaron
  • Chandrasekharan, Ramesh
  • Streng, Bradley Taylor

Abstract

Apparatuses not only capable of reducing unwanted radiative heat loss from a pedestal of a substrate processing system, but also capable of reducing radiative heat transfer to other components within a chamber of the substrate processing system.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

5.

BLADE-TYPE END EFFECTOR WITH ANGULAR COMPLIANCE MECHANISM

      
Application Number 18560334
Status Pending
Filing Date 2022-05-11
First Publication Date 2024-07-11
Owner Lam Research Corporation (USA)
Inventor
  • Embertson, Ross C.
  • Senn, Brandon Lee
  • Ditmore, Charles N.

Abstract

Disclosed herein are wafer handling robots and related systems for providing a blade-type end effector that has a built-in compliance mechanism that allows the end effector blades to rotate by a small amount relative to a wrist unit housing of the end effector wrist unit due to gravitational loading in both a first configuration and a second configuration in which the wrist unit housing is flipped upside down from the first configuration. Such a system may be used in conjunction with end effector blades made of high-stiffness materials such as silicon carbide, allowing such end effector blades to be used in conditions that normally require end effector blades made of more compliant materials.

IPC Classes  ?

6.

IMAGE ANALYSIS OF PLASMA CONDITIONS

      
Application Number 18572075
Status Pending
Filing Date 2022-07-01
First Publication Date 2024-07-11
Owner Lam Research Corporation (USA)
Inventor
  • Danek, Michal
  • Haskell, Benjamin Allen
  • Reddy, Kapu Sirish
  • Badt, David
  • Williams, Brian Joseph
  • Franzen, Paul
  • Leeser, Karl Frederick
  • Petraglia, Jennifer Leigh
  • Sakiyama, Yukinori
  • Sawlani, Kapil

Abstract

Multi-pixel sensors such as camera sensors may be configured to capture two-dimensional and/or three-dimensional images of the interior of a process chamber or other fabrication tool. The sensors may be configured to capture pixelated electromagnetic radiation intensity information from within the interior of such process chamber before, during, and/or after processing of a substrate in the chamber. Such sensors may also be utilized for control, predictive, and/or diagnostic applications.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • G06T 7/00 - Image analysis
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

7.

HALOGEN-AND ALIPHATIC-CONTAINING ORGANOTIN PHOTORESISTS AND METHODS THEREOF

      
Application Number 18546879
Status Pending
Filing Date 2022-01-28
First Publication Date 2024-07-11
Owner Lam Research Corporation (USA)
Inventor
  • Weidman, Timothy William
  • Hansen, Eric Calvin
  • Wu, Chenghao

Abstract

The present disclosure relates to a composition formed with a precursor including a C1-4 haloaliphatic or C1-4 aliphatic group or vinyl group (—CH═CH2) and other unsaturated substituents, as well as methods for forming and employing such compositions. In particular embodiments, the haloaliphatic group is a C1-2 haloalkyl group, which in turn provides a resist film having enhanced radiation absorptivity and/or minimal film shrinkage (e.g., upon radiation exposure and/or post-exposure bake). In other embodiments, the aliphatic group is a C1-2 alkyl or vinyl group and other unsaturated substituents, which can be dry deposited. In non-limiting embodiments, the radiation can include extreme ultraviolet (EUV) or deep ultraviolet (DUV) radiation.

IPC Classes  ?

  • G03F 7/004 - Photosensitive materials
  • G03F 7/095 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/20 - Exposure; Apparatus therefor
  • G03F 7/30 - Imagewise removal using liquid means
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma

8.

NON-METAL INCORPORATION IN MOLYBDENUM ON DIELECTRIC SURFACES

      
Application Number 18547481
Status Pending
Filing Date 2022-02-18
First Publication Date 2024-07-11
Owner Lam Research Corporation (USA)
Inventor
  • Schloss, Lawrence
  • Collins, Joshua
  • Kennedy, Griffin John
  • Bamnolker, Hanna
  • Lee, Sang-Hyeob
  • Van Cleemput, Patrick
  • Gopinath, Sanjay

Abstract

Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/14 - Deposition of only one other metal element
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/52 - Controlling or regulating the coating process

9.

MULTI-SECTIONAL PLASMA CONFINEMENT RING STRUCTURE

      
Application Number 18559313
Status Pending
Filing Date 2022-05-16
First Publication Date 2024-07-11
Owner Lam Research Corporation (USA)
Inventor
  • Marakhtanov, Alexei
  • Kellogg, Michael C.

Abstract

A confinement ring for use in a plasma processing chamber includes an upper horizontal section, an upper vertical section, a mid-section, a lower vertical section, a lower horizontal section and a vertical extension. The upper horizontal section extends between an inner upper radius and a first outer radius of the confinement ring. The mid-section extends between inner upper radius and a second outer radius of the confinement ring. The lower horizontal section extends between an inner lower radius and the second outer radius, and the vertical extension extends down from the lower horizontal section proximate to the inner lower radius. The upper vertical section extends between the upper horizontal section and the mid-section proximate to the inner upper radius, and the lower vertical section extends between the mid-section and the lower horizontal section proximate to the second outer radius.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

10.

VOID FREE LOW STRESS FILL

      
Application Number 18616741
Status Pending
Filing Date 2024-03-26
First Publication Date 2024-07-11
Owner Lam Research Corporation (USA)
Inventor
  • Chandrashekar, Anand
  • Yang, Tsung-Han

Abstract

Provided herein are methods of depositing low stress and void free metal films in deep features and related apparatus. Embodiments of the methods include treating the sidewalls of the holes to inhibit metal deposition while leaving the feature bottom untreated. In subsequent deposition operations, metal precursor molecules diffuse to the feature bottom for deposition. The process is repeated with subsequent inhibition operations treating the remaining exposed sidewalls. By repeating inhibition and deposition operations, high quality void free fill can be achieved. This allows high temperature, low stress deposition to be performed.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

11.

TRIPOLAR ELECTRODE ARRANGEMENT FOR ELECTROSTATIC CHUCKS

      
Application Number 18278276
Status Pending
Filing Date 2022-03-11
First Publication Date 2024-07-11
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Leeser, Karl Frederick
  • Blank, Richard
  • Hiester, Jacob L.

Abstract

A system comprises a pedestal and a controller. The pedestal is arranged below a showerhead in a processing chamber and includes at least three electrodes to clamp a substrate to the pedestal during processing. The controller is configured to measure a pedestal-to-showerhead gap and at least one of a magnitude and a direction of a relative tilt between the pedestal and the showerhead by sensing impedances between the at least three electrodes and the showerhead.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

12.

APPARATUSES FOR UNIFORM FLUID DELIVERY IN A MULTI-STATION SEMICONDUCTOR PROCESSING CHAMBER

      
Application Number 18557043
Status Pending
Filing Date 2022-04-28
First Publication Date 2024-07-04
Owner Lam Research Corporation (USA)
Inventor
  • Jeon, Eli
  • Roberts, Michael Philip
  • Agnew, Douglas Walter
  • Boatright, Daniel
  • Anandhan Duraisamy, Arun
  • Abel, Joseph R.
  • Mcdaniel, William Laurence

Abstract

The present disclosure relates to a system for a semiconductor processing. The system includes a semiconductor processing chamber having a plurality of processing stations, a plurality of manifold trunks, a plurality of valves, and a plurality of fluid manifolds. Each manifold trunk includes an outlet, a common flowpath, a plurality of trunk inlets, a plurality of orifices, and a plurality of valve interfaces.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

13.

FILL ON DEMAND AMPOULE REFILL

      
Application Number 18602760
Status Pending
Filing Date 2024-03-12
First Publication Date 2024-07-04
Owner Lam Research Corporation (USA)
Inventor
  • Nguyen, Tuan
  • Ranganathan, Eashwar
  • Swaminathan, Shankar
  • Lavoie, Adrien
  • Baldasseroni, Chloe
  • Chandrasekharan, Ramesh
  • Pasquale, Frank Loren
  • Petraglia, Jennifer Leigh

Abstract

Methods and apparatus for use of a fill on demand ampoule are disclosed. The fill on demand ampoule may refill an ampoule with precursor concurrent with the performance of other deposition processes. The fill on demand may keep the level of precursor within the ampoule at a relatively constant level. The level may be calculated to result in an optimum head volume. Methods and apparatus for use of a fill on demand ampoule are disclosed. The fill on demand ampoule may refill an ampoule with precursor concurrent with the performance of other deposition processes. The fill on demand may keep the level of precursor within the ampoule at a relatively constant level. The level may be calculated to result in an optimum head volume. The fill on demand may also keep the precursor at a temperature near that of an optimum precursor temperature. The fill on demand may occur during parts of the deposition process where the agitation of the precursor due to the filling of the ampoule with the precursor minimally effects the substrate deposition. Substrate throughput may be increased through the use of fill on demand.

IPC Classes  ?

  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials

14.

WAFER STATE DETECTION

      
Application Number 18558327
Status Pending
Filing Date 2022-04-29
First Publication Date 2024-07-04
Owner Lam Research Corporation (USA)
Inventor Baker, Noah Elliot

Abstract

Various embodiments herein relate to apparatuses and methods for wafer state detection. In some embodiments, an apparatus for wafer state detection is provided, the apparatus comprising: an RF blocking filter; a DC blocking filter; and a controller coupled to a plurality of electrodes associated with an electrostatic chuck (ESC) via the RF blocking filter and the DC blocking filter, wherein the controller is configured to: cause an input signal to be injected in an input side of a circuit associated with the plurality of electrodes, the RF blocking filter, and the DC blocking filter, wherein the input side corresponds to a first electrode; measure characteristics of an output signal at an output side of the circuit, wherein the output side corresponds to a second electrode; and calculate wafer state characteristics of a wafer positioned on a surface of a platen based on the characteristics of the output signal.

IPC Classes  ?

  • G01B 7/28 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring contours or curvatures
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

15.

MINIMIZING RADICAL RECOMBINATION USING ALD SILICON OXIDE SURFACE COATING WITH INTERMITTENT RESTORATION PLASMA

      
Application Number 18427691
Status Pending
Filing Date 2024-01-30
First Publication Date 2024-07-04
Owner Lam Research Corporation (USA)
Inventor
  • Varadarajan, Bhadri N.
  • Gong, Bo
  • Batzer, Rachel E.
  • Qiu, Huatan
  • Van Schravendijk, Bart J.
  • Hohn, Geoffrey

Abstract

Certain embodiments herein relate to an apparatus used for remote plasma processing. In various embodiments, the apparatus includes a reaction chamber that is conditioned by forming a low recombination material coating on interior chamber surfaces. The low recombination material helps minimize the degree of radical recombination that occurs when the reaction chamber is used to process substrates. During processing on substrates, the low recombination material may become covered by relatively higher recombination material (e.g., as a byproduct of the substrate processing), which results in a decrease in the amount of radicals available to process the substrate over time. The low recombination material coating may be reconditioned through exposure to an oxidizing plasma, which acts to reform the low recombination material coating. The reconditioning process may occur periodically as additional processing occurs on substrates. The apparatus may be configured to cause formation and reconditioning of the low recombination material coating.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/40 - Oxides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/452 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials by activating reactive gas streams before introduction into the reaction chamber, e.g. by ionization or by addition of reactive species
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • H01J 37/32 - Gas-filled discharge tubes

16.

IN-SITU WAFER THICKNESS AND GAP MONITORING USING THROUGH BEAM LASER SENSOR

      
Application Number 17913902
Status Pending
Filing Date 2021-03-24
First Publication Date 2024-06-27
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Wong, Goon Heng
  • Hua, Xuefeng
  • Van Selow, Anthony Paul
  • Torres, Daniel
  • Chen, Jack

Abstract

A system for determining a thickness of a substrate arranged in a processing chamber includes an emitter configured to transmit a signal toward a gap between the substrate and a component of the processing chamber arranged above the substrate, a receiver configured to receive at least a portion of the transmitted signal and generate a measurement signal based on a characteristic of the received portion of the signal, and a system controller configured to receive the measurement signal and selectively adjust a parameter of the processing chamber based on a relationship between values of the measurement signal and at least one of the thickness of the substrate, a width of the gap between the substrate and the component of the processing chamber, and an amount to adjust the parameter of the processing chamber.

IPC Classes  ?

  • G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
  • C23C 14/54 - Controlling or regulating the coating process
  • C23C 16/52 - Controlling or regulating the coating process
  • G01B 11/14 - Measuring arrangements characterised by the use of optical techniques for measuring distance or clearance between spaced objects or spaced apertures

17.

INTEGRATED ATMOSPHERIC PLASMA TREATMENT STATION IN PROCESSING TOOL

      
Application Number 18556978
Status Pending
Filing Date 2022-04-20
First Publication Date 2024-06-27
Owner Lam Research Corporation (USA)
Inventor
  • Subbaiyan, Navaneetha Krishnan
  • Little, Patrick
  • Dinneen, Daniel Mark
  • Ghongadi, Shantinath

Abstract

An atmospheric plasma treatment station is integrated in a semiconductor process tool. The atmospheric plasma treatment station directly interfaces with a deposition chamber of the semiconductor process tool without adding to the footprint or form factor of the semiconductor process tool. The atmospheric plasma treatment station includes a movable atmospheric plasma source such as a linear head for scanning across a surface of a substrate. The atmospheric plasma treatment station provides an enclosed space in a controlled environment with non-reactive gas flowing through the enclosed space. Process gases may be supplied to the linear head based on a surface condition of the substrate being treated.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

18.

ROTATIONAL INDEXERS WITH WAFER CENTERING CAPABILITY

      
Application Number 18556910
Status Pending
Filing Date 2022-04-22
First Publication Date 2024-06-27
Owner Lam Research Corporation (USA)
Inventor
  • Ratliff, Brian Lewis
  • Blank, Richard M.
  • Topping, Stephen
  • Leeser, Karl Frederick

Abstract

Rotational indexers are provided that allow for wafer-by-wafer centering to be performed in association with each wafer pedestal-to-pedestal transfer operation within a multi-station chamber. One such rotational indexer has a rotational center axis that is movable along one or more lateral directions in order to provide wafer centering capability; sealing arrangements with lateral movement capability are provided for such implementations. Another such rotational indexer uses additional rotational capability at the wafer supports of the indexer, in combination with deliberate off-center placement of the wafers on the wafer supports of the indexer, to provide wafer centering capability.

IPC Classes  ?

  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • G05B 19/4099 - Surface or curve machining, making 3D objects, e.g. desktop manufacturing
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

19.

APPARATUSES FOR MEASURING GAP BETWEEN A SUBSTRATE SUPPORT PLANE AND GAS DISTRIBUTION DEVICE

      
Application Number 18557250
Status Pending
Filing Date 2022-04-21
First Publication Date 2024-06-27
Owner Lam Research Corporation (USA)
Inventor
  • Vintila, Adriana
  • Bapat, Shriram Vasant
  • Alden, Emily Ann
  • Slevin, Damien Martin

Abstract

Some embodiments provide apparatuses capable of enabling the measurement of various characteristics of a showerhead-substrate gap in a processing chamber, including at high temperatures and at low-light conditions, using an imaging system external to the processing chamber.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

20.

YTTRIUM ALUMINUM PEROVSKITE (YAP) BASED COATINGS FOR SEMICONDUCTOR PROCESSING CHAMBER COMPONENTS

      
Application Number 18577115
Status Pending
Filing Date 2022-08-02
First Publication Date 2024-06-27
Owner Lam Research Corporation (USA)
Inventor
  • Pape, Eric A.
  • Wetzel, David Joseph
  • Xu, Lin
  • Srinivasan, Satish
  • Koshy, Robin
  • Detert, Douglas
  • Dederick, Jeremiah Michael

Abstract

A component for use in a semiconductor processing chamber is provided. A component body comprises a metallic material or ceramic material. A coating is disposed on a surface of the component body where the coating comprises a layer of yttrium aluminum oxide, the yttrium aluminum oxide layer being formed of a composition having a molar ratio of 1.0-0.9 yttrium to 1.0-1.1 aluminum over at least 90% of the yttrium aluminum oxide layer.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • B05D 1/02 - Processes for applying liquids or other fluent materials performed by spraying
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

21.

GRAPHENE-CAPPED COPPER IN DUAL DAMASCENE INTERCONNECT

      
Application Number 18291200
Status Pending
Filing Date 2022-07-19
First Publication Date 2024-06-27
Owner Lam Research Corporation (USA)
Inventor
  • Parbatani, Asish
  • Van Schravendijk, Bart J.
  • Varadarajan, Bhadri N.
  • Narkeviciute, Ieva
  • Srinivasan, Easwar
  • Sharma, Kashish
  • Knarr, Randolph
  • Schmitz, Stefan
  • Ramanan, Vinayak

Abstract

A method for selectively depositing graphene on a metal surface in a back-end-of-line substrate is provided. The method comprises providing the substrate comprising a first dielectric layer and a copper interconnect in the first dielectric layer, the copper interconnect having an exposed metal surface, wherein the exposed metal surface comprises copper, and selectively deposing a carbon layer on the exposed metal surface.

IPC Classes  ?

  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/26 - Deposition of carbon only
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

22.

SUBSTRATE SUPPORTS WITH MESOCHANNEL ASSEMBLIES

      
Application Number 18291444
Status Pending
Filing Date 2022-07-19
First Publication Date 2024-06-27
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Subramanya, Spoorthi
  • Revanna, Shivakumara
  • Flynn, Kevin
  • Gandur Balagangadhara, Chandrashekara Kuashik
  • Jain, Muskaan
  • Krishna Murthy, Santosh Kumar

Abstract

A substrate support includes a body and a mesochannel assembly. The body is configured to support a substrate within a substrate processing system. The first mesochannel assembly is disposed in the body and includes: a first mesochannels; a first supply manifold supplying coolant to each of the first mesochannels; and a first return manifold receiving the coolant from the first mesochannels. The first mesochannels are disposed between the first supply manifold and the first return manifold to facilitate flow of the coolant from the first supply manifold to the first return manifold.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes

23.

RF SIGNAL PARAMETER MEASUREMENT IN AN INTEGRATED CIRCUIT FABRICATION CHAMBER

      
Application Number 17907067
Status Pending
Filing Date 2021-03-24
First Publication Date 2024-06-20
Owner Lam Research Corporation (USA)
Inventor
  • Kapoor, Sunil
  • French, David
  • Lemson, Gary
  • Meng, Liang

Abstract

An apparatus to estimate parameters of a radio frequency (RF) signal may include a voltage sensor configured to provide an indication of a voltage of the RF signal as well as a current sensor configured to provide an indication of current conducted by the RF signal. The apparatus may additionally include an analog-to-digital converter coupled to an output port of the voltage sensor and the current sensor, wherein the analog-to-digital converter is configured to provide digital representations of an instantaneous voltage and an instantaneous current of the RF signal. The apparatus may additionally include one or more processors configured to transform the digital representations of the instantaneous voltage and current into frequency domain representations of a complex voltage and complex current.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • G01R 15/16 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using capacitive devices
  • G01R 15/18 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using inductive devices, e.g. transformers
  • G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
  • G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
  • G01R 25/00 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
  • G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

24.

SHADOW RING ALIGNMENT FOR SUBSTRATE SUPPORT

      
Application Number 18287131
Status Pending
Filing Date 2022-04-15
First Publication Date 2024-06-20
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Gulabal, Vinayakaraddy
  • Vellanki, Ravi
  • Lind, Gary B.
  • Eib, Andrew Paul

Abstract

A system to align a shadow ring on a substrate support includes a baseplate of the substrate support, an alignment recess defined within an upper surface of the baseplate, a shadow ring, an upper alignment groove defined in a lower surface of the shadow ring, an alignment block disposed within the alignment recess, and an alignment feature disposed between the shadow ring and the alignment block. The alignment feature extends into the upper alignment groove defined in the lower surface of the shadow ring.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

25.

USE OF SIGNAL FILTERING SCHEMES IN HIGH TCR BASED CONTROL

      
Application Number 18288144
Status Pending
Filing Date 2022-04-25
First Publication Date 2024-06-20
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Chandrasekharan, Ramesh
  • Thilagaraj, Mohan
  • Leeser, Karl Frederick

Abstract

A controller to control a temperature of a first substrate support in a substrate processing system includes a resistance calculation module to calculate a first resistance of a first heater element of a plurality of heater elements of the first substrate support, a temperature calculation module to calculate a first temperature of the first heater element based on the calculated first resistance, and a filter module to filter a first signal that corresponds to the calculated first resistance. The temperature calculation module selectively causes the filter module to filter the first signal in response to a determination of whether at least one condition associated with operation of the substrate processing system is met.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate

26.

CONTROL OF DISSOLVED GAS CONCENTRATION IN ELECTROPLATING BATHS

      
Application Number 18554622
Status Pending
Filing Date 2022-04-14
First Publication Date 2024-06-20
Owner Lam Research Corporation (USA)
Inventor
  • Kearns, Gregory J.
  • Blickensderfer, Jacob Kurtis
  • Venkatraman, Kailash
  • Wilmot, Frederick Dean
  • Chua, Lee Peng
  • Rash, Robert

Abstract

A concentration of a dissolved gas can be controlled by following an electroplating solution through a contactor, controlling a pressure within the contactor, and thereby maintaining the concentration of the dissolved gas in the electroplating solution within a first concentration range. The first concentration range is non-zero and sub-saturation.

IPC Classes  ?

  • C25D 21/04 - Removal of gases or vapours
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 21/12 - Process control or regulation
  • C25D 21/18 - Regeneration of process solutions of electrolytes

27.

PLASMA ETCHING CHEMISTRIES OF HIGH ASPECT RATIO FEATURES IN DIELECTRICS

      
Application Number 18592994
Status Pending
Filing Date 2024-03-01
First Publication Date 2024-06-20
Owner Lam Research Corporation (USA)
Inventor
  • Kanarik, Keren J.
  • Tan, Samantha Siamhwa
  • Pan, Yang
  • Marks, Jeffrey

Abstract

A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below −20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

28.

PLASMA ETCHING CHEMISTRIES OF HIGH ASPECT RATIO FEATURES IN DIELECTRICS

      
Application Number 18593113
Status Pending
Filing Date 2024-03-01
First Publication Date 2024-06-20
Owner Lam Research Corporation (USA)
Inventor
  • Kanarik, Keren J.
  • Tan, Samantha Siamhwa
  • Pan, Yang
  • Marks, Jeffrey

Abstract

A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below −20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

29.

BACKSIDE DEPOSITION PREVENTION ON SUBSTRATES

      
Application Number 18287372
Status Pending
Filing Date 2022-04-15
First Publication Date 2024-06-20
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Gage, Christopher
  • Chandrasekharan, Ramesh
  • Lenz, Eric H.
  • Leeser, Karl Frederick

Abstract

Various systems and methods are provided to prevent backside deposition on a substrate by using a combination of approaches. The approaches include clamping the substrate to a pedestal and/or supplying purge gases to an area where deposition is not desired. The clamping methods include electrostatic or vacuum clamping. In addition, various pedestal and edge ring designs are provided for supplying purge gases to the area where deposition is not desired. The use of clamping in conjunction with purging can further enhance the performance without affecting deposition of materials on front side of the substrate. The clamping along the edge of the substrate can be made more effective by machining an upper surface of the pedestal to have a slight dish or dome like shape (i.e., concave or convex, respectively).

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

30.

APPARATUS AND PROCESS FOR EUV DRY RESIST SENSITIZATION BY GAS PHASE INFUSION OF A SENSITIZER

      
Application Number 17905754
Status Pending
Filing Date 2021-03-24
First Publication Date 2024-06-13
Owner Lam Research Corporation (USA)
Inventor
  • Kanakasabapathy, Sivananda Krishnan
  • Tan, Samantha S.H.
  • Yu, Jengyi
  • Lee, Younghee
  • Jensen, Alan J.
  • Li, Da

Abstract

The present disclosure relates to stacks having a sensitized resist film, as well as methods and apparatuses for applying such sensitized films. In particular embodiments, the sensitizer can be provided in gas form, and unreacted sensitizer precursors can be recovered after a deposition step.

IPC Classes  ?

  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/20 - Exposure; Apparatus therefor
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

31.

DUAL ZONE HEATERS FOR METALLIC PEDESTALS

      
Application Number 18443906
Status Pending
Filing Date 2024-02-16
First Publication Date 2024-06-13
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sundaram, Sairam
  • Durbin, Aaron
  • Chandrasekharan, Ramesh

Abstract

A temperature-controlled substrate support for a substrate processing system includes a substrate support and a controller. The substrate support includes N zones and N resistive heaters, respectively, where N is an integer greater than one, and a temperature sensor located in one of the N zones. The controller is configured to calculate N resistances of the N resistive heaters during operation and adjust power to N-1 of the N resistive heaters during operation of the substrate processing system in response to a temperature measured by the temperature sensor located in the one of the N zones and the N resistances of the N resistive heaters.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

32.

CONTROL OF SEMICONDUCTOR MANUFACTURING EQUIPMENT IN MIXED REALITY ENVIRONMENTS

      
Application Number 18554823
Status Pending
Filing Date 2022-04-11
First Publication Date 2024-06-13
Owner Lam Research Corporation (USA)
Inventor
  • Unterguggenberger, Rainer
  • Thorgrimsson, Christopher
  • Chan, Henry T.
  • Huang, Chung-Ho
  • Bernier, Terrence George

Abstract

Various embodiments herein relate to a Mixed Reality (MR) control platform to operate a semiconductor manufacturing tool in an MR environment and to display data associated with the semiconductor manufacturing tool. In son embodiments, the MR control platform comprises an MR control system and an MR headset. The MR control system can obtain sensor data representative of sensor output from a semiconductor manufacturing tool. The MR control system can determine operational information associated with the semiconductor manufacturing tool and based on the sensor data. The MR control system can cause the operational information to be transmitted to the MR headset. The MR headset can receive the operational information associated with the semiconductor manufacturing tool from the MR control system. The MR headset can cause content associated with the operational information and one or more control features to be rendered in an MR environment.

IPC Classes  ?

  • G05B 19/042 - Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06T 15/20 - Perspective computation
  • G06T 17/00 - 3D modelling for computer graphics
  • G06T 19/00 - Manipulating 3D models or images for computer graphics
  • G06V 20/20 - Scenes; Scene-specific elements in augmented reality scenes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

33.

MINIMIZING TIN OXIDE CHAMBER CLEAN TIME

      
Application Number 18556075
Status Pending
Filing Date 2022-04-20
First Publication Date 2024-06-13
Owner Lam Research Corporation (USA)
Inventor
  • Chang, Ching-Yun
  • Ha, Jeongseok
  • Liu, Pei-Chi

Abstract

Techniques described herein relate to methods and apparatus for minimizing tin oxide chamber clean time. In many cases, the chamber is a deposition chamber used for depositing tin oxide on semiconductor substrates. The techniques involve exposing the chamber surface to a first plasma generated from a first plasma generation gas including reducing chemistry to reduce the tin oxide to tin, and then exposing the chamber surface to a second plasma generated from a second plasma generation gas including reducing chemistry and organic additive chemistry to remove the tin from the chamber surface. In some cases, the first plasma used to reduce the tin oxide to tin further includes inert gas.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/52 - Controlling or regulating the coating process

34.

METHOD AND APPARATUS FOR MODULATING FILM UNIFORMITY

      
Application Number 18442427
Status Pending
Filing Date 2024-02-15
First Publication Date 2024-06-06
Owner Lam Research Corporation (USA)
Inventor
  • Agarwal, Pulkit
  • Lavoie, Adrien
  • Kumar, Purushottam

Abstract

A method for processing a substrate is provided, wherein the substrate is located below a showerhead in a processing chamber. A deposition layer is deposited on the substrate, wherein at least one deposition gas is provided through the showerhead. A secondary purge gas is flowed during the depositing the deposition layer from a location outside of the showerhead in the processing chamber forming a flow curtain around an outer edge of the showerhead, wherein the secondary purge gas comprises at least one component gas. A partial pressure of the at least one component gas is changed over time during the depositing the deposition layer, wherein the depositing the deposition layer has a non-uniformity, wherein the changing the partial pressure changes the non-uniformity over time during the depositing the deposition layer.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

35.

SYSTEMS AND METHODS FOR OPTIMIZING POWER DELIVERY TO AN ELECTRODE OF A PLASMA CHAMBER

      
Application Number 18415492
Status Pending
Filing Date 2024-01-17
First Publication Date 2024-06-06
Owner Lam Research Corporation (USA)
Inventor
  • Bhowmick, Ranadeep
  • Holland, John
  • Kozakevich, Felix Leib
  • Ji, Bing
  • Marakhtanov, Alexei

Abstract

A method for optimizing delivery of power to a plasma chamber is described. The method includes dividing each cycle of a low frequency (LF) radio frequency generator (RFG) into multiple time intervals. During each of the time intervals, a frequency offset of a high frequency (HF) RFG is generated for which the delivery of power is maximized. The frequency offsets provide a substantially inverse relationship compared to a voltage signal of the LF RFG for each cycle of the voltage signal. The frequency offsets for the time intervals are multiples of the low frequency. The substantially inverse relationship facilitates an increase in the delivery of power to the electrode. A total range of the frequency offsets from a reference HF frequency over the LF RF cycle depends on a power ratio of power that is supplied by the LF RFG and power that is supplied by the HF RFG.

IPC Classes  ?

36.

ATOMIC LAYER ETCHING FOR SUBTRACTIVE METAL ETCH

      
Application Number 18435244
Status Pending
Filing Date 2024-02-07
First Publication Date 2024-06-06
Owner Lam Research Corporation (USA)
Inventor
  • Yang, Wenbing
  • Brouri, Mohand
  • Tan, Samantha Siamhwa
  • Lee, Shih-Ked
  • Fan, Yiwen
  • Choi, Wook
  • Mukherjee, Tamal
  • Lin, Ran
  • Pan, Yang

Abstract

A method for atomic layer etching a metal containing layer is provided. At least a region of a surface of the metal containing layer is modified to form a modified metal containing region by exposing a surface of the metal containing layer to a modification gas, wherein adjacent to the modified metal containing region remains an unmodified metal containing region. The modified metal containing region is selectively removed with respect to the unmodified metal containing region by exposing the surface of the metal containing layer to an inert bombardment plasma generated from an inert gas.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

37.

SYSTEMS AND METHODS FOR TUNING A MHZ RF GENERATOR WITHIN A CYCLE OF OPERATION OF A KHZ RF GENERATOR

      
Application Number 18440583
Status Pending
Filing Date 2024-02-13
First Publication Date 2024-06-06
Owner Lam Research Corporation (USA)
Inventor
  • Howald, Arthur M.
  • Valcore, Jr., John C.

Abstract

Systems and methods for tuning a megahertz radio frequency (RF) generator within a cycle of operation of a kilohertz (kHz) RF generator are described. In one of the methods, a predetermined periodic waveform is provided to a processor. The processor uses a computer-based model to determine plurality of frequency parameters for the predetermined periodic waveform. The frequency parameters are applied to the megahertz RF generator to generate an RF signal having the frequency parameters during one or more cycles of operation of the kilohertz RF generator.

IPC Classes  ?

38.

CONDUCTIVE COOLING OF A LOW TEMPERATURE PEDESTAL OPERATING IN A HIGH TEMPERATURE DEPOSITION SEQUENCE

      
Application Number 18282021
Status Pending
Filing Date 2022-03-21
First Publication Date 2024-05-30
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lind, Gary B.
  • Vellanki, Ravi
  • Clevenger, Jeff
  • Gulabal, Vinayakarddy

Abstract

A pedestal comprises a base portion, a stem portion, and a heater arranged in the base portion. The stem portion has a first end attached to a center region of the base portion. The heater includes a first loop arranged in the center region of the base portion. A first perimeter of the first loop is less than or equal to a second perimeter of the first end of the stem portion.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate

39.

PLASMA ETCHING CHEMISTRIES OF HIGH ASPECT RATIO FEATURES IN DIELECTRICS

      
Application Number 18431669
Status Pending
Filing Date 2024-02-02
First Publication Date 2024-05-30
Owner Lam Research Corporation (USA)
Inventor
  • Kanarik, Keren J.
  • Tan, Samantha Siamhwa
  • Pan, Yang
  • Marks, Jeffrey

Abstract

A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below −20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

40.

IN-SITU FILM ANNEALING IN SUBSTRATE PROCESSING

      
Application Number 18283796
Status Pending
Filing Date 2022-03-25
First Publication Date 2024-05-23
Owner Lam Research Corporation (USA)
Inventor
  • Gupta, Awnish
  • Agnew, Douglas Walter
  • Van Schravendijk, Bart Jan
  • Abel, Joseph R.
  • Pasquale, Frank L.
  • Lavoie, Adrien

Abstract

In one example, a method for depositing a film on a substrate comprises arranging a substrate on a substrate support in a processing chamber and setting a processing pressure, temperature and pressure in the chamber. The method includes striking a plasma and depositing and annealing the film on the substrate at a thickness in a predetermined film thickness range.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment

41.

LINE BENDING CONTROL FOR MEMORY APPLICATIONS

      
Application Number 18394479
Status Pending
Filing Date 2023-12-22
First Publication Date 2024-05-23
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Butail, Gorun
  • Thombare, Shruti
  • Karim, Ishtak
  • Van Cleemput, Patrick

Abstract

A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the predetermined range.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

42.

SEMICONDUCTOR TOOL ARRANGEMENTS

      
Application Number 18283797
Status Pending
Filing Date 2022-04-27
First Publication Date 2024-05-23
Owner Lam Research Corporation (USA)
Inventor Leeser, Karl Frederick

Abstract

Various examples include arrangements of semiconductor-processing tools. In one example, a semiconductor-processing tool includes multiple multi-station modules, each having multiple processing stations. At least some of the processing stations are organized in a diamond-shaped arrangement. A vacuum-transfer module is coupled to each of the multi-station modules. The vacuum-transfer module has one or more vacuum-transfer robots to transfer substrates to and from at least one of the multiple processing stations. At least one additional processing-station is located in the vacuum-transfer module. Other systems and apparatuses are disclosed.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

43.

SPATIALLY TUNABLE DEPOSITION TO COMPENSATE WITHIN WAFER DIFFERENTIAL BOW

      
Application Number 18427348
Status Pending
Filing Date 2024-01-30
First Publication Date 2024-05-23
Owner Lam Research Corporation (USA)
Inventor
  • Shaikh, Fayaz A.
  • Vintila, Adriana
  • Mudrow, Matthew
  • Linebarger, Jr., Nick Ray
  • Yin, Xin
  • Lee, James F.
  • Williams, Brian Joseph

Abstract

A plasma processing chamber for depositing a film on an underside surface of a wafer, includes a showerhead pedestal. The showerhead pedestal includes a first zone and a second zone. The first zone is configured for depositing a first film to the underside surface of the wafer and the second zone is configured for depositing a second film to the underside surface of the wafer.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes

44.

MECHANICAL SUPPRESSION OF PARASITIC PLASMA IN SUBSTRATE PROCESSING CHAMBER

      
Application Number 18392822
Status Pending
Filing Date 2023-12-21
First Publication Date 2024-05-16
Owner Lam Research Corporation (USA)
Inventor
  • Keil, Douglas
  • Augustyniak, Edward J.
  • Leeser, Karl Frederick
  • Sabri, Mohamed

Abstract

A system includes an electrode. The electrode includes a showerhead having a first stem portion and a head portion. A plurality of dielectric layers is vertically stacked between the electrode and a first surface of a conducting structure. The plurality of dielectric layers includes M dielectric layers arranged adjacent to the head portion and P dielectric portions arranged around the first stem portion. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap, and the third gap are selected to prevent parasitic plasma between the first surface and the electrode.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

45.

RING STRUCTURES AND SYSTEMS FOR USE IN A PLASMA CHAMBER

      
Application Number 18405997
Status Pending
Filing Date 2024-01-05
First Publication Date 2024-05-16
Owner Lam Research Corporation (USA)
Inventor
  • Kellogg, Michael C.
  • Mace, Adam
  • Marakhtanov, Alexei
  • Holland, John
  • Chen, Zhigang
  • Kozakevich, Felix
  • Matyushkin, Alexander

Abstract

Systems and methods for securing an edge ring to a support ring are described. The edge ring is secured to the support ring via multiple fasteners that are inserted into a bottom surface of the edge ring. The securing of the edge ring to the support ring provides stability of the edge ring during processing of a substrate within a plasma chamber. In addition, the securing of the edge ring to the support ring secures the edge ring to the plasma chamber because the support ring is secured to an insulator ring, which is connected to an insulator wall of the plasma chamber. Moreover, the support ring and the edge ring are pulled down vertically using one or more clasp mechanisms during the processing of the substrate and are pushed up vertically using the clasp mechanisms to remove the edge ring and the support ring from the plasma chamber.

IPC Classes  ?

46.

SYSTEMS AND METHODS FOR ACHIEVING PEAK ION ENERGY ENHANCEMENT WITH A LOW ANGULAR SPREAD

      
Application Number 18420737
Status Pending
Filing Date 2024-01-23
First Publication Date 2024-05-16
Owner Lam Research Corporation (USA)
Inventor
  • Shoeb, Juline
  • Wu, Ying
  • Paterson, Alex

Abstract

Systems and methods for increasing peak ion energy with a low angular spread of ions are described. In one of the systems, multiple radio frequency (RF) generators that are coupled to an upper electrode associated with a plasma chamber are operated in two different states, such as two different frequency levels, for pulsing of the RF generators. The pulsing of the RF generators facilitates a transfer of ion energy during one of the states to another one of the states for increasing ion energy during the other state to further increase a rate of processing a substrate.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

47.

REDUCING LINE BENDING DURING METAL FILL PROCESS

      
Application Number 18550190
Status Pending
Filing Date 2022-03-07
First Publication Date 2024-05-16
Owner Lam Research Corporation (USA)
Inventor
  • Chandrashekar, Anand
  • Guo, Lei
  • Liu, Gang L.
  • Gopinath, Sanjay

Abstract

Methods of mitigating line bending during feature fill include deposition of a nucleation layer having increased roughness. In some embodiments, the methods include depositing two or more metal nucleation layers.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material

48.

ADJUSTABLE DIELECTRIC CONSTANT CERAMIC WINDOW

      
Application Number 18550664
Status Pending
Filing Date 2022-03-15
First Publication Date 2024-05-16
Owner Lam Research Corporation (USA)
Inventor
  • Liu, Chin-Yi
  • Marohl, Dan

Abstract

A dielectric window for a process chamber is provided. The dielectric window includes a disc-shaped body consisting of a first dielectric material having a first dielectric constant. An annular portion consisting of a second dielectric material having a second dielectric constant greater than the first dielectric constant is seated in the disc-shaped body. The dielectric window has a substantially constant thickness over a process region of the process chamber. The process region is an interior region of the process chamber in which a plasma is generated during processing of a substrate in the process chamber. The seating of the annular portion in the disc-shaped body is configured to maintain the substantially constant thickness of the dielectric window.

IPC Classes  ?

49.

INTEGRATED DRY PROCESSES FOR PATTERNING RADIATION PHOTORESIST PATTERNING

      
Application Number 18377267
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-05-02
Owner Lam Research Corporation (USA)
Inventor
  • Yu, Jengyi
  • Tan, Samantha S.H.
  • Alvi, Mohammed Haroon
  • Wise, Richard
  • Pan, Yang
  • Gottscho, Richard Alan
  • Lavoie, Adrien
  • Kanakasabapathy, Sivananda Krishnan
  • Weidman, Timothy William
  • Lin, Qinghuang
  • Hubacek, Jerome S.

Abstract

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
  • G03F 7/38 - Treatment before imagewise removal, e.g. prebaking

50.

CONTROLLING PLATING ELECTROLYTE CONCENTRATION ON AN ELECTROCHEMICAL PLATING APPARATUS

      
Application Number 18502409
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-05-02
Owner Lam Research Corporation (USA)
Inventor
  • He, Zhian
  • Ghongadi, Shantinath
  • Ma, Quan
  • Hur, Hyungjun
  • Sweeney, Cian
  • Nguyen, Quang
  • Karim, Rezaul
  • Feng, Jingbin

Abstract

Methods and electroplating systems for controlling plating electrolyte concentration on an electrochemical plating apparatus for substrates are disclosed. A method involves: (a) providing an electroplating solution to an electroplating system; (b) electroplating the metal onto the substrate while the substrate is held in a cathode chamber of an electroplating cell of electroplating system; (c) supplying the make-up solution to the electroplating system via a make-up solution inlet; and (d) supplying the secondary electroplating solution to the electroplating system via a secondary electroplating solution inlet. The secondary electroplating solution includes some or all components of the electroplating solution. At least one component of the secondary electroplating solution has a concentration that significantly deviates from its target concentration.

IPC Classes  ?

  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 3/38 - Electroplating; Baths therefor from solutions of copper
  • C25D 17/10 - Electrodes
  • C25D 21/14 - Controlled addition of electrolyte components
  • C25D 21/18 - Regeneration of process solutions of electrolytes
  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition

51.

ELECTRODEPOSITION OF METALS USING AN IONICALLY RESISTIVE IONICALLY PERMEABLE ELEMENT OR A SHIELD SPATIALLY TAILORED TO DIE-LEVEL PATTERNS ON A SUBSTRATE

      
Application Number 18549426
Status Pending
Filing Date 2022-03-15
First Publication Date 2024-05-02
Owner Lam Research Corporation (USA)
Inventor
  • Chua, Lee Peng
  • Graham, Gabriel Hay
  • Buckalew, Bryan L.
  • Banik, Ii, Stephen J.
  • Kumar, Santosh
  • Fortner, James Isaac
  • Rash, Robert
  • Mayer, Steven T.

Abstract

An apparatus for electroplating a metal on a semiconductor substrate with high control over plated thickness on a die-level includes an ionically resistive ionically permeable element (e.g., a plate with channels), where the element allows for flow of ionic current through the element towards the substrate during electroplating, where the element includes a plurality of regions, each region having a pattern of varied local resistance, and where the pattern of varied local resistance repeats in at least two regions. An electroplating method includes providing a semiconductor substrate to an electroplating apparatus having an ionically resistive ionically permeable element or a grid-like shield having a pattern correlating with a pattern of features on the substrate, and plating metal, while the pattern on the substrate remains spatially aligned with the pattern of the element or the grid-like shield for at least a portion of the total electroplating time.

IPC Classes  ?

  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 5/02 - Electroplating of selected surface areas
  • C25D 5/08 - Electroplating with moving electrolyte, e.g. jet electroplating
  • C25D 5/54 - Electroplating of non-metallic surfaces
  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition

52.

NOZZLE FOR REMOTE PLASMA CLEANING OF PROCESS CHAMBERS

      
Application Number 18550940
Status Pending
Filing Date 2022-03-17
First Publication Date 2024-05-02
Owner Lam Research Corporation (USA)
Inventor Pool, Jeremy Jerome

Abstract

Nozzles for providing gas into a semiconductor wafer process chamber are disclosed. The nozzles may include a deflector structure that has a surface facing the nozzle outlet so as to redirect gas as it enters a chamber. The nozzles may also have a cooling system to remove heat provided to the deflector structure through the flow of plasma through the nozzle. The deflector structure may be used to distribute the plasma flowed therethrough in a more evenly distributed manner, thereby protecting hardware within the process chamber from potential hotspots. This has the further effect of redirecting gases more efficiently throughout the chamber.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

53.

LONG-LIFE EXTENDED TEMPERATURE RANGE EMBEDDED DIODE DESIGN FOR ELECTROSTATIC CHUCK WITH MULTIPLEXED HEATERS ARRAY

      
Application Number 18405595
Status Pending
Filing Date 2024-01-05
First Publication Date 2024-04-25
Owner LAM RESEARCH CORPORATION (USA)
Inventor Tian, Siyuan

Abstract

A substrate support for a plasma chamber includes a base plate arranged along a plane, a first layer of an electrically insulating material arranged on the base plate along the plane, a plurality of heating elements arranged in the first layer along the plane, and a plurality of diodes arranged in respective cavities in the first layer. The plurality of diodes are connected in series to the plurality of heating elements, respectively. Each of the plurality of diodes includes a die of a semiconductor material arranged in a respective one of the cavities. The semiconductor material has a first coefficient of thermal expansion. A first side of the die is arranged on the first layer along the plane. A first terminal of the die is connected to a first electrical contact on the first layer.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

54.

MONOLITHIC ANISOTROPIC SUBSTRATE SUPPORTS

      
Application Number 17769430
Status Pending
Filing Date 2020-10-20
First Publication Date 2024-04-18
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Hollingsworth, Joel
  • Lingampalli, Ramkishan
  • Leeser, Karl
  • Topping, Stephen
  • Baker, Noah Elliot

Abstract

A substrate support includes a monolithic anisotropic body, which includes first, second and intermediate layers. The first layer is formed of a first material and disposed therein are RF and clamping electrodes. The second layer is formed of the first material or a second material and disposed therein is a heating element. The intermediate layer is formed of a different material than the first and second layers, such that at least one of: a thermal energy conductivity of the intermediate layer is different than a thermal energy conductivity of at least one of the first or second materials; or an electrical energy conductivity of the intermediate layer is different than an electrical conductivity of at least one of the first or second materials. Either the intermediate layer is disposed between the first and second layers or the second layer is disposed between the first and intermediate layers.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

55.

POLYMERIC COATING FOR SEMICONDUCTOR PROCESSING CHAMBER COMPONENTS

      
Application Number 18546174
Status Pending
Filing Date 2022-02-25
First Publication Date 2024-04-11
Owner Lam Research Corporation (USA)
Inventor
  • Song, Yuanping
  • Pham, Johnny
  • Song, Yiwei
  • Xu, Lin
  • Kimball, Christopher

Abstract

A component in a semiconductor processing chamber is provided. An electrically conductive semiconductor or metal body has a CTE of less than 10.0×10−6/K. An intermediate layer is disposed over at least one surface of the body, the intermediate layer comprising a fluoropolymer. A perfluoroalkoxy alkane (PFA) layer is disposed over the intermediate layer to form the component.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • B05D 1/02 - Processes for applying liquids or other fluent materials performed by spraying

56.

Multiple State Pulsing for High Aspect Ratio Etch

      
Application Number 18011505
Status Pending
Filing Date 2022-06-16
First Publication Date 2024-04-11
Owner Lam Research Corporation (USA)
Inventor
  • Joi, Aniruddha
  • Dole, Nikhil
  • Wong, Merrett
  • Hudson, Eric
  • Sheth, Jay

Abstract

A method for performing an etch process on a substrate includes applying a bias signal and a source signal to an electrode of a plasma processing system. The bias signal and the source signal are pulsed RF signals that together define a repeated pulsed RF cycle, wherein each pulsed RF cycle sequentially includes a first state, a second state, a third state, and a fourth state. The power level of the bias signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state. The power level of the source signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state.

IPC Classes  ?

57.

SYSTEMS AND METHODS FOR ETCHING A HIGH ASPECT RATIO STRUCTURE

      
Application Number 18011837
Status Pending
Filing Date 2021-12-22
First Publication Date 2024-04-11
Owner Lam Research Corporation (USA)
Inventor
  • Dole, Nikhil
  • Yanagawa, Takumi
  • Hudson, Eric A.
  • Wong, Merrett
  • Joi, Aniruddha

Abstract

A method for etching a stack is described. The method includes etching a first nitrogen-containing layer of the stack by applying a non-metal gas and discontinuing the application of the non-metal gas upon determining that a first oxide layer is reached. The first oxide layer is under the first nitrogen-containing layer. The method further includes etching the first oxide layer by applying a metal-containing gas. The application of the metal-containing gas is discontinued upon determining that a second nitrogen-containing layer will be reached. The second nitrogen-containing layer is situated under the first oxide layer. The method includes etching the second nitrogen-containing layer by applying the non-metal gas.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

58.

MATCHING PRE-PROCESSING AND POST-PROCESSING SUBSTRATE SAMPLES

      
Application Number 18262145
Status Pending
Filing Date 2022-01-19
First Publication Date 2024-04-04
Owner Lam Research Corporation (USA)
Inventor
  • Lu, Yu
  • Jin, Yansha
  • Tan, Zhongkui
  • Tetiker, Mehmet Derya

Abstract

Various embodiments herein relate to systems, methods, and media for matching pre-processing and post-processing substrate samples. In some embodiments, a computer program product for matching pre-processing and post-processing substrate samples is provided, the computer program product comprising a non-transitory computer-readable on which is provided computer-executable instructions for: receiving a plurality of samples associated with a first set of dimensions characterizing a pre-processed substrate and a plurality of samples associated with a second set of dimensions characterizing a post-processed substrate; receiving an identification of one of the pre-processed dimensions and one of the post-processed dimensions that are to be matched; generating a first probability distribution of samples for the identified pre-processed dimension and a second probability distribution of samples for the identified post-processed dimension; and matching samples of the identified pre-processed dimension to samples of the identified post-processed dimension based on the first probability distribution and the second probability distribution.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G06T 7/33 - Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods
  • G06T 7/35 - Determination of transform parameters for the alignment of images, i.e. image registration using statistical methods
  • G06T 7/62 - Analysis of geometric attributes of area, perimeter, diameter or volume

59.

Showerhead Faceplate Having Flow Apertures Configured for Hollow Cathode Discharge Suppression

      
Application Number 18529576
Status Pending
Filing Date 2023-12-05
First Publication Date 2024-04-04
Owner Lam Research Corporation (USA)
Inventor
  • Selep, Michael John
  • Breiling, Patrick G.
  • Leeser, Karl Frederick
  • Thomas, Timothy Scott
  • Kamp, David William
  • Donnelly, Sean M.

Abstract

A faceplate of a showerhead has a bottom side that faces a plasma generation region and a top side that faces a plenum into which a process gas is supplied during operation of a substrate processing system. The faceplate includes apertures formed through the bottom side and openings formed through the top side. Each of the apertures is formed to extend through a portion of an overall thickness of the faceplate to intersect with at least one of the openings to form a corresponding flow path for process gas through the faceplate. Each of the apertures has a cross-section that has a hollow cathode discharge suppression dimension in at least one direction. Each of the openings has a cross-section that has a smallest cross-sectional dimension that is greater than the hollow cathode discharge suppression dimension.

IPC Classes  ?

60.

REMOVING METAL CONTAMINATION FROM SURFACES OF A PROCESSING CHAMBER

      
Application Number 18534027
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-04-04
Owner Lam Research Corporation (USA)
Inventor
  • Yu, Jengyi
  • Tan, Samantha Siamhwa
  • Heo, Seongjun
  • Yuan, Ge
  • Kanakasabapathy, Siva Krishnan

Abstract

A method for cleaning surfaces of a substrate processing chamber includes a) supplying a first gas selected from a group consisting of silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), a hydrocarbon (CxHy where x and y are integers) and molecular chlorine (Cl2), boron trichloride (BCl3), and thionyl chloride (SOCl2); b) striking plasma in the substrate processing chamber to etch the surfaces of the substrate processing chamber; c) extinguishing the plasma and evacuating the substrate processing chamber; d) supplying a second gas including fluorine species; e) striking plasma in the substrate processing chamber to etch the surfaces of the substrate processing chamber; and f) extinguishing the plasma and evacuating the substrate processing chamber.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

61.

MULTI-PLATE ELECTROSTATIC CHUCKS WITH CERAMIC BASEPLATES

      
Application Number 18534182
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-04-04
Owner Lam Research Corporation (USA)
Inventor
  • Wang, Feng
  • Gaff, Keith
  • Kimball, Christopher

Abstract

An electrostatic chuck for a substrate processing system is provided. The electrostatic chuck includes: a top plate configured to electrostatically clamp to a substrate and formed of ceramic; an intermediate layer disposed below the top plate; and a baseplate disposed below the intermediate layer and formed of ceramic. The intermediate layer bonds the top plate to the baseplate.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01J 37/244 - Detectors; Associated components or circuits therefor
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

62.

ATOMIC LAYER DEPOSITION WITH MULTIPLE UNIFORMLY HEATED CHARGE VOLUMES

      
Application Number 18265825
Status Pending
Filing Date 2021-12-14
First Publication Date 2024-04-04
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Kadam, Nitin
  • Miller, Aaron Blake
  • Patil, Naveen
  • Wongsenakhum, Panya
  • Butail, Gorun
  • Thombare, Shruti

Abstract

Multiple charge volumes (CVs) are used to supply a reactant and an inert gas at each processing chamber to perform atomic layer deposition (ALD) on substrates. A series of pulses of the reactant can be supplied at a high flow rate from two CVs during a dose step, which extends dose time. The inert gas can be supplied at an equal starting pressure from first and second CVs at first and second purge steps. A heated pulse valve manifold (PVM) minimizes temperature variations of process gases supplied from the PVM to respective processing chamber during ALD. The PVM preheats the process gases before the process gases enter the respective CVs in the PVM. The PVM includes additional supplemental heaters above and below the CVs to maintain the temperature of the process gases within the CVs. The PVM can be rapidly cooled before performing maintenance, which reduces downtime.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate

63.

PROFILE TWISTING CONTROL IN DIELECTRIC ETCH

      
Application Number 18013493
Status Pending
Filing Date 2022-06-16
First Publication Date 2024-03-28
Owner Lam Research Corporation (USA)
Inventor
  • Mackie, Neil Macaraeg
  • Lai, Kevin
  • Li, Chen
  • Zhang, He

Abstract

A substrate processing apparatus includes a vacuum chamber with upper and lower electrodes and a processing zone for processing a substrate using plasma. The upper electrode includes a surface that is substantially parallel to a surface of the substrate when the substrate is positioned in the chamber. The apparatus includes at least one magnetic field source configured to generate one or more active magnetic fields through the processing zone, and a controller coupled to the at least one magnetic field source and the upper electrode. The controller is configured to apply RF power between the upper and lower electrodes to generate the plasma using a process gas. The controller controls the current through the at least one magnetic field source during the processing of the substrate, where the current is based on a target value corresponding to at least one characteristic of the one or more active magnetic fields.

IPC Classes  ?

64.

HIGH POWER CABLE FOR HEATED COMPONENTS IN RF ENVIRONMENT

      
Application Number 18526215
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-03-28
Owner Lam Reseach Corporation (USA)
Inventor
  • Jafarian-Tehrani, Seyed Jafar
  • Finnegan, Kenneth Walter
  • O'Brien, Sean
  • Tong, Benson Q.

Abstract

A substrate support includes an edge ring, a heater element arranged within the edge ring, a ceramic layer, at least one heating element arranged within the ceramic layer, and a cable configured to provide power from a power source to the heater element and the at least one heating element. The cable includes a first plurality of wires connected to the heater element, a second plurality of wires connected to the at least one heating element, a filter module, and an isolation device connected only to the first plurality of wires between the filter module and the heater element. The first and second pluralities of wires are twisted together within the filter module. The isolation device is configured to compensate for a resonance frequency generated during operation of the heater element and the at least one heating element.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01B 9/00 - Power cables
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H03H 7/01 - Frequency selective two-port networks

65.

CAPACITANCE MEASUREMENT WITHOUT DISCONNECTING FROM HIGH POWER CIRCUIT

      
Application Number 18522090
Status Pending
Filing Date 2023-11-28
First Publication Date 2024-03-21
Owner Lam Research Corporation (USA)
Inventor
  • Kapoor, Sunil
  • Frederick, Thomas

Abstract

Methods and apparatus for measuring capacitance are disclosed.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/52 - Controlling or regulating the coating process
  • G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
  • G01R 13/02 - Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 23/64 - Impedance arrangements

66.

INTEGRATED WAFER BOW MEASUREMENTS

      
Application Number 18525539
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-03-21
Owner Lam Research Corporation (USA)
Inventor
  • Arora, Rajan
  • Souza, Michael
  • Tang, Wayne
  • Kabouzi, Yassine
  • Feng, Ye

Abstract

In some examples, a wafer bow measurement system comprises a measurement unit including: a wafer support assembly to impart rotational movement to a measured wafer supported in the measurement unit; an optical sensor; a calibration standard to calibrate the optical sensor; a linear stage actuator to impart linear direction of movement to the optical sensor; a wafer centering sensor to determine a centering of the measured wafer supported in the measurement unit; and a wafer alignment sensor to determine an alignment of the measured wafer supported in the measurement unit.

IPC Classes  ?

  • G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
  • G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment

67.

SYSTEMS AND METHODS FOR PULSE WIDTH MODULATED DOSE CONTROL

      
Application Number 18526411
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-03-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor Gregor, Mariusch

Abstract

A substrate processing system for treating a substrate includes N manifolds, Y groups of injector assemblies, and a dose controller, where Y and N are integers greater than one. Each of the Y groups of injector assemblies includes N injector assemblies located in a processing chamber. Each of the N injector assemblies in each group of injector assemblies is in fluid communication with one of the N manifolds, respectively, and includes a valve including an inlet and an outlet. The dose controller is configured to control pulse widths output to the Y groups of injector assemblies to provide temporal dosing of the substrate

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • B05B 1/14 - Nozzles, spray heads or other outlets, with or without auxiliary devices such as valves, heating means with strainers in or outside the outlet opening
  • B05B 1/30 - Nozzles, spray heads or other outlets, with or without auxiliary devices such as valves, heating means designed to control volume of flow, e.g. with adjustable passages
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

68.

MACHINE-LEARNING IN MULTI-STEP SEMICONDUCTOR FABRICATION PROCESSES

      
Application Number 18256665
Status Pending
Filing Date 2021-12-14
First Publication Date 2024-03-21
Owner Lam Research Corporation (USA)
Inventor
  • Zhang, Yan
  • Feng, Ye
  • Talukder, Dipongkar
  • Bonde, Jeffrey D.
  • Woo, Weng Foong
  • Thimmavajjula, Karthik
  • Luque, Jorge

Abstract

Methods and systems for using a time-series of spectra to identify endpoint of a multi-step semiconductor fabrication processes such as multi-step deposition and multi-step etch processes. One method includes accessing a virtual carpet (e.g., a machine learning model) that is formed from a time-series of spectra for the multi-step processes collected during a training operation. During production, in-situ time-series of spectra are compared to the virtual carpet as part of end pointing of multi-step fabrication processes.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G06N 20/00 - Machine learning
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

69.

DETERMINATION OF RECIPES FOR MANUFACTURING SEMICONDUCTOR DEVICES

      
Application Number 18385823
Status Pending
Filing Date 2023-10-31
First Publication Date 2024-03-21
Owner Lam Research Corporation (USA)
Inventor
  • Sawlani, Kapil Umesh
  • Basu, Atashi
  • Fried, David Michael
  • Danek, Michal
  • Alden, Emily Ann

Abstract

Methods, systems, and computer programs are presented for determining the recipe for manufacturing a semiconductor with the use of machine learning (ML) to accelerate the definition of recipes. One general aspect includes a method that includes an operation for performing experiments for processing a component, each experiment controlled by a recipe, from a set of recipes, that identifies parameters for manufacturing equipment. The method further includes an operation for performing virtual simulations for processing the component, each simulation controlled by one recipe from the set of recipes. An ML model is obtained by training an ML algorithm using experiment results and virtual results from the virtual simulations. The method further includes operations for receiving specifications for a desired processing of the component, and creating, by the ML model, a new recipe for processing the component based on the specifications.

IPC Classes  ?

  • G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
  • G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
  • G06F 30/337 - Design optimisation

70.

ELECTROCHEMICAL ASSEMBLY FOR FORMING SEMICONDUCTOR FEATURES

      
Application Number 18261485
Status Pending
Filing Date 2022-01-28
First Publication Date 2024-03-14
Owner Lam Research Corporation (USA)
Inventor
  • Mayer, Steven T.
  • Thorkelsson, Kari

Abstract

Methods, apparatuses, and systems for forming deposited features on workpieces are provided herein. Generally, the techniques herein employ a deposition head to define an electrical field that facilitates electrochemical deposition. Other systems and controllers can be employed, which can assist in aligning or positioning the deposition head in proximity to a workpiece and controlling the size and location of the deposited feature.

IPC Classes  ?

  • C25D 7/12 - Semiconductors
  • C25D 5/02 - Electroplating of selected surface areas
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 21/12 - Process control or regulation

71.

ALTERNATING ETCH AND PASSIVATION PROCESS

      
Application Number 18505043
Status Pending
Filing Date 2023-11-08
First Publication Date 2024-03-14
Owner Lam Research Corporation (USA)
Inventor
  • Heo, Seongjun
  • Yu, Jengyi
  • Liang, Chen-Wei
  • Jensen, Alan J.
  • Tan, Samantha S.H.

Abstract

Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.

IPC Classes  ?

  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

72.

SYSTEMS AND METHODS FOR HOMOGENOUS INTERMIXING OF PRECURSORS IN ALLOY ATOMIC LAYER DEPOSITION

      
Application Number 18519290
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-03-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Fisher, Ilanit
  • Humayun, Raashina
  • Danek, Michal
  • Van Cleemput, Patrick
  • Thombare, Shruti

Abstract

A showerhead includes a plurality of plenums and a plurality of through holes positioned in the plurality of plenums. The plenums are stacked in a sequential order in an axial direction perpendicular to a semiconductor substrate. The plenums extend radially fully across the semiconductor substrate. The plenums are disjoint from each other and are configured to respectively supply a first metal precursor, a second metal precursor, and a reactant via the respective plenums without intermixing the first metal precursor, the second metal precursor, and the reactant in the plenums. The through holes of the respective plenums are arranged in a radial direction, which is perpendicular to the axial direction, in the same sequential order as the sequential order of the plenums. The through holes of the plenums open along a flat surface at a bottom of the showerhead. The flat surface extends radially fully across the bottom of the showerhead.

IPC Classes  ?

  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers

73.

SPATIALLY AND DIMENSIONALLY NON-UNIFORM CHANNELLED PLATE FOR TAILORED HYDRODYNAMICS DURING ELECTROPLATING

      
Application Number 18261734
Status Pending
Filing Date 2022-01-19
First Publication Date 2024-03-07
Owner Lam Research Corporation (USA)
Inventor
  • Banik, Ii, Stephen J.
  • Graham, Gabriel Hay
  • Buckalew, Bryan L.
  • Rash, Robert
  • Chua, Lee Peng
  • Wilmot, Frederick Dean
  • Lin, Chien-Chieh

Abstract

An ionically resistive ionically permeable element for use in an electroplating apparatus includes ribs to tailor hydrodynamic environment proximate a substrate during electroplating. In one implementation, the ionically resistive ionically permeable element includes a channeled portion that is at least coextensive with a plating face of the substrate, and a plurality of ribs extending from the substrate-facing surface of the channeled portion towards the substrate. Ribs include a first plurality of ribs of full maximum height and a second plurality of ribs of smaller maximum height than the full maximum height. In one implementation the ribs of smaller maximum height are disposed such that the maximum height of the ribs gradually increases in a direction from one edge of the element to the center of the element.

IPC Classes  ?

  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 3/38 - Electroplating; Baths therefor from solutions of copper
  • C25D 3/60 - Electroplating; Baths therefor from solutions of alloys containing more than 50% by weight of tin
  • C25D 17/06 - Suspending or supporting devices for articles to be coated
  • C25D 21/10 - Agitating of electrolytes; Moving of racks
  • C25D 21/12 - Process control or regulation

74.

EDGE SEAL FOR LOWER ELECTRODE ASSEMBLY

      
Application Number 18377371
Status Pending
Filing Date 2023-10-06
First Publication Date 2024-03-07
Owner Lam Research Corporation (USA)
Inventor
  • Schaefer, David
  • Chhatre, Ambarish
  • Gaff, Keith William
  • Kim, Sung Je
  • Lai, Brooke Mesler

Abstract

An edge seal for sealing an outer surface of a lower electrode assembly configured to support a semiconductor substrate in a plasma processing chamber, the lower electrode assembly including an annular groove defined between a lower member and an upper member of the lower electrode assembly. The edge seal includes an elastomeric band configured to be arranged within the groove, the elastomeric band having an annular upper surface, an annular lower surface, an inner surface, and an outer surface. When the elastomeric band is in an uncompressed state, the outer surface of the elastomeric band is concave. When the upper and lower surfaces are axially compressed at least 1% such that the elastomeric band is in a compressed state, an outward bulging of the outer surface is not greater than a predetermined distance. The predetermined distance corresponds to a maximum outer diameter of the elastomeric band in the uncompressed state.

IPC Classes  ?

  • F16J 15/02 - Sealings between relatively-stationary surfaces
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H02N 13/00 - Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect

75.

PROCESSING PARTS USING SOLID-STATE ADDITIVE MANUFACTURING

      
Application Number 18270481
Status Pending
Filing Date 2022-01-06
First Publication Date 2024-02-22
Owner Lam Research Corporaton (USA)
Inventor
  • Hazarika, Pankaj Jyoti
  • Sarobol, Pylin
  • Schick, Matthew Brian
  • Torbatisarraf, Seyedalireza

Abstract

Semiconductor-processing chamber components and methods for making the components are presented. One component includes a base including a metallic material, a metal matrix composite (MMC) layer, and a dielectric layer. The MMC layer at least partially covers the base, and the MMC layer comprises a metallic material as a continuous phase and a non-metallic material as a disperse phase. Further, the MMC layer is formed on the base using solid-state additive manufacturing (SSAM). The dielectric layer is made of a non-metallic material and is directly on the MMC layer.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • B33Y 80/00 - Products made by additive manufacturing
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

76.

DOPED OR UNDOPED SILICON CARBIDE DEPOSITION AND REMOTE HYDROGEN PLASMA EXPOSURE FOR GAPFILL

      
Application Number 18501395
Status Pending
Filing Date 2023-11-03
First Publication Date 2024-02-22
Owner Lam Research Corporation (USA)
Inventor
  • Yuan, Guangbi
  • Narkeviciute, Ieva
  • Gong, Bo
  • Varadarajan, Bhadri N.

Abstract

A doped or undoped silicon carbide (SiCxOyNz) film can be deposited in one or more features of a substrate for gapfill. After a first thickness of the doped or undoped silicon carbide film is deposited in the one or more features, the doped or undoped silicon carbide film is exposed to a remote hydrogen plasma under conditions that cause a size of an opening near a top surface of each of the one or more features to increase, where the conditions can be controlled by controlling treatment time, treatment frequency, treatment power, and/or remote plasma gas composition. Operations of depositing additional thicknesses of silicon carbide film and performing a remote hydrogen plasma treatment are repeated to at least substantially fill the one or more features. Various time intervals between deposition and plasma treatment may be added to modulate gapfill performance.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01J 37/32 - Gas-filled discharge tubes

77.

CONTROL OF WAFER BOW IN MULTIPLE STATIONS

      
Application Number 18494710
Status Pending
Filing Date 2023-10-25
First Publication Date 2024-02-15
Owner Lam Research Corporation (USA)
Inventor
  • Augustyniak, Edward
  • French, David
  • Kapoor, Sunil
  • Sakiyama, Yukinori
  • Thomas, George

Abstract

A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

78.

SYSTEMS AND TECHNIQUES FOR OPTICAL MEASUREMENT OF THIN FILMS

      
Application Number 18260713
Status Pending
Filing Date 2022-01-04
First Publication Date 2024-02-15
Owner Lam Research Corporation (USA)
Inventor
  • Yang, Liu
  • Li, Mengping
  • Ghongadi, Shantinath
  • Pfau, Andrew James

Abstract

Methods provided herein may include illuminating a region on a wafer within a semiconductor processing tool, the wafer having a layer of a material that is at least semi-transparent to light and has a measurable extinction coefficient, and the region being a first fraction of the wafer's surface, detecting light reflected off the material and off a surface underneath the material using one or more detectors and generating optical data corresponding to the detected light, generating a metric associated with a property of the material on the wafer by applying the optical data to a transfer function that relates the optical data to the metric associated with the property of the material on the wafer, determining an adjustment to one or more processing parameters for a processing module, and performing or modifying a processing operation in the processing module according to the adjusted one or more processing parameters.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01N 21/84 - Systems specially adapted for particular applications

79.

PRECURSORS FOR DEPOSITION OF MOLYBDENUM-CONTAINING FILMS

      
Application Number 18379397
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-02-15
Owner Lam Research Corporation (USA)
Inventor Blakeney, Kyle Jordan

Abstract

Molybdenum-containing films are deposited on semiconductor substrates using reactions of molybdenum-containing precursors in ALD and CVD processes. In some embodiments, the precursors can be used for deposition of molybdenum metal films with low levels of incorporation of carbon and nitrogen. In some embodiments, the films are deposited using fluorine-free precursors in a presence of exposed silicon-containing layers without using etch stop layers. The precursor, in some embodiments, is a compound that includes molybdenum, at least one halogen that forms a bond with molybdenum, and at least one organic ligand that includes an element selected from the group consisting of N, O, and S, that forms a bond with molybdenum. In another aspect, the precursor is a molybdenum compound with at least one sulfur-containing ligand, and preferably no molybdenum-carbon bonds.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds

80.

CARRIER RING DESIGNS FOR CONTROLLING DEPOSITION ON WAFER BEVEL/EDGE

      
Application Number 18494756
Status Pending
Filing Date 2023-10-25
First Publication Date 2024-02-15
Owner Lam Research Corporation (USA)
Inventor
  • Janicki, Michael John
  • Williams, Brian Joseph

Abstract

Various carrier ring designs and configurations to control an amount of deposition at a wafer's front side and bevel edge are provided. The carrier ring designs can control the amount of deposition at various locations of the wafer while deposition is performed on the wafer's back side, with no deposition desired on the front side of the wafer. These locations include front side, edge, and back side of bevel; and front and back side of the wafer. Edge profiles of the carrier rings are designed to control flow of process gases, flow of front side purge gas, and plasma effects. In some designs, through holes are added to the carrier rings to control gas flows. The edge profiles and added features can reduce or eliminate deposition at the wafer's front side and bevel edge.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01J 37/32 - Gas-filled discharge tubes

81.

ADAPTIVE MODEL TRAINING FOR PROCESS CONTROL OF SEMICONDUCTOR MANUFACTURING EQUIPMENT

      
Application Number 18258497
Status Pending
Filing Date 2021-12-13
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor
  • Talukder, Dipongkar
  • Zhang, Yan
  • Feng, Ye
  • Bonde, Jeffrey D.

Abstract

Various embodiments herein relate to systems and methods for adaptive model training. In some embodiments, a computer program product for adaptive model training is provided, the computer program product comprising a non-transitory computer readable medium on which is provided computer-executable instructions for: receiving, from a plurality of process chambers, ex situ data associated with wafers fabricated using the process chambers and in situ measurements, wherein a first machine learning model is used to predict the ex situ data using the in situ measurements; calculating a metric indicating an error associated with the first machine learning model; determining whether to update the first machine learning model; and generating a second machine learning model using the ex situ data and the in situ measurements.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/66 - Testing or measuring during manufacture or treatment

82.

MOLYBDENUM DEPOSITION IN FEATURES

      
Application Number 18258973
Status Pending
Filing Date 2022-01-03
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor
  • Na, Jeong-Seok
  • Thombare, Shruti Vivek
  • Hsieh, Yao-Tsung
  • Mandia, David Joseph
  • Lai, Chiukin Steven

Abstract

Provided are deposition processes including deposition of a thin, protective Mo layer using a molybdenum chloride (MoClx) precursor. This may be followed by Mo deposition to fill the feature using a molybdenum oxyhalide (MoOyXz) precursor. The protective Mo layer enables Mo fill using an MoOyXz precursor without oxidation of the underlying surfaces. Also provided are in-situ clean processes in which a MoClx precursor is used to remove oxidation from underlying surfaces prior to deposition. Subsequent deposition using the MoClx precursor may deposit an initial layer and/or fill a feature.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

83.

REAL-TIME CONTROL OF TEMPERATURE IN A PLASMA CHAMBER

      
Application Number 18488950
Status Pending
Filing Date 2023-10-17
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor Jing, Changyou

Abstract

Systems and methods for real-time control of temperature within a plasma chamber are described. One of the methods includes sensing a voltage in real time of a rail that is coupled to a voltage source. The voltage source supplies a voltage to multiple heater elements of the plasma chamber. The voltage that is sensed is used to adjust one or more duty cycles of corresponding one or more of the heater elements. The adjusted one or more duty cycles facilitate achieving and maintaining a temperature value within the plasma chamber over time.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)

84.

NON-ELASTOMERIC, NON-POLYMERIC, NON-METALLIC MEMBRANE VALVES FOR SEMICONDUCTOR PROCESSING EQUIPMENT

      
Application Number 18489829
Status Pending
Filing Date 2023-10-18
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor
  • Gregor, Mariusch
  • Panagopoulos, Theodoros
  • Lill, Thorsten Bernd

Abstract

Non-elastomeric, non-polymeric, non-metallic membrane valves for use in high-vacuum applications are disclosed. Such valves are functional even when the fluid-control side of the valve is exposed to a sub-atmospheric pressure field which may generally act to collapse/seal traditional elastomeric membrane valves.

IPC Classes  ?

  • F16K 99/00 - Subject matter not provided for in other groups of this subclass

85.

PROTECTIVE COATING FOR ELECTROSTATIC CHUCKS

      
Application Number 18490265
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-02-08
Owner Lam Research Corporation (USA)
Inventor
  • Topping, Stephen
  • Burkhart, Vincent E.

Abstract

An ElectroStatic Chuck (ESC) including a chucking surface having at least a portion covered with a coating of silicon oxide (SiO2), silicon nitride (Si3N4) or a combination of both. The coating can be applied in situ a processing chamber of a substrate processing tool and periodically removed and re-applied in situ to create fresh coating.

IPC Classes  ?

  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

86.

REPLACEABLE AND/OR COLLAPSIBLE EDGE RING ASSEMBLIES FOR PLASMA SHEATH TUNING INCORPORATING EDGE RING POSITIONING AND CENTERING FEATURES

      
Application Number 18377141
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor
  • Sanchez, Alejandro
  • Ford, Grayson
  • Ehrlich, Darrell
  • Alwan, Aravind
  • Leung, Kevin
  • Contreras, Anthony
  • Han, Zhumin
  • Casaes, Raphael
  • Wu, Joanna

Abstract

A first edge ring for a substrate support is provided. The first edge ring includes an annular-shaped body and one or more lift pin receiving elements. The annular-shaped body is sized and shaped to surround an upper portion of the substrate support. The annular-shaped body defines an upper surface, a lower surface, a radially inner surface, and a radially outer surface. The one or more lift pin receiving elements are disposed along the lower surface of the annular-shaped body and sized and shaped to receive and provide kinematic coupling with top ends respectively of three or more lift pins.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

87.

SELECTIVE PROCESSING WITH ETCH RESIDUE-BASED INHIBITORS

      
Application Number 18485749
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor
  • Sharma, Kashish
  • Kim, Taeseung
  • Tan, Samantha S.H.
  • Hausmann, Dennis M.

Abstract

Selective deposition of a sacrificial material on a semiconductor substrate, the substrate having a surface with a plurality of regions of substrate materials having different selectivities for the sacrificial material, may be conducted such that substantial deposition of the sacrificial material occurs on a first region of the substrate surface, and no substantial deposition occurs on a second region of the substrate surface. Deposition of a non-sacrificial material may then be conducted on the substrate, such that substantial deposition of the non-sacrificial material occurs on the second region and no substantial deposition of the non-sacrificial material occurs on the first region. The sacrificial material may then be removed such that net deposition of the non-sacrificial material occurs substantially only on the second region.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

88.

CONTROL OF METALLIC CONTAMINATION FROM METAL-CONTAINING PHOTORESIST

      
Application Number 18550733
Status Pending
Filing Date 2022-03-31
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor
  • Peter, Daniel
  • Tan, Samantha Siamhwa
  • Yu, Jengyi
  • Li, Da
  • Xue, Meng
  • Choi, Wook
  • Kim, Ji Yeon
  • Jensen, Alan J.
  • Labib, Shahd Hassan
  • Lee, Younghee
  • Zhao, Hongxiang

Abstract

Various techniques for controlling metal-containing contamination on a semiconductor substrate are provided herein. Such techniques may involve one or more of a post-development bake treatment, a chemical treatment, a plasma treatment, a light treatment, and a backside and bevel edge clean. The techniques may be combined as desired for a particular application. In many cases, the techniques are used to address metal-containing contamination that is generated during a photoresist development operation.

IPC Classes  ?

  • G03F 7/40 - Treatment after imagewise removal, e.g. baking
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma

89.

PROCESS TOOL FOR DRY REMOVAL OF PHOTORESIST

      
Application Number 18377245
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor
  • Dictus, Dries
  • Weidman, Timothy William

Abstract

Dry development or dry removal of metal-containing extreme ultraviolet radiation (EUV) photoresist is performed in atmospheric conditions or performed in process tools without vacuum equipment. Dry removal of the metal-containing EUV photoresist may be performed under atmospheric pressure or over-atmospheric pressure. Dry removal of the metal-containing EUV photoresist may be performed with exposure to an air environment or with non-oxidizing gases. A process chamber or module may be modified or integrated to perform dry removal of the metal-containing EUV photoresist with baking, wafer cleaning, wafer treatment, or other photoresist processing function. In some embodiments, the process chamber for dry removal of the metal-containing EUV photoresist includes a heating assembly for localized heating of a semiconductor substrate and a movable discharge nozzle for localized gas delivery above the semiconductor substrate.

IPC Classes  ?

  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor

90.

ELECTROSTATIC CHUCK FOR USE IN SEMICONDUCTOR PROCESSING

      
Application Number 18481886
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-02-01
Owner Lam Research Corporation (USA)
Inventor Gomm, Troy Alan

Abstract

A semiconductor substrate processing apparatus includes a vacuum chamber having a processing zone in which a semiconductor substrate may be processed, a process gas source in fluid communication with the vacuum chamber for supplying a process gas into the vacuum chamber, a showerhead module through which process gas from the process gas source is supplied to the processing zone of the vacuum chamber, and a substrate pedestal module. The substrate pedestal module includes a pedestal made of ceramic material having an upper surface configured to support a semiconductor substrate thereon during processing, a stem made of ceramic material, and coplanar electrodes embedded in the platen, the electrodes including an outer RF electrode and inner electrostatic clamping electrodes, the outer RF electrode including a ring-shaped electrode and a radially extending lead extending from the ring-shaped electrode to a central portion of the platen, wherein the ceramic material of the platen and the electrodes comprise a unitary body made in a single sintering step.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

91.

SYSTEMS AND METHODS FOR REVERSE PULSING

      
Application Number 18480495
Status Pending
Filing Date 2023-10-03
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Long, Maolin
  • Tan, Zhongkui
  • Wu, Ying
  • Fu, Qian
  • Paterson, Alex
  • Drewery, John

Abstract

Systems and methods for reverse pulsing are described. One of the methods includes receiving a digital signal having a first state and a second state. The method further includes generating a transformer coupled plasma (TCP) radio frequency (RF) pulsed signal having a high state when the digital signal is in the first state and having a low state when the digital signal is in the second state. The method includes providing the TCP RF pulsed signal to one or more coils of a plasma chamber, generating a bias RF pulsed signal having a low state when the digital signal is in the first state and having a high state when the digital signal is in the second state, and providing the bias RF pulsed signal to a chuck of the plasma chamber.

IPC Classes  ?

92.

TIN OXIDE THIN FILM SPACERS IN SEMICONDUCTOR DEVICE MANUFACTURING

      
Application Number 18482197
Status Pending
Filing Date 2023-10-06
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Smith, David Charles
  • Wise, Richard
  • Mahorowala, Arpan
  • Van Cleemput, Patrick A.
  • Van Schravendijk, Bart J.

Abstract

Thin tin oxide films can be used in semiconductor device manufacturing. In one implementation, a method of processing a semiconductor substrate includes: providing a semiconductor substrate having a plurality of protruding features residing on an etch stop layer material, and an exposed tin oxide layer in contact with both the protruding features and the etch stop layer material, where the tin oxide layer covers both sidewalls and horizontal surfaces of the protruding features; and then completely removing the tin oxide layer from horizontal surfaces of the semiconductor substrate without completely removing the tin oxide layer residing at the sidewalls of the protruding features. Next, the protruding features can be removed without completely removing the tin oxide layer that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/311 - Etching the insulating layers
  • C23C 16/40 - Oxides
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/56 - After-treatment
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

93.

INTEGRATION OF FULLY ALIGNED VIA THROUGH SELECTIVE DEPOSITION AND RESISTIVITY REDUCTION

      
Application Number 18555507
Status Pending
Filing Date 2022-04-15
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Hausmann, Dennis M.
  • Ramnani, Pankaj Ghanshyam
  • Sharma, Kashish
  • Lemaire, Paul C.
  • Mahorowala, Arpan Pravin

Abstract

Methods and apparatuses for an integration scheme for forming a fully aligned via using selective deposition of graphene on metal surfaces and selective deposition of an inhibitor layer on exposed barrier surfaces prior to depositing dielectric material are provided.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C23C 16/26 - Deposition of carbon only
  • B05D 1/00 - Processes for applying liquids or other fluent materials
  • C23C 16/34 - Nitrides
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01J 37/32 - Gas-filled discharge tubes

94.

HIGH SELECTIVITY, LOW STRESS, AND LOW HYDROGEN CARBON HARDMASKS IN LOW-PRESSURE CONDITIONS WITH WIDE GAP ELECTRODE SPACING

      
Application Number 18256893
Status Pending
Filing Date 2021-12-13
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Antony, Abbin
  • Meng, Xin
  • Chen, Xinyi
  • Sonti, Sreeram
  • Reddy, Kapu Sirish

Abstract

Provided herein are methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate by providing a wide gap electrode spacing in low-pressure conditions. A wide gap electrode may facilitate control of parasitic plasmas in low-pressure conditions, thereby enabling formation of high selectivity, low stress, and low-hydrogen AHMs. The AHM may then be used to etch features into underlying layers of the substrate.

IPC Classes  ?

  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/56 - After-treatment
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/26 - Deposition of carbon only

95.

SACRIFICIAL PROTECTION LAYER FOR ENVIRONMENTALLY SENSITIVE SURFACES OF SUBSTRATES

      
Application Number 17310303
Status Pending
Filing Date 2020-01-28
First Publication Date 2024-01-25
Owner Lam Research Corporation (USA)
Inventor
  • Sirard, Stephen M.
  • Limary, Ratchana
  • Pan, Yang
  • Hymes, Diane

Abstract

A method for protecting a surface of a substrate during processing includes a) providing a solution forming a co-polymer having a ceiling temperature; b) dispensing the solution onto a surface of the substrate to form a sacrificial protective layer, wherein the co-polymer is kinetically trapped to allow storage at a temperature above the ceiling temperature; c) exposing the substrate to ambient conditions for a predetermined period; and d) de-polymerizing the sacrificial protective layer by using stimuli selected from a group consisting of ultraviolet (UV) light and heat.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

96.

Clamshell cable guide

      
Application Number 29801355
Grant Number D1012041
Status In Force
Filing Date 2021-07-28
First Publication Date 2024-01-23
Grant Date 2024-01-23
Owner LAM RESEARCH CORPORATION (USA)
Inventor Borth, Andrew

97.

METAL ETCH

      
Application Number 18257085
Status Pending
Filing Date 2021-12-06
First Publication Date 2024-01-18
Owner Lam Research Corporation (USA)
Inventor
  • Fan, Yiwen
  • Yang, Wenbing
  • Lin, Ran
  • Tan, Samantha Siamhwa
  • Weidman, Timothy William
  • Mukherjee, Tamal

Abstract

A method for etching a metal containing material is provided. The metal containing material is exposed to a halogen containing fluid or plasma to convert at least some of the metal containing material into a metal halide material. The metal halide material is exposed to a ligand containing fluid or plasma, wherein at least some of the metal halide material is formed into a metal halide ligand complex. At least some of the metal halide ligand complex is vaporized.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

98.

COATED CONDUCTOR FOR HEATER EMBEDDED IN CERAMIC

      
Application Number 18246849
Status Pending
Filing Date 2021-09-28
First Publication Date 2024-01-18
Owner Lam Research Corporation (USA)
Inventor
  • Hollingsworth, Joel
  • Lingampalli, Ramkishan Rao
  • Hazarika, Pankaj

Abstract

Various embodiments herein relate to techniques for fabricating a platen for use in a semiconductor processing apparatus, as well as the platens and intermediate structures produced by such techniques. For example, such techniques may include depositing a coating on a heater to form a coated heater, where the heater includes a metal wire on which the coating is formed; placing the coated heater in powder; consolidating the powder into a cohesive mass to form a powder-based composite; and sintering the powder-based composite to form the platen, where the platen includes the heater embedded in sintered ceramic material. The coating on the heater may act to protect the heater from chemical attack from carbon- and/or oxygen-containing compounds that may be present during sintering. The platen may be part of a pedestal that, once fabricated, may be installed in a semiconductor processing apparatus.

IPC Classes  ?

  • H05B 3/28 - Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor embedded in insulating material
  • C04B 35/64 - Burning or sintering processes

99.

METHODS AND APPARATUS FOR CONTROLLING PLASMA IN A PLASMA PROCESSING SYSTEM

      
Application Number 18475006
Status Pending
Filing Date 2023-09-26
First Publication Date 2024-01-18
Owner Lam Research Corporation (USA)
Inventor
  • Valcore, Jr., John C.
  • Lyndaker, Bradford J.

Abstract

Methods and apparatus for processing a substrate in a multi-frequency plasma processing chamber are disclosed. The base RF signal pulses between a high power level and a low power level. Each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined power level and a second predefined power level as the base RF signal pulses. Alternatively or additionally, each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined RF frequency and a second predefined RF frequency as the base RF signal pulses. Techniques are disclosed for ascertaining in advance of production time the first and second predefined power levels and/or the first and second predefined RF frequencies for the non-base RF signals.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • B44C 1/22 - Removing surface-material, e.g. by engraving, by etching
  • H03L 5/00 - Automatic control of voltage, current, or power

100.

C-shroud Modification For Plasma Uniformity Without Impacting Mechanical Strength Or Lifetime Of The C-shroud

      
Application Number 18042198
Status Pending
Filing Date 2022-01-14
First Publication Date 2024-01-11
Owner Lam Research Corporation (USA)
Inventor
  • Mankidy, Pratik
  • Kim, Jaewon
  • Singh, Harmeet
  • Li, Ming

Abstract

A confinement ring for use in a plasma processing chamber includes an upper horizontal section, a vertical section, and a lower horizontal section. The upper horizontal section extends between an upper inner radius and an outer radius of the confinement ring, The lower horizontal section extends between an lower inner radius and the outer radius of the confinement ring, and includes an extension section that extends to the lower inner radius. A top surface of the lower horizontal section provides for an angle down toward the lower inner radius. The vertical section is disposed between the outer radius and an inside radius of the confinement ring. The vertical section connects the upper horizontal section to the lower horizontal section of the confinement ring.

IPC Classes  ?

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