Lam Research Corporation

United States of America

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2023 September (MTD) 45
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H01J 37/32 - Gas-filled discharge tubes 1,467
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components 1,117
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 766
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber 743
H01L 21/3065 - Plasma etching; Reactive-ion etching 557
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07 - Machines and machine tools 134
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1.

FAST ATOMIC LAYER ETCH

      
Application Number US2023014520
Publication Number 2023/183129
Status In Force
Filing Date 2023-03-03
Publication Date 2023-09-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Yang, Wenbing
  • Tan, Samantha Siamhwa
  • Pan, Yang
  • Fan, Yiwen
  • Bennet, Alexander Declan
  • Balan, Arunima Deya
  • Patrick, Roger
  • Van Cleemput, Patrick August
  • Witkowicki, Derek
  • Li, Baichang
  • Lee, Young Ah
  • Thomas, Clint Edward

Abstract

A method for etching an etch layer is provided. The method comprises a plurality of cycles, wherein each cycle, comprises exposing the etch layer to neutral radicals for a time between 10 ms and 600 ms, wherein the neutral radicals are absorbed into the etch layer to form a modified part of the etch layer and exposing the etch layer to bombardment ions for a time between 10 ms and 600 ms, wherein the bombardment ions remove the modified part of the etch layer.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

2.

WAFER LEVEL UNIFORMITY CONTROL IN REMOTE PLASMA FILM DEPOSITION

      
Application Number 18327558
Status Pending
Filing Date 2023-06-01
First Publication Date 2023-09-28
Owner Lam Research Corporation (USA)
Inventor
  • Hohn, Geoffrey
  • Qiu, Huatan
  • Batzer, Rachel E.
  • Yuan, Guangbi
  • Gui, Zhe

Abstract

An assembly for use in a process chamber for depositing a film on a wafer. The assembly includes a pedestal having a pedestal top surface extending from a central axis of the pedestal to an outer edge, the pedestal top surface having a plurality of wafer supports for supporting a wafer. A pedestal step having a step surface extending from a step inner diameter towards the outer edge of the pedestal. A focus ring rests on the step surface and having a mesa extending from an outer diameter of the focus ring to a mesa inner diameter. A shelf steps downwards from a mesa surface at the mesa inner diameter, and extends between the mesa inner diameter and an inner diameter of the focus ring. The shelf is configured to support at least a portion of a wafer bottom surface of the wafer at a process temperature.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

3.

REDUCING INTRALEVEL CAPACITANCE IN SEMICONDUCTOR DEVICES

      
Application Number 18003145
Status Pending
Filing Date 2021-06-28
First Publication Date 2023-09-28
Owner Lam Research Corporation (USA)
Inventor
  • Abel, Joseph R.
  • Van Schravendijk, Bart J.
  • Curtin, Ian John
  • Agnew, Douglas Walter
  • Austin, Dustin Zachary
  • Gupta, Awnish

Abstract

Methods of forming air gaps in hole and trench structures are disclosed. The methods may be used to form buried voids, i.e., voids for which the top is below the top of the adjacent features. The methods include inhibition of the hole or trench structures and selective deposition at the top of the structure forming an air gap within the structures. In some embodiments, the methods are to reduce intra-level capacitance in semiconductor devices.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

4.

HIGH ENERGY ATOMIC LAYER ETCH OF A CARBON CONTAINING LAYER

      
Application Number US2023015526
Publication Number 2023/183199
Status In Force
Filing Date 2023-03-17
Publication Date 2023-09-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Yang, Wenbing
  • Li, Baichang
  • Balan, Arunima Deya
  • Fan, Yiwen
  • Tan, Samantha Siamhwa
  • Van Cleemput, Patrick August
  • Pan, Yang
  • Lee, Younghee
  • Bennet, Alexander Declan
  • Patrick, Roger
  • Witkowicki, Derek J.
  • Lee, Young-Ah
  • Thomas, Clint Edward

Abstract

A method comprises a plurality of cycles, wherein each cycle, comprises exposing the carbon containing etch layer to oxygen radicals to modify part of the carbon containing etch layer. The carbon containing etch layer is exposed to bombardment ions with an energy greater than 100 eV for less than 0.5 seconds, wherein the bombardment ions remove the modified part of the carbon containing etch layer to form etched features.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

5.

SHOWERHEAD ASSEMBLY AND SUBSTRATE PROCESSING SYSTEMS FOR IMPROVING DEPOSITION THICKNESS UNIFORMITY

      
Application Number US2022026104
Publication Number 2023/183009
Status In Force
Filing Date 2022-04-25
Publication Date 2023-09-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Jeon, Eli
  • Boatright, Daniel
  • Chen, Philip
  • Poddar, Debotosh
  • Hart, Kyle Watt
  • Agnew, Douglas Walter
  • Subramanya, Kashyap

Abstract

A showerhead assembly includes a showerhead with an upper portion including a gas channel extending in a first direction and having a first width in a second direction. A lower portion is connected to the upper portion and includes a faceplate including a plurality of gas through holes extending vertically through the faceplate in the first direction and a baffle plate arranged on a plurality of posts above the faceplate and below an outlet of the gas channel. A gas plenum is defined between the upper portion and the lower portion, extends in the second direction, and is in fluid communication with the gas channel. The showerhead assembly includes a back side gas system to supply gas to a bellows volume defined by a bellows arranged around an upper portion of the showerhead. First and second annular gas flows are supplied across an outer surface of the showerhead.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

6.

SPARK PLASMA SINTERED COMPONENT FOR CRYO-PLASMA PROCESSING CHAMBER

      
Application Number US2023015810
Publication Number 2023/183330
Status In Force
Filing Date 2023-03-21
Publication Date 2023-09-28
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Xu, Lin
  • Srinivasan, Satish
  • Singh, Harmeet
  • Daugherty, John
  • Hazarika, Pankaj

Abstract

44C, WC, TaC, W, or Mo.

IPC Classes  ?

7.

SUBTRACTIVE COPPER ETCH

      
Application Number 18010422
Status Pending
Filing Date 2021-08-12
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Yang, Wenbing
  • Lin, Ran
  • Tan, Samantha Siamhwa
  • Brouri, Mohand
  • Pan, Yang

Abstract

A method for atomic layer etching copper or copper alloy over a substrate in a plasma processing chamber comprising a plurality of cycles is provided. Each cycle of the plurality of cycles comprises a copper modification phase and an activation phase. The copper modification phase comprises flowing a modification gas into the plasma processing chamber, transforming the modification gas into a modification plasma, and exposing the copper or copper alloy to the modification plasma, wherein at least a part of the copper or copper alloy is modified. The activation phase comprises flowing an activation gas into the plasma processing chamber, wherein the activation gas, comprises a hydrogen containing gas, transforming the activation gas into an activation plasma, and exposing the modified copper or copper alloy to the activation plasma, wherein at least a volatile copper or copper alloy complex is formed.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

8.

THIN SHADOW RING FOR LOW-TILT TRENCH ETCHING

      
Application Number 18017208
Status Pending
Filing Date 2021-07-30
First Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Setton, David
  • Chhatre, Ambarish
  • Canniff, Justin Charles
  • Marohl, Dan
  • Rosslee, Craig

Abstract

A thin shadow ring for a substrate processing system includes an annular body having an inner diameter and an outer diameter. The inner diameter and the outer diameter define a cross-sectional width of the annular body between the inner diameter and the outer diameter. At least two tabs extend radially outward from the annular body. The cross-sectional width of the annular body between the inner diameter and the outer diameter is less than 1.0 inch.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

9.

COPPER ELECTRODEPOSITION SEQUENCE FOR THE FILLING OF COBALT LINED FEATURES

      
Application Number 18202062
Status Pending
Filing Date 2023-05-25
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Velmurugan, Jeyavel
  • Buckalew, Bryan L.
  • Ponnuswamy, Thomas A.

Abstract

In one example, an electroplating system comprises a bath reservoir, an anode in the bath reservoir, and a direct-current power supply. The bath reservoir initially contains a first-electrolyte solution that includes an alkaline copper-complexed solution. The bath reservoir is arranged to be drained of the first-electrolyte solution and replaced with and contain a second-electrolyte solution. The second-electrolyte solution includes an acidic-copper plating solution. The direct-current power supply generates a first direct current between the clamp and the anode to electroplate a first copper layer on the cobalt layer of the substrate submerged in the first-electrolyte solution. The direct-current power supply then generates a second direct current between the clamp and the anode to electroplate a second copper layer on the first copper layer of the substrate submerged in the second electrolyte solution. Other systems and methods are also described.

IPC Classes  ?

  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
  • C25D 3/38 - Electroplating; Baths therefor from solutions of copper
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 17/06 - Suspending or supporting devices for articles to be coated
  • C25D 5/10 - Electroplating with more than one layer of the same or of different metals
  • C25D 5/34 - Pretreatment of metallic surfaces to be electroplated
  • H01L 21/321 - After-treatment
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C25D 5/18 - Electroplating using modulated, pulsed or reversing current

10.

LOW CEILING TEMPERATURE HOMOPOLYMERS AS SACRIFICIAL PROTECTION LAYERS FOR ENVIRONMENTALLY SENSITIVE SUBSTRATES

      
Application Number 18006552
Status Pending
Filing Date 2021-07-23
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Sirard, Stephen M.
  • Blachut, Gregory
  • Limary, Ratchana
  • Hymes, Diane
  • Pan, Yang

Abstract

The present disclosure relates to a stimulus responsive polymer (SRP) that includes a homopolymer. Methods, films, and formulations employing an SRP are also described herein.

IPC Classes  ?

  • C08L 61/18 - Condensation polymers of aldehydes or ketones with aromatic hydrocarbons or their halogen derivatives only
  • B05D 1/00 - Processes for applying liquids or other fluent materials
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material

11.

ELECTRON EXCITATION ATOMIC LAYER ETCH

      
Application Number 18187342
Status Pending
Filing Date 2023-03-21
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Berry, Iii, Ivan L.
  • Lill, Thorsten
  • Fischer, Andreas

Abstract

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

12.

SHOWERHEAD FOR SUBSTRATE PROCESSING SYSTEMS

      
Application Number US2023014877
Publication Number 2023/177570
Status In Force
Filing Date 2023-03-09
Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Chan, Simon
  • Parmar, Ravi
  • Hosur Shivalinge Gowda, Arun, Kumar
  • Kho, Leonard
  • Yan, Zhongbo
  • Kittur, Vishalsagar
  • Boochakravarthy, Ashwin, Agathya
  • Ba, Xiaolan
  • Kaushik, Lav
  • Suh, Tae Won

Abstract

A dual-plenum showerhead for a substrate processing system comprises a base portion and a backplate. The base portion comprises a first surface facing a substrate, a second surface opposite the first surface, and a sidewall extending between the first surface and the second surface. The first and second surfaces are flat. The first and second surfaces and the sidewall define a first plenum. The backplate comprises a shaped surface extending from a center portion of the backplate to a periphery of the backplate. The shaped surface comprises a plurality of portions. At least one of the portions is parallel to the base portion. At least one of the portions slopes towards the base portion. The periphery of the backplate is attached to the second surface of the base portion defining a second plenum.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges

13.

DUAL PLENUM SHOWERHEAD WITH CENTER TO EDGE TUNABILITY

      
Application Number US2023062484
Publication Number 2023/177950
Status In Force
Filing Date 2023-02-13
Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor Birru, Krishna

Abstract

A dual-zone process gas distribution showerhead is disclosed. In at least one embodiment, dual-zone showerhead comprises an inner zone and an outer zone surrounding the inner zone. At least a first plenum is within the first zone and coupled to a first gas inlet port. In at least one embodiment, outer zone comprises at least a second plenum coupled to a second gas inlet port. In at least one embodiment, first plenum is coupled to a first plurality of apertures within the inner zone. In at least one embodiment, second plenum is coupled to a second plurality of apertures in the outer zone.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges

14.

APPARATUS AND METHODS FOR REDUCING WAFER BACKSIDE DAMAGE

      
Application Number US2023063240
Publication Number 2023/177967
Status In Force
Filing Date 2023-02-24
Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sundaram, Sairam
  • Chandrasekharan, Ramesh
  • Gage, Christopher

Abstract

A wafer chuck assembly is disclosed, in accordance with at least one embodiment. In at least one embodiment, wafer chuck assembly comprises a wafer chuck comprising a substantially circular surface having a first area. In least one embodiment, plurality of mesas is distributed over the wafer chuck surface. In at least one embodiment, individual ones of the plurality of mesas extend a height above the wafer chuck surface. In at least one embodiment, plurality of mesas has a contact surface having a second area that is at least 3% of the first area.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

15.

LOW-K DIELECTRIC PROTECTION DURING PLASMA DEPOSITION OF SILICON NITRIDE

      
Application Number US2023064491
Publication Number 2023/178216
Status In Force
Filing Date 2023-03-15
Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Gupta, Awnish
  • Austin, Dustin Zachary
  • Bhimarasetti, Gopinath
  • Gong, Bo
  • Mckerrow, Andrew John
  • Petraglia, Jennifer Leigh

Abstract

Methods and apparatuses for depositing silicon nitride using a plasma over low-k dielectric material while protecting the low-k dielectric material are provided. The methods comprise providing a substrate having a dielectric material deposited thereon, depositing a protective layer on the dielectric material in a plasma-free environment, and after depositing the protective layer, exposing the substrate to a first plasma to deposit a first silicon nitride while converting at least a portion of the protective layer to second silicon nitride.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/34 - Nitrides
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

16.

APPARATUS FOR PROCESSING A WAFER-SHAPED ARTICLE

      
Application Number EP2023055702
Publication Number 2023/174750
Status In Force
Filing Date 2023-03-07
Publication Date 2023-09-21
Owner LAM RESEARCH AG (Austria)
Inventor
  • Puggl, Michael
  • Brugger, Michael
  • Kohlweiss, Clara Theresia
  • Fischer, Christian
  • Egger, Stefan

Abstract

Apparatus for processing a wafer-shaped article, the apparatus comprising: a rotary chuck configured to receive a wafer-shaped article, wherein the rotary chuck comprises a plurality of contact elements, each of which is movable between a gripping position where the contact element is configured to contact a radially outer edge of the wafer-shaped article and a non-gripping position; and a non-rotating plate configured to be on an opposite side of the wafer-shaped article to the rotary chuck when the wafer-shaped article is received by the rotary chuck, wherein the non-rotating plate comprises a gas supply arrangement that is configured to supply gas to support the wafer-shaped article according to the Bernoulli principle.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

17.

COMBINED SELF-FORMING BARRIER AND SEED LAYER BY ATOMIC LAYER DEPOSITION

      
Application Number 18041391
Status Pending
Filing Date 2021-08-10
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Blakeney, Kyle Jordan
  • Dordi, Yezdi

Abstract

An electrically conductive structure in an integrated circuit (IC) includes recessed features in a dielectric layer filled with metal. The recessed features include a conformal, self-forming diffusion barrier and seed layer to limit oxidation of the metal into ions that will diffuse through the dielectric. The self-forming diffusion barrier and seed layer may also form a surface oxide layer that can be removed by an acidic solution

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 28/02 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and only coatings of metallic material
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C25D 5/02 - Electroplating of selected surface areas
  • C25D 7/12 - Semiconductors

18.

OPTIMIZING EDGE RADICAL FLUX IN A DOWNSTREAM PLASMA CHAMBER

      
Application Number 18010423
Status Pending
Filing Date 2021-12-14
First Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Bravo, Andrew Stratton
  • Park, Pilyeon
  • Kosche, Serge
  • Monbeig, Julien Augustin
  • Kawaguchi, Mark
  • Whitten, Stephen
  • Kon, Shih-Chung

Abstract

A showerhead for a processing chamber in a substrate processing system includes an upper portion having a lower surface and an upper surface and a faceplate. A lower surface of the faceplate is below the lower surface of the upper portion such that the showerhead extends into an interior volume of the processing chamber and the faceplate includes a plurality of holes arranged in a pattern to provide fluid communication between a remote plasma source above the showerhead and the interior volume of the processing chamber. A sidewall extends upward from an outer edge of the faceplate between the faceplate and the upper portion and the upper portion extends radially outward from the sidewall of the showerhead and is configured to be mounted on a sidewall of the processing chamber. A heater is embedded in the upper portion of the showerhead.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H05B 1/02 - Automatic switching arrangements specially adapted to heating apparatus

19.

METAL OXIDE WITH LOW TEMPERATURE FLUORINATION

      
Application Number 18017246
Status Pending
Filing Date 2021-07-06
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Pape, Eric A.
  • Koshy, Robin

Abstract

A method for providing a component for using in a plasma processing chamber is provided, wherein the component has a plasma facing surface. A metal oxide layer is provided on the plasma facing surface of the component. The metal oxide layer is exposed to a fluorine containing gas at a temperature of less than 600° C. for at least 2 hours at a partial pressure of at least 0.1 bar.

IPC Classes  ?

  • C23C 16/40 - Oxides
  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C23C 16/56 - After-treatment

20.

APPARATUS FOR PROCESSING A WAFER-SHAPED ARTICLE

      
Application Number 18019653
Status Pending
Filing Date 2021-04-07
First Publication Date 2023-09-21
Owner LAM RESEARCH AG (Austria)
Inventor
  • Brugger, Michael
  • Schier, Burkhart
  • Duller, Michael

Abstract

Apparatus for processing a wafer-shaped article, the apparatus comprising a support configured to support the wafer-shaped article during a processing operation; wherein: the support comprises a support body and a plurality of gripping pin assemblies adapted and positioned relative to the support body for gripping the wafer-shaped article, wherein each of the gripping pin assemblies is rotatable relative to the support body between a gripping configuration in which the gripping pin assemblies grip the wafer-shaped article, and a non-gripping configuration in which the gripping pin assemblies do not grip the wafer-shaped article; each of the gripping pin assemblies protrudes from a respective hole in the support body; and a sealing member is positioned between at least one of the gripping pin assemblies and the respective hole, the sealing member being configured to restrict infiltration of a processing liquid used in the processing operation into the hole.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

21.

Systems and Methods for Extracting Process Control Information from Radiofrequency Supply System of Plasma Processing System

      
Application Number 18011830
Status Pending
Filing Date 2021-06-28
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Bhowmick, Ranadeep
  • Marakhtanov, Alexei
  • Kozakevich, Felix Leib
  • Holland, John

Abstract

A first radiofrequency signal generator is set to generate a low frequency signal. A second radiofrequency signal generator is set to generate a high frequency signal. An impedance matching system has a first input connected to an output of the first radiofrequency signal generator and a second input connected to an output of the second radiofrequency signal generator. The impedance matching system controls impedances at the outputs of the first and second radiofrequency signal generators. An output of the impedance matching system is connected to a radiofrequency supply input of a plasma processing system. A control module monitors reflected voltage at the output of the second radiofrequency signal generator. The control module determines when the reflected voltage indicates a change in impedance along a transmission path of the high frequency signal that is indicative of a particular process condition and/or event within the plasma processing system.

IPC Classes  ?

22.

ULTRATHIN ATOMIC LAYER DEPOSITION FILM ACCURACY THICKNESS CONTROL

      
Application Number 18188325
Status Pending
Filing Date 2023-03-22
First Publication Date 2023-09-21
Owner Lam Research Corporation (USA)
Inventor
  • Qian, Jun
  • Kang, Hu
  • Lavoie, Adrien
  • Matsuyama, Seiji
  • Kumar, Purushottam

Abstract

Methods for depositing ultrathin films by atomic layer deposition with reduced wafer-to-wafer variation are provided. Methods involve exposing the substrate to soak gases including one or more gases used during a plasma exposure operation of an atomic layer deposition cycle prior to the first atomic layer deposition cycle to heat the substrate to the deposition temperature.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/40 - Oxides

23.

FEEDBACK CONTROL SYSTEMS FOR IMPEDANCE MATCHING

      
Application Number US2022030252
Publication Number 2023/177409
Status In Force
Filing Date 2022-05-20
Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Dehghan, Sina
  • Konkola, Paul
  • Topping, Stephen
  • Leeser, Karl Frederick

Abstract

Methods, systems, and media for feedback control systems for impedance matching are described. A computer program product for an impedance matching and power distribution network is disclosed. The computer program product may comprise computer-executable instructions which may cause obtaining, at a present time, present values of variable reactances associated with a station of a process chamber, wherein the variable reactances are associated with a first feedback control system for performing impedance matching for the process chamber, and wherein frequency tuning is being performed on an RF generator of the process chamber in association with a second feedback control system for performing impedance matching for the process chamber. The instructions may cause determining updated values of the variable reactances for the station to be utilized in connection with the first feedback control system based at least in part on an error associated with the second feedback control system.

IPC Classes  ?

24.

SIDEWALL PASSIVATION USING ALDEHYDE OR ISOCYANATE CHEMISTRY FOR HIGH ASPECT RATIO ETCH

      
Application Number US2023015028
Publication Number 2023/177594
Status In Force
Filing Date 2023-03-10
Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor Hudson, Eric A.

Abstract

Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along the sidewalls. In some cases, the protective coating is deposited using molecular layer deposition techniques. The protective coating may be deposited using particular reactants that result in relatively complete sidewall coating at relatively low temperatures. In some implementations, one or more of the reactants include an aldehyde functional group. In some implementations, one or more of the reactants include an isocyanate functional group.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/52 - Controlling or regulating the coating process
  • H01J 37/32 - Gas-filled discharge tubes

25.

SEAM-FREE AND CRACK-FREE DEPOSITION

      
Application Number US2023064472
Publication Number 2023/178203
Status In Force
Filing Date 2023-03-15
Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Gupta, Awnish
  • Varnell, Jason Alexander
  • Van Schravendijk, Bart J.
  • Agnew, Douglas Walter
  • Ramasagaram, Praneeth

Abstract

Methods and apparatuses for depositing material into features on a substrate by depositing a first portion of a material; etching a V-shaped hole at or near a feature opening; and depositing a second portion of the material to fill the feature are provided herein.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/311 - Etching the insulating layers
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment

26.

REDUCING CAPACITANCE IN SEMICONDUCTOR DEVICES

      
Application Number US2023064578
Publication Number 2023/178273
Status In Force
Filing Date 2023-03-16
Publication Date 2023-09-21
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Curtin, Ian John
  • Agnew, Douglas Walter
  • Gui, Zhe
  • Peissker, Tobias
  • Van Schravendijk, Bart J.

Abstract

Methods of forming air gaps in hole and trench structures using plasma enhanced atomic layer deposition (PEALD) are disclosed. The methods may be used to form buried voids, i.e., voids for which the top is below the top of the adjacent features. In some embodiments, the methods are to reduce intra-level capacitance in semiconductor devices.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C23C 16/34 - Nitrides
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

27.

SELF-LIMITING GROWTH

      
Application Number 18310523
Status Pending
Filing Date 2023-05-01
First Publication Date 2023-09-14
Owner Lam Research Corporation (USA)
Inventor
  • Collins, Joshua
  • Kennedy, Griffin John
  • Bamnolker, Hanna
  • Danek, Michal
  • Thombare, Shruti Vivek
  • Van Cleemput, Patrick A.
  • Butail, Gorun

Abstract

Provided herein are methods and apparatuses for forming metal films such as tungsten (W) and molybdenum (Mo) films on semiconductor substrates. The methods involve forming a reducing agent layer, then exposing the reducing agent layer to a metal precursor to convert the reducing agent layer to a layer of the metal. In some embodiments, the reducing agent layer is a silicon- (Si-) and boron- (B-) containing layer. The methods may involve forming the reducing agent layer at a first substrate temperature, raising the substrate temperature to a second substrate temperature, and then exposing the reducing agent layer to 10 the metal precursor at the second substrate temperature. The methods may be used to form fluorine-free tungsten or molybdenum films in certain embodiments. Apparatuses to perform the methods are also provided.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

28.

DISTRIBUTED PLASMA SOURCE ARRAY

      
Application Number 17927328
Status Pending
Filing Date 2021-05-10
First Publication Date 2023-09-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Benjamin, Neil M. P.
  • Patrick, Roger

Abstract

A substrate processing system includes a processing chamber including a window. A substrate support is arranged inside the processing chamber to support a substrate during plasma processing. A first array including E inductive coils arranged adjacent to and outside of the processing chamber, where E is an integer greater than three. A second array includes D RF direct drive circuits configured to output RF power to the first array, where D is an integer greater than three, and to generate plasma inside of the processing chamber.

IPC Classes  ?

29.

LOW RESISTANCE GATE OXIDE METALLIZATION LINER

      
Application Number 18003137
Status Pending
Filing Date 2020-07-29
First Publication Date 2023-09-14
Owner Lam Research Corporation (USA)
Inventor
  • Schloss, Lawrence
  • Chandrashekar, Anand
  • Gao, Juwen
  • Sawant-Goubert, Stephanie Noelle Sandra
  • Pan, Yu

Abstract

Methods and apparatuses for forming low resistivity tungsten using tungsten nitride barrier layers are provided herein. Methods involve depositing extremely thin tungsten nitride barrier layers prior to depositing tungsten nucleation and bulk tungsten layers. Methods are applicable for fabricating tungsten word lines in 3D NAND fabrication as well as for fabricating tungsten-containing components of DRAM and logic fabrication. Apparatus included processing stations with multiple charge volumes to pressurize gases in close vicinity to a showerhead of a processing chamber for processing semiconductor substrates.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • C23C 16/34 - Nitrides
  • C23C 16/14 - Deposition of only one other metal element
  • C23C 16/56 - After-treatment
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

30.

ENCAPSULATED COMPRESSION WASHER FOR BONDING CERAMIC PLATE AND METAL BASEPLATE OF ELECTROSTATIC CHUCKS

      
Application Number US2023014374
Publication Number 2023/172434
Status In Force
Filing Date 2023-03-02
Publication Date 2023-09-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor Pape, Eric A.

Abstract

An electrostatic chuck for a substrate processing system includes a baseplate, a ceramic plate, and a bond layer. The baseplate includes a metallic material, a sidewall and upper and lower surfaces of the baseplate defining a plenum. The baseplate further includes an inlet in fluid communication with the plenum and a first plurality of through holes extending from the upper surface to the plenum. The ceramic plate includes a second plurality of through holes extending between upper and lower surfaces of the ceramic plate. The bond layer bonds the baseplate and the ceramic plate. The bond layer includes a plurality washers. Each washer includes a core comprising a third material and a coating of a fourth material surrounding the core. The washers and the bond layer are of the same height. Inner diameters of the washers are aligned with diameters of the first and second plurality of through holes.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

31.

PEDESTAL SHROUD TO DIRECT FLOW OF PROCESS GASES AND BYPRODUCTS IN SUBSTRATE PROCESSING SYSTEMS

      
Application Number US2023014612
Publication Number 2023/172507
Status In Force
Filing Date 2023-03-06
Publication Date 2023-09-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Kubasad, Sachin Allamaprabhu
  • Wongsenakhum, Panya
  • Patil, Ravikumar
  • Hosur Shivalinge Gowda, Arun Kumar
  • Gehani, Sandeep

Abstract

A station of a substrate processing system includes a pedestal and a shroud. The pedestal is arranged in a well of the station. The pedestal includes a base portion to support a substrate and a stem portion extending from the base portion into the well of the station. The shroud is coupled to the base portion of the pedestal. The shroud surrounds the base portion and extends along the stem portion into the well of the station. The station further includes a liner lining an inner sidewall of the well of the station. The station further includes a liner lining a pedestal-facing surface of a bottom of the well of the station. The station further includes a hollow object disposed in the well of the station. The hollow object is of smaller dimensions than the well of the station.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

32.

ANOLYTE SOLUTION DOSING FOR ELECTROPLATING APPARATUS

      
Application Number US2023063748
Publication Number 2023/172854
Status In Force
Filing Date 2023-03-05
Publication Date 2023-09-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Vo, Tune
  • Quaglio, Marc
  • Ossowski, Lawrence
  • Kingrey, Lawrence
  • Sigamani, Nirmal Shankar
  • Hanson, Jeff

Abstract

An electroplating apparatus comprises an anode chamber flow loop. The anode chamber flow loop comprises an anode chamber that contains an anolyte solution and an anode. A flow meter doses anolyte solution components into the anode chamber flow loop. A first valve manifold supplies components of the anolyte solution to the flow meter. The first valve manifold comprises a first shutoff valve operable to selectively fluidly couple a source of water to the flow meter, and a second shutoff valve operable to fluidly couple sources of acid and bulk inorganic plating components to the flow meter. A second valve manifold is fluidly coupled to the second shutoff valve and comprises a third shutoff valve operable to fluidly couple the source of bulk inorganic plating components to the first valve manifold, and a fourth shutoff valve operable to fluidly couple the source of acid to the first valve manifold.

IPC Classes  ?

  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 21/12 - Process control or regulation

33.

PHOTORESISTS CONTAINING TANTALUM

      
Application Number 18005328
Status Pending
Filing Date 2021-07-16
First Publication Date 2023-09-14
Owner Lam Research Corporation (USA)
Inventor
  • Hansen, Eric Calvin
  • Wu, Chenghao
  • Weidman, Timothy William

Abstract

The present disclosure relates to a film formed with a tantalum-based precursor, as well as methods for forming and employing such films. The film can be employed as a photopatternable film or a radiation-sensitive film. In non-limiting embodiments, the radiation can include extreme ultraviolet (EUV) or deep ultraviolet (DUV) radiation.

IPC Classes  ?

  • G03F 7/004 - Photosensitive materials
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/32 - Liquid compositions therefor, e.g. developers
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
  • G03F 7/40 - Treatment after imagewise removal, e.g. baking
  • G03F 7/20 - Exposure; Apparatus therefor

34.

INTEGRATED DRY PROCESSES FOR PATTERNING RADIATION PHOTORESIST PATTERNING

      
Application Number 18184545
Status Pending
Filing Date 2023-03-15
First Publication Date 2023-09-14
Owner Lam Research Corporation (USA)
Inventor
  • Yu, Jengyi
  • Tan, Samantha S.H.
  • Alvi, Mohammed Haroon
  • Wise, Richard
  • Pan, Yang
  • Gottscho, Richard Alan
  • Lavoie, Adrien
  • Kanakasabapathy, Sivananda Krishnan
  • Weidman, Timothy William
  • Lin, Qinghuang
  • Hubacek, Jerome S.

Abstract

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G03F 7/38 - Treatment before imagewise removal, e.g. prebaking
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/004 - Photosensitive materials
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma

35.

SYSTEMS AND METHODS FOR REDUCING REFLECTED POWER AFTER A STATE TRANSITION

      
Application Number US2023013166
Publication Number 2023/172384
Status In Force
Filing Date 2023-02-15
Publication Date 2023-09-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Bhowmick, Ranadeep
  • Holland, John

Abstract

A method for reducing reflected power associated with a high frequency (HF) radio frequency (RF) generator after a transition state is described. The method includes controlling the HF RF generator to divide a state of an HF RF signal into a plurality of sub-states. The plurality of sub-states include a first sub-state and a second sub-state. The method further includes controlling the HF RF generator to apply a first reference high frequency value during the first sub-state and a second reference high frequency value during the second sub-state. The method includes applying a first set of HF offset values from the first reference high frequency value during the first sub-state and applying a second set of HF offset values from the second reference high frequency value during the second sub-state.

IPC Classes  ?

36.

METHODS OF SELECTIVE DEPOSITION AND CHEMICAL DELIVERY SYSTEMS

      
Application Number US2023014982
Publication Number 2023/172736
Status In Force
Filing Date 2023-03-10
Publication Date 2023-09-14
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sharma, Kashish
  • Bihari, Nupur
  • Edwards, Benjamin
  • Mahorowala, Arpan, Pravin
  • Doddamani, Avinash, Gouda
  • Kumar, Ashwin
  • Jaiswal, Avinash

Abstract

Systems and methods of selectively depositing metal oxide on an exposed metal surface relative to a dielectric material on a substrate by pre-treatment with a hydroxy species-generating plasma prior to inhibition of the metal surface with an inhibitor, and subsequent metal oxide deposition on the dielectric material are disclosed. Exemplary inhibitors include low vapor pressure inhibitors. Exemplary systems include heated ampoules and gas lines for delivering inhibitors or other processing chemicals.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/40 - Oxides
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/52 - Controlling or regulating the coating process

37.

SUBSTRATE PROCESSING SYSTEMS INCLUDING GAS DELIVERY SYSTEM WITH REDUCED DEAD LEGS

      
Application Number 18196605
Status Pending
Filing Date 2023-05-12
First Publication Date 2023-09-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Chandrasekharan, Ramesh
  • Xavier, Antonio
  • Pasquale, Frank Loren
  • Blaquiere, Ryan
  • Petraglia, Jennifer Leigh
  • Mamunuru, Meenakshi

Abstract

A gas delivery system includes a 2-port valve including a first valve located between a first port and a second port. A 4-port valve includes a first node connected to a first port and a second port. A bypass path is located between the third port and the fourth port. A second node is located along the bypass path. A second valve is located between the first node and the second node. A manifold block defines gas flow channels configured to connect the first port of the 4-port valve to a first inlet, configured to connect the second port of the 4-port valve to the first port of the 2-port valve, the third port of the 4-port valve to a second inlet, the second port of the 2-port valve to a first outlet, and the fourth port of the 4-port valve to a second outlet.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

38.

REMOVABLE SHOWERHEAD FACEPLATE FOR SEMICONDUCTOR PROCESSING TOOLS

      
Application Number 18000635
Status Pending
Filing Date 2021-06-04
First Publication Date 2023-09-07
Owner Lam Research Corporation (USA)
Inventor
  • Shankarnarayana, Manjesh
  • Luo, Bin
  • Lenz, Eric H.

Abstract

Showerheads for semiconductor processing operations are disclosed that have removable faceplates and various features that provide additional benefit in the context of removable faceplates.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

39.

Systems and Methods for Analyzing and Intelligently Collecting Sensor Data

      
Application Number 18011445
Status Pending
Filing Date 2021-08-31
First Publication Date 2023-09-07
Owner Lam Research Corporation (USA)
Inventor
  • Valcore, Jr., John C.
  • Wong, Travis Joseph
  • Wu, Ying
  • Mudunuri, Sandeep
  • Pust, Bostjan
  • Dash, Shreeram Jyoti

Abstract

A method for controlling a plasma tool is described. The method includes receiving, by a processor, a first set of metric data from a plasma tool. The method further includes analyzing the first set of metric data to determine a first location and a first time window for capturing of a second set of metric data. The method includes providing, by the processor, the first location and the first time window to a data processing system of the plasma tool. The method also includes receiving the second set of metric data captured at the first location and for the first time window. The method includes analyzing the second set of metric data to generate variable data and controlling the plasma tool according to the variable data.

IPC Classes  ?

40.

MAGNETIC FIELD CONTROL SYSTEM

      
Application Number 18013489
Status Pending
Filing Date 2022-05-17
First Publication Date 2023-09-07
Owner Lam Research Corporation (USA)
Inventor
  • Griffin, Alecia Chantalle
  • De La Llera, Anthony
  • Phillips, Peter Bradley
  • Ji, Bing

Abstract

A substrate processing apparatus includes a vacuum chamber with a processing zone for processing a substrate using plasma and at least one magnetic field source configured to generate one or more active magnetic fields through the processing zone. The apparatus also includes a magnetic field sensor configured to detect a signal representing the one or more active magnetic fields, and a controller coupled to the magnetic field sensor, and the at least one magnetic field source. The controller is configured to detect a target value corresponding to at least one characteristic of the one or more active magnetic fields, set an initial current through the at least one magnetic field source, the initial current corresponding to the target value; and adjust a subsequent current through the at least one magnetic field source based on the detected signal representing the one or more active magnetic fields.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01J 37/34 - Gas-filled discharge tubes operating with cathodic sputtering

41.

LAYER UNIFORMITY IMPROVEMENT OF DEPOSITION-INHIBITION-DEPOSITION PROCESSES

      
Application Number US2023014094
Publication Number 2023/167848
Status In Force
Filing Date 2023-02-28
Publication Date 2023-09-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Birru, Krishna
  • Kho, Leonard
  • Lin, Jasmine Yuen-Sen
  • Vyas, Raul
  • Chandrashekar, Anand
  • Clevenger, Jeff

Abstract

Disclosed herein is a process tool, comprising a wafer chuck and a showerhead. In at least one implementation, wafer chuck is coupled to a motor that is operable to vertically displace wafer chuck relative to showerhead. In at least one implementation, a carrier ring is between wafer chuck and showerhead. In at least one implementation, carrier ring comprises an overhang extending over an edge of a wafer on the wafer chuck. In at least one implementation, carrier ring is mechanically coupled to a spindle operable to vertically displace carrier ring relative to wafer chuck.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

42.

SELECTIVE PRECISION ETCHING OF SEMICONDUCTOR MATERIALS

      
Application Number US2023062787
Publication Number 2023/168170
Status In Force
Filing Date 2023-02-17
Publication Date 2023-09-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Gordon, Madeleine Parker
  • Musselwhite, Nathan
  • Kawaguchi, Mark Naoshi

Abstract

Various embodiments described herein relate to methods and apparatus for etching a semiconductor substrate to remove a target material from a surface of the substrate. Generally, the techniques described herein are thermal techniques that do not rely on the use of plasma. In a number of embodiments, a particular gas mixture is provided to the reaction chamber to react with the target material. The gas mixture may include a combination of a halogen source such as hydrogen fluoride (HF), an organic solvent and/or water, an additive, and a carrier gas. A number of different materials may be used for the organic solvent and/or for the additive. The additive may act to form a complex with HF or another halogen source.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C09K 13/08 - Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound

43.

GAP CHARACTERIZATION IN ELECTRODEPOSITION TOOL

      
Application Number US2023063390
Publication Number 2023/168210
Status In Force
Filing Date 2023-02-28
Publication Date 2023-09-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Herr, Jared
  • Hiester, Jacob L.
  • Hosack, Chad M.
  • Graham, Gabriel
  • Quaglio, Marc
  • Rash, Robert
  • Fortner, James
  • Galginaitis, Jason Gordon
  • Bertsch, Kevin

Abstract

Examples are disclosed herein that relate to characterizing a plating gap between an anode structure and a cathode in an electrodeposition tool. One example provides a fixture for characterizing a spacing of a plating gap of an electrodeposition tool. The fixture comprises a substrate holder interface configured to contact a seal of a substrate holder of the electrodeposition tool. The fixture further comprises a protrusion comprising a contact surface configured to contact the anode structure of the electrodeposition tool during a plating gap characterization process. A thickness dimension comprising a distance between a plane of the substrate holder interface and the contact surface of the protrusion corresponds to a preselected plating gap spacing.

IPC Classes  ?

  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 17/06 - Suspending or supporting devices for articles to be coated
  • C25D 21/12 - Process control or regulation

44.

REMOTE PLASMA SOURCE SHOWERHEAD ASSEMBLY WITH ALUMINUM FLUORIDE PLASMA EXPOSED SURFACE

      
Application Number 18011582
Status Pending
Filing Date 2021-06-24
First Publication Date 2023-09-07
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Pape, Eric A.
  • Kon, Shih-Chung
  • Hazarika, Pankaj
  • Xu, Lin

Abstract

A component of a processing chamber in a substrate processing system includes a base material comprising aluminum, the base material having one or more surfaces, a diffusion barrier layer formed on the surfaces of the base material, wherein the diffusion barrier layer includes magnesium and fluorine (F), and a coating formed on the surfaces. The diffusion barrier layer is arranged between the surfaces and the coating and the coating includes fluorine.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides

45.

PULSING RF COILS OF A PLASMA CHAMBER IN REVERSE SYNCHRONIZATION

      
Application Number 18015708
Status Pending
Filing Date 2021-07-01
First Publication Date 2023-09-07
Owner Lam Research Corporation (USA)
Inventor
  • Shoeb, Juline
  • Kamp, Tom A.
  • Paterson, Alexander Miller

Abstract

Systems and methods for pulsing radio frequency (RF) coils are described. One of the methods includes supplying a first RF signal to a first impedance matching circuit coupled to a first RF coil, supplying a second RF signal to a second impedance matching circuit coupled to a second RF coil, and pulsing the first RF signal between a first parameter level and a second parameter level. The method includes pulsing the second RF signal between a third parameter level and a fourth parameter level in reverse synchronization with the pulsing of the first RF signal.

IPC Classes  ?

46.

SYNCHRONIZATION OF RF GENERATORS

      
Application Number 18012212
Status Pending
Filing Date 2021-09-24
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Wu, Ying
  • Drewery, John Stephen
  • Paterson, Alexander Miller
  • Zhou, Xiang
  • Wang, Zhuoxian
  • Kimura, Yoshie

Abstract

Systems and methods for synchronization of radio frequency (RF) generators are described. One of the methods includes receiving, by a first RF generator, a first recipe set, which includes information regarding a first plurality of pulse blocks for operating the first RF generator. The method further includes receiving, by a second RF generator, a second recipe set, which includes information regarding a second plurality of pulse blocks for operating a second RF generator. Upon receiving a digital pulsed signal, the method includes executing the first recipe set and executing the second recipe set. The method further includes outputting a first one of the pulse blocks of the first plurality based on the first recipe set in synchronization with a synchronization signal. The method includes outputting a first one of the pulse blocks of the second plurality based on the second recipe set in synchronization with the synchronization signal.

IPC Classes  ?

47.

AUTOMATED SHOWERHEAD TILT ADJUSTMENT

      
Application Number 18012224
Status Pending
Filing Date 2021-06-10
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Tehrani, Sam Jafarian
  • Cmelak, Bryan Anthony
  • Hiester, Jacob Lee
  • Luo, Bin
  • Wiltse, John

Abstract

In some examples, an automated tilting system is provided for adjusting an orientation of a component in a substrate processing chamber. The automated tilting system comprises at least one tilt adjustment motor arranged to cooperate with the component and be connected to a portion of the component by a coupling. The coupling is configured such that automated rotational motion by the at least one tilt adjustment motor imparts corresponding axial movement, relative to the at least one tilt adjustment motor or a datum structure, to the connected portion of the component to adjust the orientation of the component in the processing chamber.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

48.

SUBSTRATE SUPPORTS WITH MULTILAYER STRUCTURE INCLUDING COUPLED HEATER ZONES WITH LOCAL THERMAL CONTROL

      
Application Number 18013445
Status Pending
Filing Date 2021-08-02
First Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Singh, Harmeet
  • Mitrovic, Slobodan
  • Ehrlich, Darrell
  • Wu, Benny

Abstract

A substrate support assembly for supporting a substrate includes a baseplate, a ceramic plate arranged on the baseplate, and N resistive heaters arranged in X rows and Y columns and coupled to the ceramic plate. X, Y, and N are integers greater than 1, and N is less than or equal to X*Y. Each of the N resistive heaters have a first terminal and a second terminal. The ceramic plate includes Y conductors arranged in a first layer of the ceramic plate, and X conductors arranged in a second layer of the ceramic plate. The first terminals of each resistive heater in one of the X rows are directly connected to the Y conductors, respectively, by first vias. Second terminals of each resistive heater in the one of the X rows are directly connected to one of the X conductors by second vias.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H05B 3/28 - Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor embedded in insulating material

49.

RF ASSEMBLY FOR SUBSTRATE PROCESSING SYSTEMS

      
Application Number US2023012470
Publication Number 2023/163854
Status In Force
Filing Date 2023-02-07
Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Vasquez, Miguel Benjamin
  • French, David

Abstract

An inductor strap for a radio frequency matching circuit of a substrate processing system comprises a first end and a second end each comprising a respective connector tab configured to connect to a terminal of a respective capacitor, an inductor coil disposed between the first end and the second end, and an intermediate portion disposed between the inductor coil and one of the first end and the second end. The intermediate portion comprises a planar connection plate configured to couple the inductor strap to a surface of a radio frequency enclosure that houses the radio frequency matching circuit.

IPC Classes  ?

  • H01F 27/28 - Coils; Windings; Conductive connections
  • H01J 37/32 - Gas-filled discharge tubes
  • H03H 7/38 - Impedance-matching networks
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

50.

LOW RESISTANCE MOLYBDENUM DEPOSITION FOR LOGIC SOURCE/DRAIN CONTACTS

      
Application Number US2023062877
Publication Number 2023/164413
Status In Force
Filing Date 2023-02-17
Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Hsieh, Yao-Tsung
  • Griffiths, Matthew Bertram Edward
  • Na, Jeong-Seok
  • Lai, Chiukin Steven
  • Mandia, David Joseph

Abstract

Provided is an efficient method for filling a semiconductor substrate conformal layer lined feature utilizing a metal precursor to selectively deposit metal at the bottom of the feature and to etch the conformal layer lining from feature sidewalls.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material

51.

SYSTEM AND METHOD FOR PERFORMING 3D PHOTORESIST PROFILE GENERATION

      
Application Number US2023013761
Publication Number 2023/164090
Status In Force
Filing Date 2023-02-24
Publication Date 2023-08-31
Owner COVENTOR, INC. (USA)
Inventor
  • Wang, Qing, Peng
  • Bao, Rui
  • Li, Cheng
  • Chen, Yu, De
  • Huang, Shi-Hao
  • Ervin, Joseph

Abstract

Systems and methods for performing 3D photoresist profile generation for a semiconductor device fabrication environment are discussed. The methods comprise receiving in a virtual fabrication environment a top contour mask and a bottom contour mask, creating a loading map using a subset of density information extracted from the top contour mask and the bottom contour mask, performing an etch operation using the loading map to generate the 3D photoresist profile, and outputting a result of the etch operation.

IPC Classes  ?

  • G03F 7/20 - Exposure; Apparatus therefor
  • G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
  • G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

52.

ATOMIC LAYER ETCHING OF A SEMICONDUCTOR, A METAL, OR A METAL OXIDE WITH SELECTIVITY TO A DIELECTRIC

      
Application Number 18002788
Status Pending
Filing Date 2021-08-20
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Lill, Thorsten Bernd
  • Fischer, Andreas
  • Routzahn, Aaron Lynn

Abstract

Semiconductor processing methods and apparatuses are provided. Some methods include providing a substrate to a processing chamber, the substrate having a semiconductor portion and a dielectric portion, modifying the semiconductor portion of the substrate selective to the dielectric portion of the substrate by flowing a first process gas comprising a first halogen species onto the substrate and providing a first activation energy to cause the first halogen species to preferentially adsorb on the semiconductor portion relative to the dielectric portion to form a first halogenated semiconductor, and removing the first halogenated semiconductor by flowing a second process gas comprising a second halogen species onto the substrate and providing a second activation energy, without providing a plasma, to cause the second halogen species to react with the first halogenated semiconductor and cause the first halogenated semiconductor to desorb from the substrate.

IPC Classes  ?

53.

ETCHING OF INDIUM GALLIUM ZINC OXIDE

      
Application Number 18003257
Status Pending
Filing Date 2022-03-15
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Routzahn, Aaron Lynn
  • Fischer, Andreas
  • Lill, Thorsten Bernd

Abstract

Indium gallium zinc oxide can be etched by providing a wafer having a layer of indium gallium zinc oxide to a processing chamber, heating the wafer to a first temperature, flowing a first chemical species comprising a fluoride to create a layer of indium gallium zinc oxyfluoride, and removing the layer of indium gallium zinc oxyfluoride by flowing a second chemical species comprising an alkyl aluminum halide, an aluminum alkalide, an organoaluminium compound, a diketone, silicon halide, silane, halogenated silane, or alkyl silicon halide.

IPC Classes  ?

  • H01L 21/465 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

54.

PEDESTAL THERMAL PROFILE TUNING USING MULTIPLE HEATED ZONES AND THERMAL VOIDS

      
Application Number 18008273
Status Pending
Filing Date 2021-06-04
First Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lind, Gary B.
  • Mahadeva, Alok

Abstract

A substrate support includes a body and a thermal void. The body is configured to support a substrate during processing of the substrate. The body includes plates including a top plate, a first intermediate plate, a second intermediate plate and a bottom plate. The plates are arranged to form a stack. The first intermediate plate is disposed on the second intermediate plate. The thermal void is defined by an upper surface of the second intermediate plate and at least one of a lower surface of the first intermediate plate or a lower surface of the top plate. The thermal void is annular-shaped.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

55.

LOW FREQUENCY RF GENERATOR AND ASSOCIATED ELECTROSTATIC CHUCK

      
Application Number 18011062
Status Pending
Filing Date 2021-11-05
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Marakhtanov, Alexei M.
  • Kozakevich, Felix Leib
  • Ji, Bing
  • Bhowmick, Ranadeep
  • Holland, John Patrick
  • Matyushkin, Alexander

Abstract

A system having the low frequency RF generator is described. The low frequency RF has an operating frequency range between 10 kilohertz (kHz) and 330 kHz. The low frequency RF generator generates an RF signal. The system further includes an impedance matching circuit coupled to the low frequency RF generator for receiving the RF signal. The impedance matching circuit modifies an impedance of the RF signal to output a modified RF signal. The system includes a plasma chamber coupled to the RF generator for receiving the modified RF signal. The plasma chamber includes a chuck having a dielectric layer and a base metal layer. The dielectric layer is located on top of the base metal layer. The dielectric layer has a bottom surface, and the base metal layer has a top surface. The base metal layer has a porous plug and the bottom surface of the dielectric layer has a portion that is in contact with the porous plug.

IPC Classes  ?

56.

CONTROLLING TEMPERATURE PROFILES OF PLASMA CHAMBER COMPONENTS USING STRESS ANALYSIS

      
Application Number 18013475
Status Pending
Filing Date 2021-08-11
First Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor Drewery, John

Abstract

A system for estimating stress on a component of a processing chamber during a process includes a plurality of sensors configured to sense temperatures at a plurality of locations of the component during the process and a controller a controller configured to interpolate the temperatures to estimate a temperature distribution across the component and to estimate the stress on the component during the process. A method of estimating stress on a component of a processing chamber during a process includes sensing temperatures at a plurality of locations of the component during the process, interpolating the temperatures to estimate a temperature distribution across the component, and estimating the stress on the component during the process.

IPC Classes  ?

57.

ADJUSTABLE GEOMETRY TRIM COIL

      
Application Number 18013477
Status Pending
Filing Date 2021-06-24
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor Bailey, Iii, Andrew D.

Abstract

Methods, systems, apparatuses, and computer programs are presented for controlling etch rate and plasma uniformity using magnetic fields. A substrate processing apparatus includes a vacuum chamber including a processing zone for processing a substrate. The apparatus further includes a magnetic field sensor configured to detect a signal representing a residual magnetic field associated with the vacuum chamber. At least one magnetic field source is configured to generate one or more supplemental magnetic fields through the processing zone of the vacuum chamber. A magnetic field controller is coupled to the magnetic field sensor and the at least one magnetic field source. The magnetic field controller is configured to adjust at least one characteristic of the one or more supplemental magnetic fields, causing the one or more supplemental magnetic fields to reduce the residual magnetic field to a pre-determined value.

IPC Classes  ?

58.

SOLENOID BANK WITH STANDBY SOLENOID VALVES FOR CONTROLLING PNEUMATIC VALVES OF A SUBSTRATE PROCESSING SYSTEM

      
Application Number 18020302
Status Pending
Filing Date 2021-08-17
First Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Panchangam, Swajeeth Pilot
  • Gulabal, Vinayakaraddy
  • Saghi, Yeshwanth
  • Gowdaru, Keerthi

Abstract

A fluid control system for a substrate processing system includes (M + N) inlets configured to fluidly connect to (M) solenoid valves and (N) standby solenoid valves, respectively, where (M) and (N) are integers greater than zero. (M) outputs are configured to be fluidly connected to (M) pneumatic valves. A valve switching system is configured to selectively block (1) to (N) of the M inlets corresponding to (1) to (N) failed ones of (M) solenoid valves, respectively, and supply fluid from (1) to (N) of the (N) standby solenoid valves to (1) to (N) of the (M) outputs corresponding to the (1) to (N) failed ones of (M) solenoid valves, respectively.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

59.

COOLING FOR A PLASMA-BASED REACTOR

      
Application Number 18142570
Status Pending
Filing Date 2023-05-02
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Drewery, John Stephen
  • Benjamin, Neil Martin Paul

Abstract

In one embodiment, the disclosed apparatus is a heat-pipe cooling system that includes a conical structure having an upper portion that is configured to be formed above a dielectric window with the conical structure being configured to condense vapor from a heat-transfer fluid placed or incorporated within a volume formed between the dielectric window and the conical structure. At least one cooling coil is formed on an exterior portion of the conical structure. Other apparatuses and systems are disclosed.

IPC Classes  ?

60.

VACUUM-INTEGRATED HARDMASK PROCESSES AND APPARATUS

      
Application Number 18297989
Status Pending
Filing Date 2023-04-10
First Publication Date 2023-08-31
Owner Lam Research Corporation (USA)
Inventor
  • Marks, Jeffrey
  • Antonelli, George Andrew
  • Gottscho, Richard A.
  • Hausmann, Dennis M.
  • Lavoie, Adrien
  • Knisley, Thomas Joseph
  • Reddy, Sirish K.
  • Varadarajan, Bhadri N.
  • Kolics, Artur

Abstract

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

IPC Classes  ?

  • G03F 1/76 - Patterning of masks by imaging
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/18 - Pretreatment of the material to be coated
  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F 7/26 - Processing photosensitive materials; Apparatus therefor
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 18/14 - Decomposition by irradiation, e.g. photolysis, particle radiation

61.

WAFER BOW COMPENSATION BY PATTERNED UV CURE

      
Application Number US2023012800
Publication Number 2023/163861
Status In Force
Filing Date 2023-02-10
Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Lei, Tong
  • Chi, Yushan
  • Yu, Jiang

Abstract

UV light may be directed through a patterned window to cause selective UV exposure of certain areas of a substrate. A stress-tunable film deposited on the substrate may undergo localized stress changes from selective UV exposure. Localized stress changes in the stress-tunable film may mitigate wafer bowing in the substrate. The patterned window may be designed with UV-transparent regions and UV-non-transparent regions to facilitate targeted UV exposure of the stress-tunable film. In some implementations, the patterned window may include a metal coating, a ceramic cover, or a metal cover for selective UV exposure. In some implementations, the patterned window may further include transition regions that permit partial transmission of UV light to limit stress changes in corresponding areas of the stress-tunable film.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting

62.

THERMAL FILM DEPOSITION

      
Application Number US2023013525
Publication Number 2023/163950
Status In Force
Filing Date 2023-02-21
Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Varnell, Jason Alexander
  • Austin, Dustin Zachary
  • Ramasagaram, Praneeth
  • Bart J., Van Schravendijk
  • Petraglia, Jennifer Leigh
  • Agnew, Douglas Walter
  • Gupta, Awnish
  • Liu, Pei-Chi
  • Agarwal, Pulkit

Abstract

Methods and apparatuses for depositing superconformal dielectric material using thermal chemical vapor deposition-enhanced atomic layer deposition are provided. Methods and apparatuses for depositing material using modified atomic layer deposition integrating pyrolyzing a deposition precursor such as an aminosilane during dose to form a pyrolyzed layer, optional inert gas plasma for densification, and an oxygen-containing or nitrogen-containing plasma to convert the pyrolyzed layer into an oxygen-containing or nitrogen-containing material.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/56 - After-treatment

63.

ATOMIC LAYER ETCHING USING AN INHIBITOR

      
Application Number US2023062150
Publication Number 2023/164367
Status In Force
Filing Date 2023-02-07
Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Routzahn, Aaron, Lynn
  • Fischer, Andreas
  • Lill, Thorsten

Abstract

Examples are provided related to using an inhibitor in an atomic layer etching process. One example provides a method for performing atomic layer etching of a substrate. The method comprises performing a plurality of etch cycles. At least one process cycle of the plurality of etch cycles comprises exposing the substrate to a modification chemical in a modification step, exposing the substrate to an inhibitor chemical, and exposing the substrate to a volatilization chemical in a removal step.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

64.

SENSORS FOR SEMICONDUCTOR PROCESSING TOOLS

      
Application Number US2023062893
Publication Number 2023/164415
Status In Force
Filing Date 2023-02-20
Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Patil, Ravikumar
  • Gowdaru, Keerthi
  • Patil, Pawan Murlidhar
  • Leeser, Karl Frederick

Abstract

Described herein is a pedestal assembly comprising a platen and a sensor support plate below the platen. In at least one implementation, sensor support plate comprises a sensor compartment and a waveguide temperature sensor within the sensor compartment. In at least one implementation, waveguide temperature sensor comprises a temperature sensor comprising a first reflector structure and a second reflector structure. In at least one implementation, first reflector structure and second reflector structure are separated by a gauge length.

IPC Classes  ?

  • G01K 11/22 - Measuring temperature based on physical or chemical changes not covered by group , , , or using measurement of acoustic effects
  • G01K 11/32 - Measuring temperature based on physical or chemical changes not covered by group , , , or using changes in transmittance, scattering or luminescence in optical fibres
  • G01K 1/08 - Protective devices, e.g. casings
  • G01K 1/14 - Supports; Fastening devices; Arrangements for mounting thermometers in particular locations

65.

SURFACE INHIBITION ATOMIC LAYER DEPOSITION

      
Application Number US2023063389
Publication Number 2023/164717
Status In Force
Filing Date 2023-02-28
Publication Date 2023-08-31
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Zhang, Tao
  • Agarwal, Pulkit
  • Abel, Joseph R.
  • Bhandari, Shiva Sharan
  • Petraglia, Jennifer Leigh

Abstract

Atomic layer deposition (ALD) of dielectric material in gaps that facilitates void-free bottom-up gap fill can involve flowing a reaction inhibitor during the ALD process. In some embodiments, the reaction inhibitor is flowed during at least part of a plasma operation of a plasma-enhanced ALD (PEALD) process.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/32 - Carbides
  • C23C 16/34 - Nitrides
  • C23C 16/40 - Oxides

66.

TREOS

      
Serial Number 98150644
Status Pending
Filing Date 2023-08-25
Owner Lam Research Corporation ()
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Computer hardware and recorded software systems for the installation, operation, maintenance, and repair of semiconductor manufacturing machines, semiconductor substrates manufacturing machines, semiconductor wafer processing machines; Electronic components, namely, electrodes, electrostatic chucks, pedestals with signal transmitter, o-rings with readable circuitry antenna or signal transmitter, edge rings with readable circuitry antenna or signal transmitter, mechanisms for sealing with readable circuitry antenna or signal transmitter, electronic calibrator, electric actuators, electric measurement sensors, recorded operating software for operating semiconductor manufacturing machines, electrical controllers, transducers in the nature of electrical transducers and electro-optic transducers, electronic signal transmitters, electronic signal receivers, coaxial cables, fiber optic cables, Pressure and optical sensors, showerhead having electronic sensors and signal transmitters, pumps with electronic sensors and signal transmitters, vacuum gauges with electronic sensors and signal transmitters, pipes with electronic sensors and signal transmitters, tubes for chemicals with sensors or electronic circuitry or signal transmitter, feed lines with sensors or electronic circuitry or signal transmitter, fans with electronic sensors and signal transmitters, power supplies electrical, power cables, doors with electronic sensors and signal transmitters, windows with electronic sensors and signal transmitters, and chamber walls with electronic sensors and signal transmitters all for semiconductor manufacturing machines; Electronic components, namely, electrodes, electrostatic chucks, pedestals with signal transmitter, o-rings with readable circuitry antenna or signal transmitter, edge rings with readable circuitry antenna or signal transmitter, mechanisms for sealing with readable circuitry antenna or signal transmitter, electronic calibrator, electric actuators, electric measurement sensors, recorded operating software for operating semiconductor substrates manufacturing machines, electrical controllers, transducers in the nature of electrical transducers and electro-optic transducers, electronic signal transmitters, electronic signal receivers, coaxial cables, fiber optic cables, pressure and optical sensors, showerhead having electronic sensors and signal transmitters, pumps with electronic sensors and signal transmitters, vacuum gauges with electronic sensors and signal transmitters, pipes with electronic sensors and signal transmitters, tubes for chemicals with sensors or electronic circuitry or signal transmitter, feed lines with sensors or electronic circuitry or signal transmitter, fans with electronic sensors and signal transmitters, power supplies electrical, power cables, doors with electronic sensors and signal transmitters, windows with electronic sensors and signal transmitters, and chamber walls with electronic sensors and signal transmitters all for semiconductor substrates manufacturing machines; Electronic components, namely, electrodes, electrostatic chucks, pedestals with signal transmitter, o-rings with readable circuitry antenna or signal transmitter, edge rings with readable circuitry antenna or signal transmitter, mechanisms for sealing with readable circuitry antenna or signal transmitter, electronic calibrator, electric actuators, electric measurement sensors, recorded operating software for operating semiconductor wafer processing machines, electrical controllers, transducers in the nature of electrical transducers and electro-optic transducers, electronic signal transmitters, electronic signal receivers, coaxial cables, fiber optic cables, pressure and optical sensors, showerhead having electronic sensors and signal transmitters, pumps with electronic sensors and signal transmitters, vacuum gauges with electronic sensors and signal transmitters, pipes with electronic sensors and signal transmitters, tubes for chemicals with sensors or electronic circuitry or signal transmitter, feed lines with sensors or electronic circuitry or signal transmitter, fans with electronic sensors and signal transmitters, power supplies electrical, power cables, doors with electronic sensors and signal transmitters, windows with electronic sensors and signal transmitters, and chamber walls with electronic sensors and signal transmitters all for semiconductor wafer processing machines; Electronic components, namely, electrodes, electrostatic chucks, pedestals with signal transmitter, o-rings with readable circuitry antenna or signal transmitter, edge rings with readable circuitry antenna or signal transmitter, mechanisms for sealing with readable circuitry antenna or signal transmitter, electronic calibrator, electric actuators, electric measurement sensors, recorded operating software for operating semiconductor wafer processing equipment, electrical controllers, transducers in the nature of electrical transducers and electro-optic transducers, electronic signal transmitters, electronic signal receivers, coaxial cables, fiber optic cables, pressure and optical sensors, showerhead having electronic sensors and signal transmitters, pumps with electronic sensors and signal transmitters, vacuum gauges with electronic sensors and signal transmitters, pipes with electronic sensors and signal transmitters, tubes for chemicals with sensors or electronic circuitry or signal transmitter, feed lines with sensors or electronic circuitry or signal transmitter, fans with electronic sensors and signal transmitters, power supplies electrical, power cables, doors with electronic sensors and signal transmitters, windows with electronic sensors and signal transmitters, and chamber walls with electronic sensors and signal transmitters all for semiconductor wafer processing equipment; Downloadable interactive multimedia computer program for the installation, operation, maintenance, and repair of semiconductor manufacturing machines, semiconductor substrates manufacturing machines, semiconductor wafer processing machines; Measurement apparatus and instruments, namely, pressure measuring apparatus and distance measuring apparatus for use in semiconductor manufacturing, semiconductor substrates manufacturing, and semiconductor wafer processing; Tools and equipment, namely, namely, electrodes, electrostatic chucks, pedestals with signal transmitter, o-rings with readable circuitry antenna or signal transmitter, edge rings with readable circuitry antenna or signal transmitter, mechanisms for sealing with readable circuitry antenna or signal transmitter, electronic calibrator, electric actuators, electric measurement sensors, recorded operating software for operating semiconductor manufacturing machines, electrical controllers, transducers in the nature of electrical transducers and electro-optic transducers, electronic signal transmitters, electronic signal receivers, coaxial cables, fiber optic cables, Pressure and optical sensors, showerhead having electronic sensors and signal transmitters, pumps with electronic sensors and signal transmitters, vacuum gauges with electronic sensors and signal transmitters, pipes with electronic sensors and signal transmitters, tubes for chemicals with sensors or electronic circuitry or signal transmitter, feed lines with sensors or electronic circuitry or signal transmitter, fans with electronic sensors and signal transmitters, power supplies electrical, power cables, doors with electronic sensors and signal transmitters, windows with electronic sensors and signal transmitters, and chamber walls with electronic sensors and signal transmitters all for semiconductor manufacturing; Tools and equipment, namely, namely, electrodes, electrostatic chucks, pedestals with signal transmitter, o-rings with readable circuitry antenna or signal transmitter, edge rings with readable circuitry antenna or signal transmitter, mechanisms for sealing with readable circuitry antenna or signal transmitter, electronic calibrator, electric actuators, electric measurement sensors, recorded operating software for operating semiconductor manufacturing machines, electrical controllers, transducers in the nature of electrical transducers and electro-optic transducers, electronic signal transmitters, electronic signal receivers, coaxial cables, fiber optic cables, Pressure and optical sensors, showerhead having electronic sensors and signal transmitters, pumps with electronic sensors and signal transmitters, vacuum gauges with electronic sensors and signal transmitters, pipes with electronic sensors and signal transmitters, tubes for chemicals with sensors or electronic circuitry or signal transmitter, feed lines with sensors or electronic circuitry or signal transmitter, fans with electronic sensors and signal transmitters, power supplies electrical, power cables, doors with electronic sensors and signal transmitters, windows with electronic sensors and signal transmitters, and chamber walls with electronic sensors and signal transmitters all for semiconductor wafer processing

67.

TREOS

      
Serial Number 98150653
Status Pending
Filing Date 2023-08-25
Owner Lam Research Corporation ()
NICE Classes  ? 07 - Machines and machine tools

Goods & Services

Semiconductor manufacturing machines; Semiconductor substrates manufacturing machines; Semiconductor wafer processing equipment; Semiconductor wafer processing machines; and replacement parts and fittings for all of the aforementioned goods

68.

METAL CHELATORS FOR DEVELOPMENT OF METAL-CONTAINING PHOTORESIST

      
Application Number 18005571
Status Pending
Filing Date 2021-07-16
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Hansen, Eric Calvin
  • Weidman, Timothy William
  • Wu, Chenghao
  • Gu, Kevin Li
  • Dictus, Dries

Abstract

The present disclosure relates to use of a metal chelator to treat an exposed photoresist film. In particular embodiments, the metal chelator is employed to remove an interfacial area that is disposed between exposed and unexposed areas or disposed within an exposed area, thereby enhancing patterning quality.

IPC Classes  ?

  • G03F 7/32 - Liquid compositions therefor, e.g. developers
  • G03F 7/20 - Exposure; Apparatus therefor
  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • G03F 7/38 - Treatment before imagewise removal, e.g. prebaking

69.

SYSTEMS AND METHODS FOR CENTRAL FREQUENCY TUNING

      
Application Number US2022053727
Publication Number 2023/158490
Status In Force
Filing Date 2022-12-21
Publication Date 2023-08-24
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Bhowmick, Ranadeep
  • Holland, John, P.

Abstract

Systems and methods for central frequency tuning are described. One of the methods includes receiving a voltage signal from an output of a match coupled to a low frequency (LF) radio frequency (RF) generator and a high frequency (HF) RF generator. The method further includes dividing the voltage signal into a plurality of bins for each cycle of an LF RF signal generated by the LF RF generator. The method also includes identifying a first bin from the plurality of bins during which a zero crossing occurs, accessing measurements of a parameter for occurrences of a pre-determined number of the plurality of bins, and calculating a frequency of operation of the HF RF generator for the first bin based on the measurements of the parameter. The method includes controlling the HF RF generator to operate at the frequency of operation during an occurrence of the first bin.

IPC Classes  ?

70.

HIGH PRESSURE INERT OXIDATION AND IN-SITU ANNEALING PROCESS TO IMPROVE FILM SEAM QUALITY AND WER

      
Application Number US2023062571
Publication Number 2023/159012
Status In Force
Filing Date 2023-02-14
Publication Date 2023-08-24
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Jeon, Eli
  • Agnew, Douglas Walter
  • Bhandari, Shiva Sharan
  • Curtin, Ian John
  • Abel, Joseph R.
  • Varnell, Jason Alexander
  • Barnett, Cody
  • Iadanza, Christopher Nicholas
  • Austin, Dustin Zachary

Abstract

Methods of filling a gap with a dielectric material including using an inhibition plasma during deposition. The inhibition plasma increases a nucleation barrier of the deposited film. The inhibition plasma selectively interacts near the top of the feature, inhibiting deposition at the top of the feature compared to the bottom of the feature, enhancing bottom-up fill. A process chamber may have multiple pressure switches to enable a process after deposition at a higher pressure than the pressure during deposition.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

71.

SELECTIVE SILICON TRIM BY THERMAL ETCHING

      
Application Number 18004051
Status Pending
Filing Date 2022-01-21
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Musselwhite, Nathan
  • Zhu, Ji
  • Melaet, Gerome Michel Dominique
  • Kawaguchi, Mark Naoshi

Abstract

Methods and apparatuses for precise trimming of silicon-containing materials are provided. Methods involve oxidizing silicon-containing materials and thermally removing the oxidized silicon-containing materials at particular temperatures for a self-limiting etch process. Methods also involve a surface reaction limited process using a halogen source and modulated temperature and exposure duration to etch small amounts of silicon-containing materials. Apparatuses are capable of flowing multiple oxidizers at particular temperature ranges to precisely etch substrates.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/321 - After-treatment

72.

PHOTORESISTS FROM SN(II) PRECURSORS

      
Application Number 18005594
Status Pending
Filing Date 2021-07-16
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Hansen, Eric Calvin
  • Wu, Chenghao
  • Weidman, Timothy William

Abstract

The present disclosure relates to a film formed with an organotin(II) compound, as well as methods for forming and employing such films. The film can be employed as a photopatternable film or a radiation-sensitive film. In non-limiting embodiments, the radiation can include extreme ultraviolet (EUV) or deep ultraviolet (DUV) radiation

IPC Classes  ?

73.

IN-SITU HYDROCARBON-BASED LAYER FOR NON-CONFORMAL PASSIVATION OF PARTIALLY ETCHED STRUCTURES

      
Application Number 18012194
Status Pending
Filing Date 2022-06-13
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Hudson, Eric
  • Reddy, Kapu Sirish
  • Puthenkovilakam, Ragesh
  • Deshmukh, Shashank
  • Kumar, Prabhat
  • Gopaladasu, Prabhakara
  • Yun, Seokmin
  • Zhang, Xin

Abstract

A method for selectively etching at least one feature in a first region with respect to a second region of a stack is provided. The first region is selectively etched with respect to the second region to form at least one partial feature in the first region, the at least one partial feature having a depth with respect to a surface of the second region. An in-situ a fluorine-free, non-conformal, carbon-containing mask is deposited over the first region and the second region, wherein the carbon-containing mask is selectively deposited on the second region at a second thickness with respect to the first region at a first thickness, the second thickness being greater than the first thickness. The first region is further etched in-situ to etch the at least one partial feature and wherein the carbon-containing mask acts as an etch mask for the second region.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

74.

VACUUM-INTEGRATED HARDMASK PROCESSES AND APPARATUS

      
Application Number 18298003
Status Pending
Filing Date 2023-04-10
First Publication Date 2023-08-24
Owner Lam Research Corporation (USA)
Inventor
  • Marks, Jeffrey
  • Antonelli, George Andrew
  • Gottscho, Richard A.
  • Hausmann, Dennis M.
  • Lavoie, Adrien
  • Knisley, Thomas Joseph
  • Reddy, Sirish K.
  • Varadarajan, Bhadri N.
  • Kolics, Artur

Abstract

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

IPC Classes  ?

  • G03F 1/76 - Patterning of masks by imaging
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/18 - Pretreatment of the material to be coated
  • G03F 7/004 - Photosensitive materials
  • G03F 7/16 - Coating processes; Apparatus therefor
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F 7/26 - Processing photosensitive materials; Apparatus therefor
  • G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 18/14 - Decomposition by irradiation, e.g. photolysis, particle radiation

75.

SYSTEMS AND METHODS FOR REDUCING VARIABILITY IN FEATURES OF A SUBSTRATE

      
Application Number US2022053888
Publication Number 2023/158491
Status In Force
Filing Date 2022-12-22
Publication Date 2023-08-24
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Jayanti, Sriharsha
  • Delgadino, Gerardo
  • Wong, Merrett

Abstract

A method for reducing variability between features of a substrate is described. The method includes generating, by a single radio frequency (RF) generator, an RF signal. The method further includes modifying, by the single RF generator, the RF signal to alternate among three states or four states for a time period.

IPC Classes  ?

76.

INTEGRATION OF VAPOR DEPOSITION PROCESS INTO PLASMA ETCH REACTOR

      
Application Number 18003139
Status Pending
Filing Date 2021-10-22
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Hudson, Eric A.
  • Serino, Andrew Clark
  • Nicholson, Thad
  • Chandrasekharan, Ramesh
  • Schoepp, Alan M.

Abstract

Various embodiments herein relate to methods and systems for integrating a vapor deposition process and an etch process in a single reactor. The vapor deposition process involves delivery of at least one deposition vapor in the absence of plasma. The etch process is a plasma etch process. Various features may be combined as desired to promote high quality deposition and etching results.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/56 - After-treatment
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

77.

PLASMA DISCHARGE UNIFORMITY CONTROL USING MAGNETIC FIELDS

      
Application Number 18013480
Status Pending
Filing Date 2021-08-30
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Panagopoulos, Theodoros
  • Marakhtanov, Alexei M.
  • Ji, Bing
  • De La Llera, Anthony
  • Holland, John P.
  • Paeng, Dong Woo

Abstract

Methods, systems, apparatuses, and computer programs are presented for controlling plasma discharge uniformity using magnetic fields. A substrate processing apparatus includes a vacuum chamber with a processing zone for processing a substrate. The apparatus further includes a magnetic field sensor to detect a first signal representing an axial magnetic field and a second signal representing a radial magnetic field associated with the vacuum chamber. The apparatus includes at least two magnetic field sources to generate an axial supplemental magnetic field and a radial supplemental magnetic field through the processing zone of the vacuum chamber. The apparatus includes a magnetic field controller coupled to the magnetic field sensor and the at least two magnetic field sources. The magnetic field controller adjusts at least one characteristic of one or more of the axial supplemental magnetic field and the radial supplemental magnetic field based on the first signal and the second signal.

IPC Classes  ?

  • H01J 37/34 - Gas-filled discharge tubes operating with cathodic sputtering
  • H01L 21/311 - Etching the insulating layers

78.

WAFER EDGE TILT AND ETCH RATE UNIFORMITY

      
Application Number US2022053427
Publication Number 2023/154114
Status In Force
Filing Date 2022-12-19
Publication Date 2023-08-17
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Mankidy, Pratik
  • Kim, Jaewon

Abstract

An edge ring for use in a plasma chamber includes a first pair of edge ring segments with each one of the first pair of edge ring segments having a first thickness and a second pair of edge ring segments with each one of the second pair of edge ring segments having a second thickness. Each of the first pair of edge ring segments is oriented adjacent to each of the second pair of edge ring segments and each of the second pair of edge ring segments is oriented adjacent to each of the first pair of edge ring segments.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

79.

ETCH UNIFORMITY IMPROVEMENT IN RADICAL ETCH USING CONFINEMENT RING

      
Application Number US2022053429
Publication Number 2023/154115
Status In Force
Filing Date 2022-12-19
Publication Date 2023-08-17
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Fischer, Andreas
  • Amburose, Gnanamani
  • Monbeig, Julien

Abstract

A confinement ring for use in a process chamber includes a tubular extension that is configured to surrounds a process region in the process chamber. An upper end of the tubular extension is configured to connect to a showerhead of the process chamber and a lower end that is configured to extend into the process region and proximate to an edge ring that surrounds a wafer received within the process region. A foot extension has an inner end that joins to the lower end of the tubular extension and extends outwardly from the process region to the outer end. The foot extension provides an annular surface that is configured to form a gap with a top surface of the edge ring.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

80.

METHOD FOR DEPOSITING HIGHLY DOPED ALUMINUM NITRIDE PIEZOELECTRIC MATERIAL

      
Application Number US2023061478
Publication Number 2023/154631
Status In Force
Filing Date 2023-01-27
Publication Date 2023-08-17
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Hopman, Willem Cornelis Lambert
  • Dekkers, Jan Matthijn
  • Heuver, Jeroen Aaldert

Abstract

The invention relates to a method for manufacturing a doped wurtzite aluminum nitride piezoelectric thin film material, which method comprises the steps of: providing a deposition device, such as a pulsed lased deposition device or a physical vapor deposition device, with a target and a substrate, wherein the target material is a doped aluminum nitride composite, wherein the doping element is a rare earth element, preferably scandium; depositing a first layer of the target material on the substrate by operating the deposition device, wherein the kinetic energy of the plasma particles being deposited is above a first threshold value; depositing a second layer of the target material on top of the first layer by operating the deposition device, wherein the kinetic energy of the plasma particles being deposited is below a second threshold value and wherein the first threshold value is larger than the second threshold value.

IPC Classes  ?

  • C23C 14/06 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
  • C23C 28/04 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and only coatings of inorganic non-metallic material

81.

EVALUATION OF PLASMA UNIFORMITY USING COMPUTER VISION

      
Application Number US2023061947
Publication Number 2023/154663
Status In Force
Filing Date 2023-02-03
Publication Date 2023-08-17
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Sawlani, Kapil
  • Franzen, Paul
  • Savchak, Oksana
  • Danek, Michal
  • Leeser, Karl Frederick
  • Tobin, Samuel

Abstract

Various embodiments herein relate to apparatuses and methods for evaluating plasma uniformity using computer vision. In some embodiments, a method comprises obtaining signals from one or more camera sensors optically coupled to one or more optical access apertures of a device fabrication process chamber during performance of a plasma-based operation. The method may comprise determining, from the signals, plasma characteristics during the performance of the plasma-based operation. The method may comprise determining, from the plasma characteristics, a non-uniformity of one or more wafer characteristics of a wafer undergoing the plasma-based operation.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

82.

METHODS TO IMPROVE WAFER WETTABILITY FOR PLATING - ENHANCEMENT THROUGH SENSORS AND CONTROL ALGORITHMS

      
Application Number 17998255
Status Pending
Filing Date 2021-05-03
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Hur, Hyungjun
  • Tilak, Pooja
  • Ghongadi, Shantinath
  • Sweeney, Cian

Abstract

Various embodiments include methods and apparatuses to moisturize a substrate prior to an electrochemical deposition process. In one embodiment, a method to control substrate wettability includes placing a substrate in a humidification environment, controlling the humidification environment to moisturize a surface of the substrate; and placing the substrate into a plating cell. Other methods and systems are disclosed.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C25D 7/12 - Semiconductors
  • C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
  • C25D 21/12 - Process control or regulation

83.

METAL OXIDE DIFFUSION BARRIERS

      
Application Number 17999442
Status Pending
Filing Date 2021-06-25
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Brogan, Lee J.
  • Van Cleemput, Patrick A.
  • Huie, Matthew Martin
  • Blakeney, Kyle Jordan
  • Liu, Yi Hua

Abstract

Various embodiments herein relate to methods, apparatus, and systems for forming an interconnect structure, or a portion thereof, on a substrate. In one example, the method includes receiving the substrate in a processing chamber, the substrate having dielectric material exposed within recessed features formed therein; exposing the substrate to plasma to thereby modify a top surface of the dielectric material; forming a metal oxide barrier layer on the modified top surface of the dielectric material, wherein the metal oxide barrier layer is formed through atomic layer deposition and/or chemical vapor deposition. In certain implementations, one or more additional step may be taken to improve processing results, for example to promote nucleation and/or adhesion of relevant layers.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • C23C 16/34 - Nitrides
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01J 37/32 - Gas-filled discharge tubes

84.

CONCENTRATION CONTROL USING A BUBBLER

      
Application Number 18001587
Status Pending
Filing Date 2021-07-21
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Chandrasekharan, Ramesh
  • Srinivasan, Easwar
  • Pohl, Erica Sakura Strandberg
  • Borth, Andrew
  • Altecor, Aleksey V.

Abstract

The present disclosure relates, in part, to an apparatus for controlling the concentration of a component within a gas mixture. In particular embodiments, the component is a vaporized liquid component, such as a vaporized stabilizer or a vaporized precursor. Also described are systems thereof and methods for such control.

IPC Classes  ?

  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C23C 16/26 - Deposition of carbon only
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
  • C23C 16/52 - Controlling or regulating the coating process

85.

CHEMISTRY FOR HIGH ASPECT RATIO ETCH FOR 3D-NAND

      
Application Number 18003146
Status Pending
Filing Date 2022-05-24
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Dole, Nikhil
  • Yanagawa, Takumi

Abstract

Various embodiments herein relate to methods and apparatus for etching a memory hole in a stack of materials on a substrate. In some cases, the stack includes alternating layers of silicon oxide and silicon nitride. In other cases, the stack includes alternating layers of silicon oxide and polysilicon. In either case, three or more sets of processing conditions are used to etch the substrate. Various processing conditions such as the composition of a reactant mixture, pressure, substrate temperature, and/or plasma generation conditions are varied between the three or more sets of processing conditions to produce high quality etching results with high selectivity, a highly vertical etch profile, and a low degree of bowing.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C09K 13/00 - Etching, surface-brightening or pickling compositions

86.

DRY DEPOSITED PHOTORESISTS WITH ORGANIC CO-REACTANTS

      
Application Number 18005169
Status Pending
Filing Date 2021-07-16
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Hansen, Eric Calvin
  • Weidman, Timothy William
  • Wu, Chenghao
  • Lin, Qinghuang
  • Blakeney, Kyle Jordan

Abstract

The present disclosure relates to a film formed with a precursor and an organic co-reactant, as well as methods for forming and employing such films. The film can be employed as a photopatternable film or a radiation-sensitive film. In particular embodiments, the carbon content within the film can be tuned by decoupling the sources of the radiation-sensitive metal elements and the radiation-sensitive organic moieties during deposition. In non-limiting embodiments, the radiation can include extreme ultraviolet (EUV) or deep ultraviolet (DUV) radiation.

IPC Classes  ?

  • G03F 7/004 - Photosensitive materials
  • G03F 7/20 - Exposure; Apparatus therefor
  • G03F 7/16 - Coating processes; Apparatus therefor
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

87.

EXCLUSION RING FOR SUBSTRATE PROCESSING

      
Application Number 18013749
Status Pending
Filing Date 2021-07-13
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Gulabal, Vinayakaraddy
  • Vellanki, Ravi
  • Dhawade, Eashan Raju
  • Mahadeva, Alok
  • Chen, Erica Maxine
  • Ba, Xiaolan

Abstract

In some examples, an exclusion ring locates a substrate on a substrate-support assembly in a processing chamber. An example exclusion ring comprises an inner edge portion to cover an edge of a substrate in the processing chamber and an outer edge portion to support the exclusion ring on the substrate support assembly in the processing chamber. The outer edge portion may include an outer edge of the exclusion ring. A separation zone extending between the inner edge portion and the outer edge of the exclusion ring includes an undercut in an undersurface of the exclusion ring. In some examples, a cooling gas is directed at the exclusion ring while the exclusion ring is located at a station or during an indexing operation performed by the exclusion ring within a processing tool.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/28 - Deposition of only one other non-metal element
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

88.

Selected Reject Band Non-Radiofrequency-Coupling Tile and Associated Methods and Systems

      
Application Number 18017381
Status Pending
Filing Date 2021-08-04
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Kapoor, Sunil
  • Madsen, Eric
  • Marohl, Dan

Abstract

A selected reject band non-RF-coupling tile includes a ground plate disposed on a first side of a printed circuit board. The selected reject band non-RF-coupling tile also includes a planar inductor disposed on a second side of the printed circuit board. The selected reject band non-RF-coupling tile also includes a conductive via structure extending through the printed circuit board. The conductive via structure electrically connects to both the ground plate and the planar inductor at a location near an interior end of the planar inductor. The selected reject band non-RF-coupling tile is used to shield enclosure walls and/or other electrical circuitry from RF fields. The selected reject band non-RF-coupling tile is also used to encapsulate an RF carrying component to block RF fields that emanate from the RF carrying component.

IPC Classes  ?

  • H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 1/02 - Printed circuits - Details
  • H01F 27/28 - Coils; Windings; Conductive connections

89.

ELECTROSTATIC CHUCKS WITH COOLANT GAS ZONES AND CORRESPONDING GROOVE AND MONOPOLAR ELECTROSTATIC CLAMPING ELECTRODE PATTERNS

      
Application Number 18139660
Status Pending
Filing Date 2023-04-26
First Publication Date 2023-08-17
Owner Lam Research Corporation (USA)
Inventor
  • Matyushkin, Alexander
  • Comendant, Keith Laurence
  • Holland, John Patrick

Abstract

An electrostatic chuck for a substrate processing system is provided and includes a baseplate, an intermediate layer disposed on the baseplate, and a top plate. The top plate is bonded to the baseplate via the intermediate layer and is configured to electrostatically clamp to a substrate. The top plate includes a monopolar clamping electrode and seals. The monopolar clamping electrode includes a groove opening pattern with coolant gas groove opening sets. The seals separate coolant gas zones. The coolant gas zones include four or more coolant gas zones. Each of the coolant gas zones includes distinct coolant gas groove sets. The top plate includes the distinct coolant gas groove sets. Each of the distinct coolant gas groove sets has one or more coolant gas supply holes and corresponds to a respective one of the coolant gas groove opening sets.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

90.

BALUN TRANSFORMER WITH ENHANCED RF COUPLING EMBEDDED IN HIGH-STRENGTH DIELECTRIC MATERIALS

      
Application Number US2023012347
Publication Number 2023/154233
Status In Force
Filing Date 2023-02-03
Publication Date 2023-08-17
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Peng, Shen
  • Liu, James, Zu Yi
  • Benyuhmin, Narudha
  • Kapoor, Sunil
  • Marohl, Dan

Abstract

A balun transformer for use in powering an electrode coil of a semiconductor chamber is provided. In one example, the balun transformer includes a primary coil having a primary winding between a primary first end and a primary second end. The primary winding defined from a primary rectangular conductor. The balun transformer includes a secondary coil having a secondary winding between a secondary first end and a secondary second end. The secondary winding defined from a secondary rectangular conductor. The primary rectangular conductor and the secondary rectangular conductor are interleaved in a spaced apart orientation, such that one or two sides of each of the primary rectangular conductor and the secondary rectangular conductor are adjacent to one another.

IPC Classes  ?

  • H01F 30/10 - Single-phase transformers
  • H01F 27/30 - Fastening or clamping coils, windings, or parts thereof together; Fastening or mounting coils or windings on core, casing, or other support
  • H01J 37/32 - Gas-filled discharge tubes
  • H03H 7/38 - Impedance-matching networks

91.

UNIFORMITY CONTROL CIRCUIT FOR IMPEDANCE MATCH

      
Application Number 18010194
Status Pending
Filing Date 2021-11-02
First Publication Date 2023-08-10
Owner Lam Research Corporation (USA)
Inventor
  • Marakhtanov, Alexei M.
  • Kozakevich, Felix Leib
  • Ji, Bing
  • Holland, John P.

Abstract

An impedance match housing is described. The impedance match housing includes an impedance matching circuit having an input that is coupled to a radio frequency (RF) generator. The impedance matching circuit has an output that is coupled to a first RF strap. The impedance match housing includes a uniformity control circuit coupled in parallel to a portion of the first RF strap to modify uniformity in a processing rate of a substrate when the substrate is processed within a plasma chamber.

IPC Classes  ?

92.

Systems and Methods for Radiofrequency Signal Generator-Based Control of Impedance Matching System

      
Application Number 18012962
Status Pending
Filing Date 2021-11-09
First Publication Date 2023-08-10
Owner Lam Research Corporation (USA)
Inventor
  • Lyndaker, Bradford J.
  • Marakhtanov, Alexei
  • Kozakevich, Felix Leib
  • Hopkins, David

Abstract

An RF signal supply system for plasma generation includes an RF signal generator, an impedance matching system, and a control module. The RF signal generator includes a control system. The impedance matching system has an input connected to an output of the RF signal generator, an output connected to a plasma processing system, a gamma control capacitor, and a frequency control capacitor. The control module is connected in data communication with each of the RF signal generator and the impedance matching system. The control module is programmed to transmit control signals to the impedance matching system based on corresponding data received from the control system of the RF signal generator, where the control signals direct control of the gamma control capacitor and the frequency control capacitor. The control module is also programmed to transmit data received from the impedance matching system to the control system of the RF signal generator.

IPC Classes  ?

93.

SUBSTRATE TRANSFER DOOR ASSEMBLIES WITH RADIATING ELEMENTS FOR SUBSTRATE PROCESSING CHAMBERS

      
Application Number 18013161
Status Pending
Filing Date 2021-08-23
First Publication Date 2023-08-10
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Drewery, John
  • Inori, David
  • Desepte, Andre
  • Kinsler, Michael Julius

Abstract

A substrate transfer door assembly includes a body, one or more radiating elements, a member, and at least one lifting coupler. The body includes a central portion. At least the central portion of the body operates as a substrate transfer door and covers at least one of an opening of a liner or an opening of a chamber wall of a substrate processing chamber. The one or more radiating elements radiating heat away from the body. The member extends from the body. The at least one lifting coupler is connected to the member and movable in a vertical direction between an open position and a closed position to cover the at least one of the opening of the liner or the opening of the chamber wall with the central portion of the body.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

94.

SEAL VENTING IN A SUBSTRATE PROCESSING CHAMBER

      
Application Number 18013737
Status Pending
Filing Date 2021-06-30
First Publication Date 2023-08-10
Owner Lam Research Corporation (USA)
Inventor
  • Han, Hui Ling
  • Kinsler, Michael Julius
  • Madsen, Steven James
  • Pioux, Gabriel

Abstract

In some examples, a double seal arrangement for a substrate processing chamber comprises a radially inner barrier seal disposed within a barrier seal gland. The barrier seal gland includes an inner toe and an outer toe. A radially outer vacuum seal is disposed within a vacuum seal gland. The vacuum seal gland includes at least an inner toe. A first venting pathway is provided between the inner toe of the vacuum seal gland and the outer toe of the barrier seal gland, and a second venting pathway is provided between the outer toe of the barrier seal gland and the inner toe of the barrier seal gland. A third venting pathway is in communication at least with the inner toe of the barrier seal gland, and a vacuum source connected to at least one of the first, second, and third venting pathways.

IPC Classes  ?

95.

FRICTION STIR PROCESSING FOR CORROSION RESISTANCE

      
Application Number 18013742
Status Pending
Filing Date 2021-06-30
First Publication Date 2023-08-10
Owner Lam Research Corporation (USA)
Inventor
  • Martin, Keith Joseph
  • Linebarger, Jr., Nick Ray

Abstract

In some examples, techniques for enhancing a corrosion resistance of a component are provided. In some examples, the component includes a granular metallic material. A friction stir processing operation is performed on the material. The friction stir processing operation comprises passing a rotating head of a friction stir welding tool through a surface thickness of the granular metallic material in a treatment path.

IPC Classes  ?

  • C22F 3/00 - Changing the physical structure of non-ferrous metals or alloys by special physical methods, e.g. treatment with neutrons
  • C22F 1/04 - Changing the physical structure of non-ferrous metals or alloys by heat treatment or by hot or cold working of aluminium or alloys based thereon

96.

SUBSTRATE SUPPORT WITH UNIFORM TEMPERATURE ACROSS A SUBSTRATE

      
Application Number 18013768
Status Pending
Filing Date 2021-11-16
First Publication Date 2023-08-10
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Smith, Jeremy George
  • Matyushkin, Alexander
  • Samulon, Eric
  • Comendant, Keith
  • Yu, Yixuan

Abstract

A substrate support for a substrate processing system includes a baseplate and a spray coat layer arranged on the baseplate. The spray coat layer has a first thickness and a first thermal conductivity. A bond layer is arranged on the spray coat layer. The bond layer has a second thickness and a second thermal conductivity. A ceramic layer is arranged on the bond layer. At least one of the first thickness and the second thickness varies in at least one of a radial direction and an azimuthal direction such that a third thermal conductivity between the ceramic layer and the baseplate varies in the at least one of the radial direction and the azimuthal direction.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating

97.

PORTABLE ROBOT FOR SEMICONDUCTOR EQUIPMENT MAINTENANCE TASKS

      
Application Number US2022053426
Publication Number 2023/149958
Status In Force
Filing Date 2022-12-19
Publication Date 2023-08-10
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Roy, Shambhu, Nath
  • Bhattacharyya, Gautam
  • Gadepally, Kamesh, Venkata
  • Brand, Vitali
  • Palanisamy, Kavin
  • Nallahally Jayaram, Abhilash
  • Glover, Daniel

Abstract

A robot arm assembly for use in a process module includes a base plate, a robot arm, a safety shield and a controller. The robot arm is disposed over the base plate and includes a plurality of components. The safety shield is defined to surround the base plate and the robot arm. The controller is disposed along a top surface on a lateral side of the safety shield and used to control operation of the robot arm and the plurality of components of the robot arm. The robot arm is configured to be mounted directly over a process module when a maintenance operation is to be performed at the process module.

IPC Classes  ?

  • B25J 11/00 - Manipulators not otherwise provided for
  • B25J 9/16 - Programme controls
  • B25J 9/12 - Programme-controlled manipulators characterised by positioning means for manipulator elements electric
  • B25J 19/02 - Sensing devices
  • B25J 19/06 - Safety devices
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

98.

RF POWER PATH SYMMETRY

      
Application Number US2023011285
Publication Number 2023/150029
Status In Force
Filing Date 2023-01-20
Publication Date 2023-08-10
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Vasquez, Miguel Benjamin
  • French, David Michael

Abstract

In some examples, a multi-station process tool comprises a plurality of process chambers, each process chamber located at a station of the multi-station process tool; and a RF power path component associated with each station of the multi-station process tool, the RF power path component geometrically positioned and oriented such that, when energized, a symmetric RF power path is created with respect to a center of the multi-station process tool.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

99.

A WAFER CHUCK ASSEMBLY WITH THERMAL INSULATION FOR RF CONNECTIONS

      
Application Number US2023061512
Publication Number 2023/150478
Status In Force
Filing Date 2023-01-27
Publication Date 2023-08-10
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Breiling, Patrick G.
  • Belostotskiy, Sergey G.
  • Thomas, Timothy S.
  • Hollingsworth, Joel
  • Chandrasekharan, Ramesh
  • Vahidi, Mahmoud

Abstract

Described is a wafer chuck assembly comprising a platen with one or more plasma electrodes, and a radio frequency (RF) assembly comprising at least one RF conductor electrically coupled to the one or more plasma electrodes. The at least one RF conductor comprises a rod with a rod tip coupled to the one or more plasma electrodes, and a rod stem mechanically coupled to a thermal choke with a hollow interior. The rod comprises a first electrically conductive material and has a first width and a first length. The thermal choke comprises a second electrically conductive material, and has a second width and a second length; and the second width is equal or greater than the first width.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01J 37/32 - Gas-filled discharge tubes

100.

METHOD OF MOUNTING WIRES TO SUBSTRATE SUPPORT CERAMIC

      
Application Number 18010322
Status Pending
Filing Date 2021-07-12
First Publication Date 2023-08-10
Owner LAM RESEARCH CORPORATION (USA)
Inventor
  • Mikhnenko, Oleksandr
  • Chau, Quan

Abstract

A substrate support assembly includes a baseplate, a ceramic plate arranged on the baseplate, and a plurality of wires. The ceramic plate includes a plurality of slots arranged on a side facing the baseplate and a plurality of electrically conducting terminals disposed in the plurality of slots, respectively. Each of the terminals includes a base portion connected to the ceramic plate, a second portion extending from the base portion towards the baseplate, and an opening in the second portion extending from an end of the second portion adjacent to the base portion to a distal end of the second portion. Each of the wires passes through the opening of the respective terminal and is braided around the distal end of the second portion of the respective terminal.

IPC Classes  ?

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