Abstract

The present disclosure relates to a memory cell (1) and to a method of erasing the memory cell (1). The memory cell comprises a doped well (100) of a first conductivity type and a transistor (T). Transistor (T) comprises a doped first region (106) of a second conductivity type opposite to the first conductivity type, the first doped region extending in the doped well (100); a buried doped channel (118) of the second conductivity type extending in the doped well (100); and a gate stack (108) resting on the doped well (100), above the buried doped channel (118). The gate stack (108) comprises a first layer (110) adapted to trap charges, a second insulating layer (112) resting on the first layer and a third conductive layer (114) resting on the second layer.

IPC Classes  ?

• H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A method includes compiling, by a compiler (305) of a Smart Secure Platform (SSP) supporting a Primary Platform (105) and a Secondary Platform, source code comprising an implementation of an operating system of the Secondary Platform and applications of the Secondary Platform, to produce compiled source code compatible by an operating system of the Primary Platform (105); linking, by the compiler (305), personalization data to the compiled source code to produce a native Secondary Platform Bundle (SPB) compatible with the Primary Platform (105), the personalization data being associated with a subscription of a user of the SSP; and delivering, by the compiler, the native SPB.

IPC Classes  ?

• G06F 8/76 - Adapting program code to run in a different environment; Porting
• H04W 12/30 - Security of mobile devices; Security of mobile applications
• G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
• H04W 8/20 - Transfer of user or subscriber data

Abstract

Embedded secure element The present description concerns an embedded electronic system or a method implemented by such a system, including: at least one volatile memory (RAM); and at least one low-level operating system managing the allocation of areas of the volatile memory to a plurality of high-level operating system, each including one or a plurality of applications, wherein said volatile memory includes: at least a first portion (PRAM30) reserved to execution data of a first application (App30); and at least a second portion intended to store execution data of at least a second application (App31), the execution data of the first application remaining in the volatile memory in case of a deactivation or of a setting to standby of this first application.

IPC Classes  ?

• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
• G06F 9/46 - Multiprogramming arrangements
• G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
• G06F 12/02 - Addressing or allocation; Relocation
• G06F 9/4401 - Bootstrapping
• G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data

Abstract

The present description concerns an embedded electronic system or a method implemented by such a system including: at least one volatile memory (RAM); at least one low-level operating system managing the allocation of areas of the volatile memory to a plurality of high-level operating systems, each including one or a plurality of applications (App20, App21), wherein data of execution of one or a plurality of tasks of said first application (App20) are partly transferred by the low-level operating system from said volatile memory to a non-volatile memory (WM) when the execution of said task of the first application is interrupted by the execution of at least one task of a second application (App21).

IPC Classes  ?

• G06F 9/46 - Multiprogramming arrangements
• G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
• G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
• G06F 9/4401 - Bootstrapping
• G06F 12/02 - Addressing or allocation; Relocation
• G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
• G06F 21/74 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode

Abstract

A method comprises molding laser direct structuring material (10), having particles (12) dispersed therein, onto at least one semiconductor die (11), applying laser beam energy to produce structured formations (14) with a part of the particles (12) exposed at the structured formations (14), contacting the structured formations (14) with a solution containing one or more organic compounds, forming a film covering at least partly the structured formations (14) and comprising one or more conductive polymers resulting from a polymerization reaction of the one or more organic compounds, and forming electrically-conductive material (24) onto the film.

IPC Classes  ?

• H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

Abstract

The present description concerns a secure on-board element (E) comprising a volatile memory (PRAM), and being configured to implement at least part of a first application (App30) and at least part of one or more second applications (App31) designed to be implemented by at least one low-level operating system (113) of the secure on-board element (E), in which: - execution data of the first application (App30) are stored in a first reserved part of the volatile memory (PRAM) configured to store only execution data of the first application (App30); and - execution data of the second applications are stored in a second part of the volatile memory (PRAM) different from the first reserved part of the volatile memory (PRAM).

IPC Classes  ?

• G06F 9/445 - Program loading or initiating
• G06F 12/02 - Addressing or allocation; Relocation
• G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
• G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• G06F 21/60 - Protecting data
• G06F 21/77 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards

Abstract

The present invention concerns an onboard secure element (E) comprising a virtual memory (VRAM), and being configured to implement at least part of a first application (App20) adapted to be implemented by at least one low level operating system (113) of the onboard secure element (E), wherein execution data relating to one or more secondary tasks of said first application (App20) are stored in part of said virtual memory (VRAM) when the execution of said part of the first application (App20) is interrupted by the execution of at least part of a second application (App21).

IPC Classes  ?

• G06F 9/445 - Program loading or initiating
• G06F 12/02 - Addressing or allocation; Relocation
• G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
• G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• G06F 21/60 - Protecting data
• G06F 21/77 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards

Abstract

A method of communication for use, for instance, in systems such as solar panel power generation systems, house monitoring systems, traffic surveillance systems or smart street lighting systems may comprise:- providing a communication circuit (such as a modem 10) for communicating signals conveying information messages, the communication circuit (10) supporting a first communication protocol (101), adopting, for instance, S-FSK modulation, and a second communication protocol (102), adopting, for instance,PSK or QAM modulation,- including in the communicated signals first signals conveying first information messages and second signals conveying second information messages, wherein the first information messages comprise repetitive messages having fixed repeated content and the second information messages comprise non-repetitive messages having variable content, and- transmitting the first signals and the second signals via the communication circuit using the first communication protocol (101) for the first, repetitive signals and the second communication protocol (102) for the second, non-repetitive signals, respectively.

IPC Classes  ?

• H04W 4/20 - Services signalling; Auxiliary data signalling, i.e. transmitting data via a non-traffic channel
• H04L 29/08 - Transmission control procedure, e.g. data link level control procedure

Abstract

A vehicle such as a motor car (V) equipped with a radio equipment (14) is provided with a rearview camera 5 (10). Video frames from the rearview camera (10) are received at the radio equipment (14) and transmitted to a mobile communication device (S) such as a smart phone equipped with a video screen (S1) so that video frames from the rearview camera (10) are displayed on the 10 video screen (S1) of the mobile communication device (S).

IPC Classes  ?

• H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
• B60R 1/00 - Optical viewing arrangements; Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles

Abstract

A device (504) includes an interface (508) and Time Division Multiple Access (TDMA) Medium Access Control (MAC) circuitry (510) coupled to the interface. The TDMA MAC circuitry (510) detects (610) a beacon (210) in a frame (202) having a defined frame duration and determines (620) a frame compensation value based on a start time of the frame, a reference start time of the frame, and a number of elapsed frames. A current frame duration value is determined (622) based on the frame compensation value and the defined frame duration.

IPC Classes  ?

• H04B 3/54 - Systems for transmission via power distribution lines
• H04L 12/70 - Packet switching systems
• H04J 3/06 - Synchronising arrangements

Abstract

An electronic device includes a rectifier bridge (130) that includes an input configured to be coupled to power over Ethernet (PoE) power sourcing equipment (PSE), and an output. A transistor (140) is configured to selectively couple the output with a load. The electronic device includes a maintain power signature (MPS) device (170), and a control circuit (180). The control circuit is to maintain the transistor on when a load current is above a threshold, source current from the rectifier bridge to the MPS device when the load current is below the threshold, and switch the transistor to a diode configuration when the load current is below the threshold.

IPC Classes  ?

• H04L 12/10 - Current supply arrangements
• H04L 12/40 - Bus networks
• G06F 1/26 - Power supply means, e.g. regulation thereof
• G05F 3/24 - Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only

Abstract

A method for providing, e.g. by means of an application (S_APPa) installed on an Universal Integrated Circuit Card (108a),a response to a SCP80 command is described. Initially, a first SMS message is received, e.g. by means of a mobile device (10), from a remote server (MNO) and decrypted according to the protocol SCP80. Specifically, this first SMS message contains a first command requesting the execution of a proactive command. Once, the proactive command has been executed and a respective response has been obtained,a second SMS message (SMS3) is transmitted to the remote server (MNO) indicating that the response has been obtained. Next, a third SMS message (SMS4) is received from the remote server (MNO)and decrypted according to the protocol SCP80. Specifically, this third SMS message (SMS4) contains a second command (C-APDU2) requesting the transmission of a response message determined as a function of the proactive command response(RSP1). Accordingly, the response message (R-APDU1)may be generated, encrypted according to the protocol SCP80 and transmitted(SMS5) the remote server (MNO).

IPC Classes  ?

• H04W 12/02 - Protecting privacy or anonymity, e.g. protecting personally identifiable information [PII]
• H04W 4/00 - Services specially adapted for wireless communication networks; Facilities therefor

Abstract

A method for transmitting at least one IP data packet to an IP address being associated with a host name is described. Specifically, in order to obtain the IP address associated with a host name, a first service message of the Short Message Service is transmitted to a Short Message Service gateway server (402), wherein the first service message comprising a host name resolution request for the host name. In response to this request, a second service message of the Short Message Service is received from the Short Message Service gateway server (402), wherein the second service message comprising the IP address associated with the host name. Finally, at least one IP data packet is transmitted to the IP address associated with the host name.

IPC Classes  ?

• H04L 12/58 - Message switching systems
• H04L 29/12 - Arrangements, apparatus, circuits or systems, not covered by a single one of groups characterised by the data terminal
• H04W 4/14 - Short messaging services, e.g. short message service [SMS] or unstructured supplementary service data [USSD]

Abstract

A device for detecting obstacles (10) that is wearable by a subject (18) on a foot (19), in particular integrated in an item of footwear (30) that is wearable by the subject (18), the aforesaid device (10) comprising at least one ultrasound source (12T) for emitting an ultrasound transmission signal (UT) and an ultrasound receiver (12T) for receiving a corresponding ultrasound signal (UR) reflected by an obstacle (16), a control module (11) for measuring a time of flight (At) between emission of the ultrasound transmission signal (UT) and reception of the corresponding ultrasound signal (UR) reflected by the obstacle (16) and calculating, on the basis of the aforesaid time of flight (Δt), the distance (d) at which the obstacle (16) is located. The device comprises an inertial sensor (13), in particular an acceleration sensor, designed to measure acceleration of the foot (19) along three axes (x, y, z), and a control module (11) configured for enabling operation of the ultrasound source (12T) if the aforesaid acceleration values measured by the inertial sensor (13) respect a given condition (Cen) for enabling measurement of the time of flight (Δt).

IPC Classes  ?

• G01S 15/93 - Sonar systems specially adapted for specific applications for anti-collision purposes
• G01S 15/02 - Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems using reflection of acoustic waves
• G01S 15/10 - Systems for measuring distance only using transmission of interrupted, pulse-modulated waves
• G01S 7/523 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of pulse systems
• G01S 7/521 - Constructional features

Abstract

An integrated-circuit card (1) is described, said card comprising a substrate (2) and a circuit (3) integrated in the substrate (2), with the pads of the circuit (3) substantially coplanar with a surface (S) of the substrate (2). The substrate (2) comprises a first area defining a first sector (5) comprising the circuit (3) and able to be separated from the card (1), said first sector (5) having a form and size equivalent to a 4FF format of integrated-circuit cards and being intended to be separated from the card owing to a first pre-cut or weakening line (4) delimiting said first sector (5) with 4FF format; the card further comprises at least one area defining a second sector (7) around the first sector (5) and able to be separated from card (1) owing to a second pre-cut or weakening line (6), said second sector (7) having a form or size equivalent to a 2FF or 3FF format of integrated-circuit cards, and a screen-printed coating (8) on the surface (SC) opposite to the surface (S) of the substrate (2), in the region of at least the second sector (7), the screen-printed coating (8) having, along the second sector (7), a thickness (B) which is equal to the difference between a predefined thickness (X) of the 2FF or 3FF format and a thickness (A) of the first sector ( 5 ).

IPC Classes  ?

• G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier

Abstract

It's illustrated a method to detect a message compatible with the OTA standard (Over The Air) and affected by a wrong ciphering. The method comprises the steps of receiving the ciphered OTA message; deciphering the OTA message; reading a counter field (PCNTR) of padding bytes in the deciphered OTA message and reading corresponding padding bytes in the OTA message deciphered; detecting at least one bit 1 in at least one of the padding bytes of the OTA message deciphered, said at least one bit 1 being indicative of the wrong ciphering.

IPC Classes  ?

• H04W 12/10 - Integrity
• H04W 12/02 - Protecting privacy or anonymity, e.g. protecting personally identifiable information [PII]
• H04W 12/12 - Detection or prevention of fraud

Abstract

A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.

IPC Classes  ?

• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
• G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication

Abstract

An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

IPC Classes  ?

• G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
• H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

Abstract

A communication interface (921) for interfacing a transmission circuit (901) with an interconnection network (701), wherein the transmission circuit (901) requests via a transmission request transmission of a predetermined amount of data. In particular, the communication interface (921) receives data segments from the transmission circuit (901), stores the data segments in a memory (922), and verifies whether the memory (922) contains the predetermined amount of data. In the case where the memory (922) contains the predetermined amount of data, the communication interface (921) starts transmission (924) of the data stored in the memory (922). Instead, in the case where the memory (922) contains an amount of data that is less than the predetermined amount of data, the communication interface (921) determines a parameter that identifies the time that has elapsed since the transmission request or the first datum received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface (921) starts transmission (924) of the data stored in the memory.

IPC Classes  ?

• G06F 13/40 - Bus structure

Abstract

The invention relates to an integrated electronic device (400; 400a; 500, 500'; 600, 600'; 700, 700') on a semiconductor material chip for detecting the pressure related to a force (F) applied in a predetermined direction (d) within a solid structure. The device comprises: - an integrated element (51) defined by an operating surface of the chip (52) that is substantially orthogonal to the direction (d) of application of the force; first (53) and second (54) conductive elements accommodated within the substrate element (51) and configured to face the operating surface; a measure module (55) accommodated within the substrate element and comprising first (56) and second (57) measurement terminals which are electrically connected to the first (53) and second (54) conductive elements, respectively; a detecting element (58) arranged in the predetermined direction (d) such that the operating surface (52) is sandwiched between the first (53) and second (54) conductive elements and this detecting element ( 58 ); - an insulating layer (59) suitable to coat at least the operating surface in order to galvanically insulate the first (53) and second (54) conductive elements. The device comprises a layer of dielectric material (510, 510') which is at least sandwiched between the detecting element (58) and the insulating layer (59). The layer of dielectric material is elastically deformable following the application of the force (F) in the predetermined direction to change an electromagnetic coupling between the detecting element (58) and the above-mentioned first (53) and second (54) conductive elements.

IPC Classes  ?

• G01L 25/00 - Testing or calibrating of apparatus for measuring force, torque, work, mechanical power, or mechanical efficiency
• G01L 1/14 - Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators

Abstract

An integrated electronic device 1 for detecting at least one parameter related to humidity and/or presence of water and/or acidity/basicity of an environment surrounding the device is described. Such device 1 comprises a separation layer 14 from the surrounding environment, comprising at least one portion of insulating material 14, and further comprises a first conductive member 11 and a second conductive member 12, made of an electrically conductive material, arranged inside the separation layer 14, with respect to the surrounding environment, and separated from the surrounding environment by the separation layer 14. The device 1 also comprises a measurement module 15, having two measurement terminals 151, 152, electrically connected with the first 11 and the second 12 conductive members, respectively; the measurement module 15 is configured to provide an electric potential difference between the first 11 and the second 12 conductive members. The device 1 further comprises electrode means 13, configured to act as an electrode, arranged outside of the separation layer 14, with respect to the first 11 and the second 12 conductive members; the electrode means 13 are arranged so as to form, with the first 11 and the second 12 conductive members, an electromagnetic circuit having an electromagnetic circuit overall impedance variable based upon the exposure to environmental conditions with a variable level of humidity and/or acidity/basicity. The measurement module 15 is configured to measure the electromagnetic circuit overall impedance, which is present between the measurement terminals 151, 152, and to determine the at least one parameter to be detected, based on the overall impedance measured.

IPC Classes  ?

• G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance

Abstract

A planar electric circuit board may include a planar support of a foldable material defining a base surface and wings coupled to the base surface along respective folding lines so that the wings, when folded along the folding lines, are erected with respect to the base surface and remain in that position. An auxiliary circuit is on the planar support and may include pairs of capacitive coupling plates defined on the wings and on the base surface, and electric communication lines coupled to corresponding ones of the pairs of capacitive coupling plates.

IPC Classes  ?

• H05K 1/02 - Printed circuits - Details

Abstract

The present invention provides for a method for extraction of descriptors from video content, comprising the following steps: a Key Frame Extracting step, applying a local descriptors-based approach to select pictures of the incoming video as key frames that are representative of a temporal region of the video which is visually homogeneous; a Content Analysis step, analysing the content of said key frames and classifying image patches of said key frames as interesting or not for said extraction of descriptors; a Descriptors Extracting step, extracting compact descriptors from said selected key frames, and defining a set of surrounding images also on the basis of input received from said Content Analysis step; a Temporal Coding step, multiplexing information about the time points at which said key frames have been extracted in said Key Frame Extracting step with said compact descriptors extracted in said Descriptors Extracting step, obtaining said descriptors.

IPC Classes  ?

• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• G06K 9/46 - Extraction of features or characteristics of the image

Abstract

An integrated electronic device, delimited by a first surface (S1) and by a second surface (S2) and including: a body (2) made of semiconductor material, formed inside which is at least one optoelectronic component chosen between a detector (30) and an emitter (130); and an optical path (OP), which is at least in part of a guided type and extends between the first surface and the second surface, the optical path traversing the body. The optoelectronic component is optically coupled, through the optical path, to a first portion of free space and a second portion of free space, which are arranged, respectively, above and underneath the first and second surfaces.

IPC Classes  ?

• G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections

Abstract

The network (100) of electronic devices is formed on a flexible substrate (15; 101) by a plurality of electronic devices (1; 104) assembled on the flexible substrate. The electronic devices have an embedded antenna for mutual coupling (4; 111) of a wireless type. Each electronic device (1; 104) is formed by a chip or a complex system integrating a transceiver circuit (3) connected to the embedded antenna (4; 11) and a functional part (12; 112) connected to the transceiver circuit and including at least one element chosen in the group comprising: a sensor, an actuator, an interface, an electrode, a memory, a control unit, a power-supply unit, a converter, an adapter, a digital circuit, an analog circuit, an RF circuit, a microelectromechanical system, an electrode, a well, a cell, a container for liquids. The flexible support may be a substrate (15) of plastic material that incorporates the electronic devices or a garment having smart buttons that house the electronic devices.

IPC Classes  ?

• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H01L 23/64 - Impedance arrangements
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/66 - High-frequency adaptations
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
• H02J 5/00 - Circuit arrangements for transfer of electric power between ac networks and dc networks
• G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
• A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
• H01Q 7/00 - Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
• H02J 17/00 - Systems for supplying or distributing electric power by electromagnetic waves

Abstract

A package (15) for devices (100) insertable into a solid structure (300) for detecting and monitoring one or more local parameters is described. The package (15) is made of a building material formed of particles of micrometric or sub-micrometric dimensions. A device (100) for detecting and monitoring one or more local parameters within a solid structure is further described. The device (100) comprises an integrated detection module (1), having at least one integrated sensor (10), and a package (15), having the above-mentioned characteristics, so arranged as to coat at least one portion of the device (100), comprising the integrated detection module (1). A method for manufacturing the device (100), and a system (200) for monitoring parameters in a solid structure (300), comprising such a device (100), are also described.

IPC Classes  ?

• G01D 11/24 - Housings
• G01M 5/00 - Investigating the elasticity of structures, e.g. deflection of bridges or aircraft wings

Abstract

In an assembly of a semiconductor integrated device (30), a package (32) has a base element (33) and a covering element (34) defining an internal space (35), an access opening (36) is provided through the covering element (34) for access to the internal space (35) from outside, and a MEMS acoustic transducer (20) is housed within the package (32) and includes a die (21) integrating a microelectromechanical sensing structure (1), defining a membrane (2) suspended over a cavity (6) and facing a rigid plate (3). The MEMS acoustic transducer (20) is set so that the die (21) is directly set between the access opening (36) and the internal space (35), defining an uninterrupted fluidic path including the access opening (36), the cavity (6), and the internal space (35). The semiconductor integrated device (30) includes a further MEMS sensor (44), with a die (45) integrating a respective microelectromechanical sensing structure (46) having a sensing element (64) set in fluid communication with the outside through the same fluidic path.

IPC Classes  ?

• H04R 1/04 - Structural association of microphone with electric circuitry therefor
• H04R 19/00 - Electrostatic transducers
• H04R 19/04 - Microphones

Abstract

A base (2) carries a first chip (3) and a second chip (4) oriented differently with respect to the base and packaged in a package (6). Each chip integrates an antenna and a magnetic via (13). A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips (3, 4) even if the magnetic path is interrupted, and is formed by a first stretch (5c) coupled between the first magnetic-coupling element (13) of the first chip and the first magnetic-coupling element (12) of the second chip, and a second stretch (5f) coupled between the second magnetic-coupling element (12) of the first chip and the second magnetic-coupling element (13) of the second chip. The first stretch has a parallel portion (5c1, 5c3) extending parallel to the faces (2a, 2b) of the base. The first and second stretches have respective transverse portions (5i1, 5i2) extending on the main surfaces of the second chip, transverse to the parallel portion.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A vertical-conduction electronic device (100; 150), comprising: a semiconductor wafer (1) including a semiconductor layer (2, 3) having a first side (3a), a first type of conductivity (N), and a first doping level; a first body region (32) and a second body region (34), which have a second type of conductivity (P) and extend in the semiconductor layer (2, 3); an enriched region (12), having the first type of conductivity and a second doping " level higher than the first doping level, which extends in the semiconductor layer facing the first side (3a), between the first and second body regions (32, 34); a dielectric filling region (20), which extends in the semiconductor layer, facing the first side (3a), and completely surrounded by the enriched region (12); and a gate structure (29), which extends on the first side (3a) on the enriched region (12), on the dielectric filling region (20), on part of the first body region (32), and on part of the second body region (34).

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

The present invention relates to a flexible antenna for NFC communication with SIM card of a mobile device, comprising a RF pad for establishing radio communication with another device. Each projection extending from the RF pad comprises on its end a SIM pad with a different orientation with respect to the orientation of the other SIM pads on the other projections.

IPC Classes  ?

• H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
• H01Q 1/22 - Supports; Mounting means by structural association with other equipment or articles
• H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier

Abstract

A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

IPC Classes  ?

• G06F 1/00 - ELECTRIC DIGITAL DATA PROCESSING - Details not covered by groups and

Abstract

A MEMS device (17) formed by a body (2); a cavity (25), extending above the body; mobile and fixed structures (18, 19) extending above the cavity and physically connected to the body via anchoring regions (16); and electrical-connection regions (10a, 10b, 10c), extending between the body (2) and the anchoring regions (16) and electrically connected to the mobile and fixed structures. The electrical-connection regions (10a, 10b, 10c) are formed by a conductive multilayer including a first semiconductor material layer (5), a composite layer (6) of a binary compound of the semiconductor material and of a transition metal, and a second semiconductor material layer (7).

IPC Classes  ?

• B81B 7/00 - Microstructural systems
• B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes

Abstract

A method for manufacturing a protective layer (25) for protecting an intermediate structural layer (22) against etching with hydrofluoric acid (HF), the intermediate structural layer (22) being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminium oxide, by atomic layer deposition, on the intermediate structural layer (22); performing a thermal crystallization process on the first layer of aluminium oxide, forming a first intermediate protective layer (25a),- forming a second layer of aluminium oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallisation process on the second layer of aluminium oxide, forming a second intermediate protective layer (25b) and thereby completing the formation of the protective layer (25). The method for forming the protective layer (25) can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

A detection, structure (1) for a z-axis resonant accelerometer (24) is provided with an inertial mass (2) anchored to a substrate (20) by means of elastic anchorage elements (6) so as to be suspended above the substrate (20) and perform an inertial movement of rotation about a first axis of rotation (A) belonging to a plane (xy) of main extension of the inertial mass (2), in response to an external acceleration (az) acting along a vertical axis (z) transverse with respect to the plane (xy); and a first resonator element (10a) and a second resonator element (10b), which are mechanically coupled to the inertial mass (2) by respective elastic supporting elements (16), which enable a movement of rotation about a second axis of rotation (B) and a third axis of rotation (C), in a resonance condition. In particular, the second axis of rotation (B) and the third axis of rotation (C) are parallel to one another, and are moreover parallel to the first axis of rotation (A) of the inertial mass (2).

IPC Classes  ?

• G01P 15/097 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by vibratory elements

Abstract

An electronic device includes a silicon substrate (2) having a first side and a second side. A structural layer of gallium nitride (6) is formed over the first side of the silicon substrate and includes an active area of the electronic device. A transition layer (8) is provided between the substrate and the structural layer. The transition layer electrically and/or thermally insulated the substrate and the structural layer from one another. A via hole (20) made of a conductive material extends through the structural layer and the transition layer. The via hole is electrically and/or thermally connected to the active area of the electronic device and to the substrate.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections

Abstract

The present invention relates to a method and an apparatus for manufacturing lead frames. According to the present invention, a coating layer (120) is formed on one or more predefined portions (A, B, C, D, E, F, G, H) of the surface (110s) of the substrate (100) of the lead frame (100) by delimiting the predefined portions (A, B, C, D, E, F, G, H) by means of screen printing. The employment of screen printing allows the obtainment of large amounts of lead frames with excellent electronic and structural properties in a quick and cost-effective way.

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
• B41C 1/14 - Forme preparation for stencil printing or silk-screen printing

Abstract

The invention concerns a method for etching a PVD deposited barium strontium titanate (BST) layer, wherein a non-ionic surfactant at a concentration between 0.1 and 1 percent is added to an acid etching solution.

IPC Classes  ?

• H01L 21/311 - Etching the insulating layers

Abstract

A sound sensor (11) in which a vibrating membrane (22) and a fixed membrane (23) are formed on the upper surface of a semiconductor substrate (21) converts a sound wave into an electrical signal and outputs the same by the change in the electrostatic capacity between a vibrating electrode (220) of the vibrating membrane (22) and a fixed electrode (230) of the fixed membrane (23). In the sound sensor (11) at least one of the vibrating electrode (220) or the fixed electrode (230) is divided, and a plurality of electrical signals are output from each of the resulting plurality of electrodes.

IPC Classes  ?

• H04R 19/04 - Microphones

Abstract

4D data ultrasound imaging system (100) comprising a matrix (10) of transducer elements (3) suitable for transmitting and for receiving ultrasound signals, said transducer elements (3) being divided into sub-matrixes (21) suitable for receiving in a delayed way a same acoustic signal, a plurality of reception channels (22) with one of said reception channels (22) being associated with one of said transducer elements (3), a beamformer device (109) comprising a plurality of storage cells (111) arranged in re-phasing matrixes (112), each re-phasing matrix (1 12) being associated with a corresponding sub-matrix (21) with each row (Ri) associated with one of said transducer elements (3), said storage cells (111) comprising an input storage stage (In) that is selectively associated with a row (Ri) and a reading output stage (Out) that is selectively associated with a buffer (16); each storage cell (111) that belongs to a same column (Coi) has the input stage (In) that is dynamically activated in sequential times with respect to another storage cell (11 1) of the same column (Coi) for storing the same delayed acoustic signal, said storage cells (1 11) that belong to the same column (Coi) have the output stage (Out) that is simultaneously activated.

IPC Classes  ?

• G01S 15/89 - Sonar systems specially adapted for specific applications for mapping or imaging

Abstract

A retinal prosthesis including an electronic stimulation unit (40) housed inside an eye and including: a plurality of electrodes (62); an electronic control circuit (92, 102), which is electrically connected to the electrodes and supplies to the electrodes electrical stimulation signals designed to stimulate a portion of a retina of the eye; and a local antenna (114) connected to the electronic control circuit. The retinal prosthesis further includes an electromagnetic expansion (35) housed inside the eye and formed by a first expansion antenna (44) and a second expansion antenna (46) electrically connected together, the first expansion antenna being magnetically or electromagnetically coupled to an external antenna (38), the second expansion antenna being magnetically or electromagnetically coupled to the local antenna, the electromagnetic expansion moreover receiving an electromagnetic supply signal transmitted by the external antenna and generating a corresponding replica signal.

IPC Classes  ?

• A61F 9/08 - Devices or methods enabling eye-patients to replace direct visual perception by another kind of perception

Abstract

Device (100) for detecting and monitoring local parameters within a solid structure (300). The device comprises an integrated detection module (1) made on a single chip, having an integrated functional circuitry portion (16) comprising at least one integrated sensor (10) and an integrated antenna (11), and electromagnetic means (2) for transmitting/receiving signals and energy exchange. The integrated functional circuitry portion (16) comprises a functional surface (18) facing towards the outside of the chip. A passivation layer (15) is arranged to completely cover at least the functional surface (18), so that the integrated detection module (1) is entirely hermetically sealed and galvanically insulated from the surrounding environment. The integrated antenna (11), the electromagnetic means (2) and the remote antenna (221) are operatively connected wirelessly through magnetic or electromagnetic coupling.

IPC Classes  ?

• G01N 27/20 - Investigating the presence of flaws
• G01N 33/38 - Concrete; Lime; Mortar; Gypsum; Bricks; Ceramics; Glass
• G01L 1/18 - Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material

Abstract

The present invention in a single structure combines a pad comprising a connection terminal suitable for connecting the circuit elements integrated in a chip to circuits outside of the chip itself and at least one condenser. By combining a connection pad and a condenser in a single structure it is possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the condenser itself. In this way, the costs and size of the chip can be reduced.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A control device for a switching mode DC-DC converter, the converter comprising at least a half-bridge with at least first (Q1) and second (Q2) switches connected between an input voltage (Vin) and a reference voltage. The converter further comprises a transformer (20) with a primary coupled with the center point (HB) of the half -bridge and a secondary (22) coupled with a load (Load). The control device comprises an error detector (2) configured to determine an error signal (Se) between a first signal (Vout1) representative of the voltage (Vout) across the load and a first reference signal (Vref2) and a frequency controller (100) configured to increase the switching frequency of the half -bridge when the error signal (Se) is kept below a second signal (Vrefl).

IPC Classes  ?

• H02M 3/337 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration

Abstract

A coupling interface couples a transceiver to one or more capacitive voltage dividers of a power transmission system. The coupling interface includes a first signal path including an adjustable inductance configured to form a resonance circuit with a capacitance associated with the one or more capacitive voltage dividers. The coupling interface may include a second signal path including an adjustable inductance configured to form a resonance circuit with the capacitance associated with the one or more capacitive voltage dividers.

IPC Classes  ?

• H04B 3/56 - Circuits for coupling, blocking, or by-passing of signals

Abstract

An integrated magnetoresistive device, where a substrate (17) of semiconductor material is covered, on a first surface (19), by an insulating layer (18). A magnetoresistor (26) of ferromagnetic material extends in the insulating layer and defines a sensitivity plane of the sensor. A concentrator (34) of ferromagnetic material including at least one arm (34a), extending in a transversal direction to the sensitivity plane and vertically offset to the magnetoresistor (26). In this way, magnetic flux lines directed perpendicularly to the sensitivity plane are concentrated and deflected so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

IPC Classes  ?

• G01R 33/00 - Arrangements or instruments for measuring magnetic variables
• G01R 33/09 - Magneto-resistive devices

Abstract

A low voltage isolation circuit (1) is described inserted between a connection node (HVout) to a matrix (2) of switches suitable for receiving a high voltage signal (IM) and a connection terminal (pzt) to a load (PZ) suitable for transmitting said high voltage signal (IM) to said load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, - Vss) and comprising at least a first driving transistor (M l), inserted, in series with a first driving diode (Dl), between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted, in series with a second diode (D2), between the driving central circuit node (Xc) and the second supply voltage reference (-Vss). The switch comprises an isolation block (8) connected to the connection terminal (pzt), to the connection node (HVout) and to the driving central circuit node (Xc) and comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the connection node (HVout) to the matrix (2) of switches and the connection terminal (pzt) to the load (PZ) of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc).

IPC Classes  ?

• H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
• H03K 17/30 - Modifications for providing a predetermined threshold before switching
• G01S 7/52 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group
• B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy

Abstract

A switching circuit (10) for an ultrasound transmission channel (1) is inserted between a connection terminal (Xdcr) and a low voltage output terminal (LVout) and comprising a receiving switch (30) a high voltage clamp circuit (HV1) inserted between the connection terminal (Xdcr) and a central node (Vc), a low voltage clamping switch (25) inserted between said central node (Vc) and a reference voltage (GND), the receiving switch (30) being low voltage and being inserted between the central node (Vc) and the low voltage output terminal (LVout), the clamping switch (25) and the receiving switch (30) being controlled in a complementary way with respect to each other. A transmission channel ( 1) for ultrasound applications is also described comprising at least such a switching circuit (10) and a process for driving said switching circuit (10).

IPC Classes  ?

• B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
• H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Abstract

A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).

IPC Classes  ?

• H03F 3/30 - Single-ended push-pull amplifiers; Phase-splitters therefor
• H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
• H03F 3/217 - Class D power amplifiers; Switching amplifiers
• H03F 3/45 - Differential amplifiers
• H04B 10/155 - Transmitters
• H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only

Abstract

A microelectromechanical detection structure (1; 1') for a MEMS resonant biaxial accelerometer (16) is provided with: an inertial mass (2; 2'), anchored to a substrate (30) by means of elastic elements (8) in such a way as to be suspended above the substrate (30), the elastic elements (8) enabling inertial movements of detection of the inertial mass (2; 2') along a first axis of detection (x) and a second axis of detection (y) that belong to a plane (xy) of main extension of said inertial mass (2; 2'), in response to respective linear external accelerations (ax, ay); and at least one first resonant element (10a) and one second resonant element (10b), which have a respective longitudinal extension, respectively along the first axis of detection (x) and the second axis of detection (y), and are mechanically coupled to the inertial mass (2; 2') through a respective one of the elastic elements (8) in such a way as to undergo a respective axial stress (N1, N2) when the inertial mass moves respectively along the first axis of detection (x) and the second axis of detection (y).

IPC Classes  ?

• G01P 15/097 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by vibratory elements
• G01P 15/18 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration in two or more dimensions

Abstract

A process for manufacturing a semiconductor device (10; 10') envisages the steps of: providing a semiconductor material body (2) having at least one deep trench (4) that extends through said body of semiconductor material starting from a top surface (2a) thereof; and filling the deep trench (4) via an epitaxial growth of semiconductor material, thereby forming a columnar structure (8) within the body of semiconductor material (2). The manufacturing process further envisages the step of modulating the epitaxial growth by means of a concurrent chemical etching of the semiconductor material that is undergoing epitaxial growth so as to obtain a compact filling free from voids of the deep trench (4); in particular, a flow of etching gas is introduced into the same reaction environment as that of the epitaxial growth, wherein a flow of source gas is supplied for the same epitaxial growth.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device

Abstract

The invention relates to a security system comprising at least one integrated circuit (24a) and a transceiver / transponder circuit (30), the at least one integrated circuit (24a) being provided with an antenna (36) for communicating with the transceiver / transponder circuit (30), an inhibiting element (24b, 44, 44a, 44b) being associated with the at least one integrated circuit (24a) for inhibiting communications with the transceiver / transponder circuit (30) and for securing the data contained in the at least one integrated circuit (24a). Advantageously, the inhibiting element (24b, 44, 44a, 44b) is an electromagnetic inhibiting element, the security system further comprising a coupling element (22) that is associated with the antenna (36) of the at least one integrated circuit (24a) for temporarily deactivating the electromagnetic inhibiting element (24b, 44, 44a, 44b) to allow communications between the at least one integrated circuit (24a) and the transceiver / transponder circuit (30).

IPC Classes  ?

• G06K 19/073 - Special arrangements for circuits, e.g. for protecting identification code in memory

Abstract

An integrated circuit (100) controls a switch (M) of a switching current regulator. The current regulator comprises primary (L1) and secondary (L2) windings where a first (Ip) and a second (Is) current flow, respectively. The switch (M) is adapted to initiate or interrupt the circulation of the first current (Ip) in the primary winding. The control integrated circuit (100) comprises a comparator (4) configured to compare a first signal (Vcs) representative of said first current to a second signal (Vcsref) and a divider circuit (7) configured to generate said second signal as a ratio of a third signal (A), proportional to a voltage on the primary winding, with a voltage on a capacitor (Ct). The capacitor (Ct) is charged by a further current controlled by the third signal (A) when the second current (Is) is different from zero and is discharged through a resistor (Rt) when the value of said second current is substantially zero.

IPC Classes  ?

• H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
• H02M 7/217 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

Abstract

Disclosed is an acoustic sensor (1), wherein a conductive vibrating membrane (14) and an upper fixed electrode plate (5) are arranged on the upper face of a silicon substrate (11) so that an air gap (22) is provided between the conductive vibrating membrane (14) and the upper fixed electrode plate (5), and impurities are added on the surface of the silicon substrate (11).

IPC Classes  ?

• H04R 19/04 - Microphones
• H04R 31/00 - Apparatus or processes specially adapted for the manufacture of transducers or diaphragms therefor

Abstract

In an acoustic sensor (11), a vibrating membrane (22) and a fixed membrane (23) are formed on the upper face of a semiconductor substrate, and an acoustic wave is detected by the change of capacitance between a vibration electrode (22a) of the vibrating membrane (22) and a fixed electrode (23a) of the fixed membrane (23). The fixed membrane(23) is provided with a plurality of sound holes (32) for delivering the acoustic wave from the outside to the vibrating membrane (22), and the fixed electrode (23a) is formed so that the boundary of the edge portion (40) does not intersect the sound holes (32).

IPC Classes  ?

• H04R 19/04 - Microphones

Abstract

An integrated control circuit of a switch is described, which is adapted to open or close a current path; said integrated circuit includes a comparator to compare a first signal with a second signal representative of the current flowing through said current path. The comparator outputs a third variable signal between a low logic level and a high logic level according to whether said second signal is lower than said first signal or vice versa; the integrated circuit has a driver to generate a signal to drive said switch in response to the third signal, and is configured to detect a spike on the leading edge of said second signal and to blank said third signal for a first blanking time period which depends on a turn-on delay of said switch and a second blanking period which depends on the duration of said spike on the leading edge of said second signal.

IPC Classes  ?

• H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only

Abstract

A method for manufacturing a semiconductor wafer (112) is provided. The method comprises providing a monocrystalline silicon wafer (102), epitaxially growing a first layer (108) of a first material on the silicon wafer (102), and epitaxially growing a second layer (110) of a second material on the first layer. Said first material is monocrystalline silicon carbide, and said second material is monocrystalline silicon.

IPC Classes  ?

• H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A testing system for carrying out electrical testing of at least a through via (10) extending, at least in part, through a substrate (3) of a body (2) of semiconductor material and having a first end (10b) buried within the substrate (3) and not accessible from the outside of the body (2). The testing system has an electrical test circuit (22) integrated in the body (2) and electrically coupled to the through via (10) and to electrical-connection elements (8) carried by the body (2) for electrical connection towards the outside; the electrical test circuit (22) has a buried microelectronic structure (28) integrated in the substrate (3) so as to be electrically coupled to the first end (10b) of the through via (10), thereby closing an electrical path within the substrate (3) and enabling detection of at least one electrical parameter of the through via (10) through the electrical-connection means (8).

IPC Classes  ?

• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

A transmission channel (1) is described comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVP0, HVP1, HVM0, HVM1), a clamping circuit (10) being connected to a first output terminal (HVout) of the transmission channel (1), an antinoise block (6) being connected between the first output terminal (HVout) and a connection terminal (Xdcr) of the transmission channel (1); as well as a switching circuit (30) being inserted between the connection terminal (Xdcr) and a second output terminal (LVout) of the transmission channel (1). Advantageously according to the invention, the clamping circuit (10) comprises a clamping core (11), a reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4 ) inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping circuit (10), the circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2 ) being in correspondance with conduction terminals of said transistors (MB1,MB2,MB3,MB4,MC1,MC2) comprised into the high voltage buffer block(4) and into the clamping circuit (10), and a switching circuit (30).

IPC Classes  ?

• H03K 17/06 - Modifications for ensuring a fully conducting state
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes
• B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
• H03K 17/0416 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit
• H03K 17/16 - Modifications for eliminating interference voltages or currents

Abstract

A low voltage isolation circuit (1) is described inserted between an input terminal (HVout) suitable for receiving a high voltage signal (IM) and an output terminal (pzt) suitable for transmitting the high voltage signal (IM) to a load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, -Vss) and comprising a first driving transistor (Ml), inserted between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted between the driving central circuit node (Xc) and the second supply voltage reference (-Vss) as well as an isolation block (8) connected to the connection terminal (pzt), to the input terminal (HVout) and, through a protection block (9) comprising a first and a second protection transistor (MD1, MD2), being in anti-series to each other and having control terminals receiving respective complementary protection driving signals (dr1, dr2), to the driving central circuit node (Xc), the isolation block (8) comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the input (HVout) and output (pzt) terminals of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc) through the protection block (9), said diode block (7) comprising at least one first and one second transmission diode (DN1, DN2), connected in antiparallel, i.e. by having an anode terminal of said first diode connected to a cathode terminal of said second diode and vice versa.

IPC Classes  ?

• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
• H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 17/06 - Modifications for ensuring a fully conducting state
• B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
• H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
• H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit

Abstract

A low voltage isolation switch (1) is described, inserted between an input terminal (HVout) suitable for receiving a high voltage signal (IM) and an output terminal (pzt) suitable for transmitting this high voltage signal (IM) to a load (PZ) of the type comprising at least one driving block (5) being inserted between a first and a second voltage reference (Vss, -Vss) and comprising a first driving transistor (M1), inserted, in series to a first driving diode (D1), between the first voltage reference (Vss) and a first driving central circuit node (Xd) and a second driving transistor (M2), in turn inserted, in series with a second driving diode (D2), between the driving central circuit node (Xd) and the second supply voltage reference (-Vss) as well as a control transistor (MD) connected across a diode block (7) comprising at least one first and one second transmission diode (DN1, DN2), connected in antiparallel, i.e. by having the anode terminal of the first diode connected to the cathode terminal of the second one and vice versa, between the input (HVout) and output (pzt) terminals of the low voltage isolation switch (1), this control transistor (MD) having a control terminal connected to the driving central circuit node (Xd) through a low voltage decoupling block (6), in turn inserted between a first and a second substrate terminal (SS1, SS2) and also comprising a first and a second parasite capacitive element (Par1, Par2) connected to these first and second substrate terminals (SS1, SS2) as well as comprising at least one first decoupling transistor (M3) and one second decoupling transistor inserted (M4), being in parallel to each other and having control terminals connected to the first and second parasite capacitive elements (Par1, Par2), respectively.

IPC Classes  ?

• H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
• H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes
• H03K 17/06 - Modifications for ensuring a fully conducting state
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
• H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit

Abstract

A clamping circuit (10) to a voltage reference (GND) is described, of the type comprising at least one clamping core (11) connected to an output terminal (HVout) and having a central node (XC) connected to the voltage reference (GND) and in turn including at least one first and one second clamp transistor (MC1; MC2), connected to the central node (XC) and having respective control terminals (XG1, XG2), the clamping core (11) being also connected at the input to a low voltage input driver block (13). Advantageously according to the invention, the clamping core (11) further comprises at least one first switching off transistor (MS1) connected to the output terminal (HVout) and to the first clamp transistor (MC1), as well as a second switching off transistor (MS2) connected to the output terminal (HVout) and to the second clamp transistor (MC2), these first and second clamp transistors (MC1, MC2) being high voltage MOS transistors of complementary type and these first and second switching off transistors (MS1, MS2) being high voltage MOS transistors of complementary type and connected to the first and second clamp transistors (MC1, MC2) by having the respective equivalent or body diodes in anti-series so as to close themselves when the clamping circuit (10) is active and to sustain positive and negative high voltages when the clamping circuit (10) is not active.

IPC Classes  ?

• H03K 17/06 - Modifications for ensuring a fully conducting state
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes
• B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy

Abstract

A switching circuit (30) is described being inserted between a connection terminal (Xdcr) and an output terminal (LVout) of a transmission channel (1) and of the type comprising at least one first and one second switching transistor (MSW1, MSW2) which are high voltage MOS transistors of complementary type inserted, in series to each other and by having respective equivalent or body diodes (DSW1, DSW2) in anti-series, between the connection terminal (Xdcr) and the output terminal (LVout). Advantageously according to the invention, the switching circuit comprises at least one bootstrap circuit (31) connected to respective first and second control terminals (XG1, XG2) of these at least one first and one second switching transistor (MSW1, MSW2), as well as to respective first and second voltage references (VDD_P, VDD_M) and having values of parasite capacities between these first and second control terminals (XG1, XG2) and at least one first and one second bootstrap node (XB1, XB2) of at least one order of magnitude lower with respect to the gate-source capacities (Csw1, Csw2) of these at least one first and one second switching transistor (MSW1, MSW2).

IPC Classes  ?

• H03K 17/0416 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit
• H03K 17/06 - Modifications for ensuring a fully conducting state
• H03K 17/16 - Modifications for eliminating interference voltages or currents
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy

Abstract

A transmission channel (1) is described of the type comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVPO, HVP1, HVMO, HVM1), these buffer transistors (MB1, MB2, MB3, MB4) being also connected to a clamping block (5), in turn comprising clamping transistors (MC1, MC2) connected to at least one output terminal (HVout) of this transmission channel through diodes (DC1, DC2) connected to prevent the body diodes of the clamping transistors (MC1, MC2) from conducting. Advantageously according to the invention, the transmission channel (1) comprises at least one reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4) and being inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping block (5), these circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) being in correspondence with conduction terminals of the transistors (MB l, MB2, MB3, MB4; MC1, MC2) comprised into the high voltage buffer block (4) and into the clamping block (5).

IPC Classes  ?

• H03K 17/0416 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit
• H03K 17/16 - Modifications for eliminating interference voltages or currents
• H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes
• B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy

Abstract

A MEMS transducer (1) has a micromechanical sensing structure (10) and a package (46). The package (46) is provided with a substrate (45), carrying first electrical-connection elements (47), and with a lid (25), coupled to the substrate to define an internal cavity (24), in which the micromechanical sensing structure (10) is housed. The lid (25) is formed by: a cap layer (20) having a first surface (20a) and a second surface (20b), set opposite to one another, the first surface (20a) defining an external face of the package (46) and the second surface (20b) facing the substrate (45) inside the package (46); and a wall structure (21), set between the cap layer (20) and the substrate (45), and having a coupling face (21a) coupled to the substrate (45). At least a first electrical component (10, 11) is coupled to the second surface (20b) of the cap layer (20), inside the package (46), and the coupling face (21a) of the wall structure (21) carries second electrical-connection elements (30), electrically connected to the first electrical component (10, 11) and to the first electrical-connection elements (47).

IPC Classes  ?

• H04R 19/00 - Electrostatic transducers
• B81B 7/00 - Microstructural systems

Abstract

Circuit (1) of a voltage controlled oscillator comprising: - a bridge structure including two cross-coupled transistors of N type (M3, M4) and two cross-coupled transistors of P type (M5, M6); - a current mirror (3) connected to the two cross-coupled transistors of N type (M3, M4) and arranged to generate a bias current (IB) for the circuit (1); - an LC resonator (2) placed in parallel between the two cross-coupled transistors of N type (M3, M4) and the two cross-coupled transistors of P type (M5, M6). The circuit (1) is characterised in that the LC resonator (2) comprises: two pairs of differential inductors (L1, L2) mutually coupled by means of a mutual inductance coefficient (M), each pair comprising a first inductor (L1) arranged on a respective branch (10a) of an external loop, and a second inductor (L2) arranged on a respective branch (12a) of an internal loop; a first varactor (Cv33) connected to a common node (A) and to a first branch (12a) of the internal loop; a second varactor (Cv33) connected to the common node (A) and to a second branch (12a) of the internal loop.

IPC Classes  ?

• H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
• H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS - Details

Abstract

The invention relates to a driving method for obtaining a linear gain variation of a transconductance amplifier, of the type comprising at least one differential transistor cell, with adjustment of a driving voltage value (Vtgc1) of a degenerative driving transistor (MD1) of said transconductance amplifier, comprising the steps of : generating an output current signal of a differential cell (11) being a copy of said differential transistor cell of said transconductance amplifier, said output current signal having a linear relationship with a transconductance value of said copy differential cell (11) as said driving voltage (Vtgc1) varies; generating a reference current signal having a linear relationship with a differential input voltage; comparing said output current signal and said reference current signal for adjusting said driving voltage value (Vtgc1) and modifying said transconductance value of said copy differential cell (11) up to a balance of said current signals.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers
• H03G 1/00 - CONTROL OF AMPLIFICATION - Details of arrangements for controlling amplification

Abstract

It is described a driving circuit (1) having at least one output terminal (OUT) connected to an ultrasonic pulse generator circuit and providing thereto with an output voltage (Vout), characterized in that it comprises at least one first portion (2A) connected to a first voltage reference (VPH) and including at least one first output transistor (MOP) being inserted between the first voltage reference (VPH) and the output terminal (OUT), such a first portion (2A) further comprising: at least one first high voltage comparator (3A) being connected to said output terminal (OUT) and to a first threshold voltage reference (VTHP), at least one first start-up circuit (4A) being controlled by a first setting signal (SETP); at least one first switching ON /OFF circuit (5A) being connected at its input to the first start-up circuit (4A), in correspondence with a first internal circuit node (XP), and to the first high voltage comparator (3A), in correspondence with a second internal circuit node (YP), and at its output to a control terminal of the first output transistor (MOP); the first start-up circuit (4A) providing a switching on signal (ONA) to the first switching on/ off circuit (5A) while the high voltage comparator (3A) provides a switching off signal (OFFA) to the first switching on/ off circuit (5A) which causes the switching off of the output transistor (MOP), the high voltage comparator (3A) generating the switching off signal (OFFA) when the output voltage (Vout) reaches a first desired supply voltage value which depends on the value of the first threshold voltage reference (VTHP).

IPC Classes  ?

• H03K 3/355 - Monostable circuits

Abstract

A lid for a MEMS device and the relative manufacturing method. The lid includes: a first board (20) with opposite first and second surfaces (20a, 20b) having first and second metal layers (21a, 21b) disposed thereon, respectively, wherein a through cavity (200) extends through the first board and the first and second metal layers; a second board (23) with opposite third and fourth surfaces (23a, 23b); an adhesive layer (22) sandwiched between the second surface of the first board and the third surface of the second board to couple the first and second boards together such that the through cavity is closed by the second board, thereby forming a recess (200); and a first conductor layer (25a) coating the bottom and the side surfaces (201a, 201b) of the recess. The lid enhances the shielding effect upon the MEMS device.

IPC Classes  ?

• B81B 7/00 - Microstructural systems

Abstract

Ring oscillator comprising a plurality of elementary units (5) connected in cascade and linked in order to make a chain with the respective output terminals (OUT) connected to the input terminals (IN) of the successive elementary units (5) of the chain, the elementary units (5) being crossed by a cyclic signal (CLK) during a time period (Δt) of activation, each of said elementary units (5) comprising an auxiliary recovery terminal (15) for temporarily resetting each elementary unit (5) during each loop of said cyclic signal (CLK), said auxiliary recovery terminal (15) being connected to an output terminal (OUT) of a successive elementary unit (5) of the chain.

IPC Classes  ?

• H03K 3/03 - Astable circuits
• H03K 23/54 - Ring counters, i.e. feedback shift register counters

Abstract

The invention relates to a High Voltage switch configuration (10) having an input terminal (IN) which receives an input signal (Vin) to drive a load and an output terminal (OUT) which issues an output signal (Vout) to the load. Advantageously according to the invention, the High Voltage switch configuration ( 10) comprises at least a first and a second diode (D1, D2), being placed in antiseries between said input and output terminals (IN, OUT) and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node (Xc1).

IPC Classes  ?

• H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes

Abstract

A process for manufacturing a MEMS device, wherein a bottom silicon region (4b) is formed on a substrate and on an insulating layer (3); a sacrificial region (5a) of dielectric is formed on the bottom region; a membrane region (21), of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug as far as the sacrificial region so as to form through trenches (15); the side wall and the bottom of the through trenches are completely coated in a conformal way with a porous material layer (16); at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity (18); and the through trenches are filled with filling material (20a) so as to form a monolithic membrane suspended above the cavity (18).

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

A resonant dc-dc converter for converting an input dc voltage to an output dc voltage is provided. The converter includes a switching circuit for receiving the input dc voltage and generating a periodic square wave voltage oscillating between a high value corresponding to the input dc voltage and a low value corresponding to a fixed voltage. The square wave voltage oscillates at a main frequency with a main duty cycle. The converter further includes a switching driving circuit for driving the switching circuit. The switching driving circuit includes a timing circuit for setting the main frequency and the main duty cycle of the square wave voltage. The timing circuit is configured to set the value of the main duty cycle to about 50% when the converter operates in steady state. The converter includes a conversion circuit based on a resonant circuit for generating the output dc voltage from the square wave voltage based on the main frequency and on the main duty cycle. The converter further includes a disabling circuit for temporarily halting the timing circuit after a power on of the converter in such a way to temporarily vary the main duty cycle of the square wave voltage during at least one period of the square wave voltage.

IPC Classes  ?

• H02M 3/337 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration

Abstract

A power supply circuit (30; 30'; 30'') for an electrical appliance (49), comprising a turning-on stage (32; 32') configured for determining a transition from a turned-off state, in which the power supply circuit (30; 30; 30) is off and does not supply electric power, to a turned-on state of the power supply circuit (30; 30'; 30''). The turning-on stage (32; 32') comprises a transducer (33; 36) of the remote-control type configured for triggering the transition in response to the reception of a wireless signal.

IPC Classes  ?

• H02M 1/36 - Means for starting or stopping converters

Abstract

A method for carrying out nucleic acid amplification, includes providing a reaction chamber (31), accommodating an array (36) of nucleic acid probes (37) at respective locations, for hybridizing to respective target nucleic acids; and introducing a solution (50) into the reaction chamber (31), wherein the solution (50) contains primers, capable of binding to target nucleic acids, nucleotides, nucleic acid extending enzymes and a sample including nucleic acids. The a structure of the nucleic acid probes (37) and of the primers so that a hybridization temperature (TH) of the probes (37) is higher than an annealing temperature (TA) of the primers, whereby hybridization and annealing take place in respective separate temperature ranges (RH, RA).

IPC Classes  ?

• C12Q 1/68 - Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions involving nucleic acids

Abstract

An integrated electronic device (1) having a body (9) of semiconductor material and a first antenna (3;3a) which enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna (3b,3c). The integrated electronic device (1) has a first via (4;4a- 4d;50;50a;53) of magnetic material arranged at least in part inside the body (9), which forms, in use, a communication channel between the first antenna (3;3a) and the further antenna (3b,3c).

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

In order to verify robustness in regard to electrical overstresses of an electronic circuit under test (DUT), the latter is exposed to electrical overstresses (12, 14), and the behaviour thereof following upon exposure to said electrical overstresses is monitored (18). Moreover, the electrical overstress is applied to the electronic circuit (DUT) when the electronic circuit (DUT) is in its normal applicational conditions of operation. In particular, there is envisaged both the testing of the electronic circuit (DUT) in dynamic conditions by causing it to be traversed by the currents that characterize operation thereof and by exposing at least one supply line (20) of said electronic circuit under test (DUT) to electrical overstresses and the testing of said electronic circuit under test (DUT) in static conditions, without causing it to be traversed by the currents that characterize operation thereof and by exposing to electrical overstresses both the supply (20) and the input and/or output lines of said electronic circuit under test (DUT). The device (14) for generating the overstresses can be mounted on a circuit board (12), which can be coupled as daughter board to a mother board (10), on which the electronic circuit under test (DUT) is mounted.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

The method for detecting the presence of liquids includes detecting an initial temperature (Tl) in a channel (9) accommodating a liquid; heating the channel for a predetermined test time (Δt2); detecting a test temperature (T2); determining a temperature variation (S) on the basis of the initial temperature, the test temperature, and the test time; and comparing the temperature variation with at least one threshold (Z). Before detecting an initial temperature, an ambient temperature is read, the channel is heated to the initial temperature, and is kept at the initial temperature for a time period.

IPC Classes  ?

• B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
• B01L 7/00 - Heating or cooling apparatus; Heat insulating devices
• G01N 35/00 - Automatic analysis not limited to methods or materials provided for in any single one of groups ; Handling materials therefor
• G01F 23/00 - Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm

Abstract

A semiconductor device includes at least one first component (5) (for example, a first integrated circuit), having a front face provided with electrical connection pads. The first component is embedded in a support layer (2) is a position such that the front face of the first component is not covered and lies parallel to a first face of the support layer. An intermediate layer (8) is formed on the front face of the first component and on the first face of the support layer. An electrical connection network (9) within the intermediate layer selectively connects to the electrical connection pads of the first component. The device further includes at least one second component (11) (for example, a second integrate circuit, having one face placed above the intermediate layer and provided with electrical connection pads selectively connected to the electrical connection network. Electrical connection vias (17) pass through the support layer and selectively connect the electrical connection network to an external electrical connection formed on a second face of the support layer.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

Abstract

The invention relates to a method for an improved checking of repeatability and reproducibility of a measuring chain, in particular for the quality control by means of the semiconductor device testing, wherein testing steps are provided for multiple and different devices to be subjected to measurement through a measuring system comprising at least one concatenation of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement. Advantageously, the method comprises the following steps: checking repeatability and reproducibility of each type of unit that forms part of the measuring chain of the concatenation; then making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement.

IPC Classes  ?

• G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

Bistable carbazole compounds of formula (I) are described, wherein M is Fe, Co, Ru or Os, preferably Fe, useful as basic functional units for computing systems based on the QCA (Quantum Cellular Automata) paradigm; a process for their preparation is also described.

IPC Classes  ?

• C07F 17/02 - Metallocenes of metals of Groups 8, 9 or 10 of the Periodic System
• G06N 99/00 - Subject matter not provided for in other groups of this subclass

Abstract

The present invention relates to a circuit architecture for the parallel supplying of power during an electric or electromagnetic testing, such as EMWS or EWS or WLBI testing, of a plurality of electronic devices (2) each integrated on a same semiconductor wafer (1) wherein the electronic devices (1) are neatly provided on the semiconductor wafer (1) through integration techniques and have edges (5) bounded by separation scribe lines (7). Advantageously according to the invention, the circuit architecture comprises: - at least one conductive grid (4), interconnecting at least one group of the electronic devices (2) and having a portion being external (14) to the devices of the group and a portion being internal (13) to the devices of the group; the external portion (14) of the conductive grid (4) being extended also along the separation scribe lines (7); the internal portion (13) being extended within at least a part of the devices of the group; interconnection pads (6) between the external portion (14) and the internal portion (13) of the conductive grid (4) being provided on at least a part of the devices of the group, the interconnection pads (6) forming, along with the internal and external portions, power supply lines which are common to different electronic devices (2) of the group.

IPC Classes  ?

• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

A probe card (105') adapted for testing at least one integrated circuit integrated on corresponding at least one die (145) of a semiconductor material wafer, the probe card including a board (125') adapted for the coupling to a tester apparatus, and a plurality of probes (225) coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units (135'), each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test (145), the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

IPC Classes  ?

• G01R 1/073 - Multiple probes

Abstract

In a reliable method and a relative circuit for monitoring the powering of a remote device through a LAN it is not necessary to generate an extra biasing voltage higher than the DC power supply voltage. As in known power distribution systems, the DC voltage used for supplying the remote device is applied to the LAN line and at the same time an AC voltage is applied to the same line for monitoring whether the remote device is connected or not to the LAN line. However, differently from prior techniques, the DC voltage is applied to a first or 'high' terminal and the AC voltage is applied to the other or 'low' terminal of the LAN line through a decoupling capacitor. This arrangement makes possible to supply the remote device with the largest possible DC voltage compatible with a fully integrated AC signal generator, disconnection detector and PSE controller and enhances the reliability of recognition of whether the powered device is connected to or disconnected from the LAN line.

IPC Classes  ?

• H04L 12/10 - Current supply arrangements

Abstract

PDs that can be supplied through the LAN line are discriminated from PDs that cannot be so supplied in function of the resistance of the supply line and of the voltage drop Vdrop caused by nonlinear elements in series therewith. The values of these two parameters are estimated by applying two distinct voltages to the supply terminals of the LAN line and sensing the relative steady-state currents absorbed by the power supply line and by processing voltage and current values for estimating the resistance (Rdet) of the line and the voltage drop (Vdrop) caused by nonlinear elements connected in series therewith.

IPC Classes  ?

• H04L 12/10 - Current supply arrangements

Abstract

An electrostatic micromotor (10') is provided with a fixed substrate (12), a mobile substrate (13) facing the fixed substrate (12), and electrostatic-interaction elements (14, 15, 17) enabling a relative movement of the mobile substrate (3) with respect to the fixed substrate (2) in a movement direction (x); the electrostatic micromotor is also provided with a capacitive position-sensing structure (18') configured to enable sensing of a relative position of the mobile substrate (13) with respect to the fixed substrate (12) in the movement direction (x). The capacitive position-sensing structure (18') is formed by at least one sensing indentation (22), extending within the mobile substrate (13) from a first surface (13a; 13b) thereof, and by at least one first sensing electrode (24), facing, in at least one given operating condition, the sensing indentation (22).

IPC Classes  ?

• H02N 1/00 - Electrostatic generators or motors using a solid moving electrostatic charge carrier

IPC Classes  ?

• H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• H04L 27/26 - Systems using multi-frequency codes

Abstract

Electronic device (1, 1a, 1b, 1c, 1d, 1e) which comprises: a substrate (2) provided with at least one passing opening (5), a MEMS device (7) with function of differential sensor provided with a first and a second surface (9, 10) and of the type comprising at least one portion (11) sensitive to chemical and/or physical variations of fluids present in correspondence with a first and a second opposed active surface (11a, 11b) thereof, the first surface (9) of the MEMS device (7) leaving the first active surface (11a) exposed and the second surface (10) being provided with a further opening (12) which exposes said second opposed active surface (11b), the electronic device (1, 1d, 1e) being characterised in that the first surface (9) of the MEMS device (7) faces the substrate (2) and is spaced therefrom by a predetermined distance, the sensitive portion (11) being aligned to the passing opening (5) of the substrate (2), and in that it also comprises: a protective package (14, 14a, 14b), which incorporates at least partially the MEMS device (7) and the substrate (2) so as to leave the first and second opposed active surfaces (11a, 11b) exposed respectively through the passing opening (5) of the substrate (2) and the further opening (12) of the second surface (10).

IPC Classes  ?

• B81B 7/00 - Microstructural systems
• G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
• G01L 13/02 - Devices or apparatus for measuring differences of two or more fluid pressure values using elastically-deformable members or pistons as sensing elements
• G01D 11/24 - Housings

Abstract

A regulation and shaping circuit comprising a first input terminal (405) for receiving a first input signal (Vref) with a first frequency; a second input terminal (410) for receiving a second input signal (Vin1) with a second frequency higher than the first frequency; a first circuital branch (420) coupled to the first input terminal and, through first coupling means (Z2) active at the first frequency, to an output terminal (415) for providing an output signal (Vout1); a second circuital branch (425) coupled to the second input terminal and to the output terminal, wherein said second circuital branch comprises a negative feedback circuital loop (430, 435) adapted to control the output signal according to the second input signal.

IPC Classes  ?

• H04L 25/49 - Transmitting circuits; Receiving circuits using three or more amplitude levels

Abstract

An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN') input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

IPC Classes  ?

• H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
• H03F 3/45 - Differential amplifiers

Abstract

An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (CI) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (Cpi). The device also comprises a charging and discharging device (SWCPIR, SWG) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.

IPC Classes  ?

• H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements

Abstract

Herein described is a control device of a device for the correction of the power factor in forced switching power supplies; said device for the correction of the power factor comprises a converter (20) and said control device (1) is coupled to the converter to obtain from an alternating input line voltage (Vin) a regulated output voltage (Vout) . The control device (1) comprises generating means (421-423) associated to a capacitor (Cf f) for generating a signal (Vff) representative of the root-mean- square value of the alternating line voltage; the generating means (421-424) are associated to means for discharging (Rf f) said capacitor. The control device comprises further means for discharging (Ml, COMPl, Cl; Ml 6, COMPI 1, CI 1; M50, COMP22, C0MP33, Cint) the capacitor (Cf f) suitable for discharging said capacitor when the signal (Vff) representative of the root-mean- square value of the alternating line voltage goes below a given value (VCl, VCI 1, Vint) .

IPC Classes  ?

• G05F 1/70 - Regulating power factor; Regulating reactive current or power
• H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

Abstract

A control device for a power factor correction device in forced switching power supplies is disclosed; the device for correcting the power factor comprises a converter (20) and said control device (1) is coupled with the converter to obtain from an input alternating line voltage (Vin) a regulated output voltage (Vout). The converter (20) comprises a power transistor (M) and the control device (1) comprises a driving circuit (3, 4, 6, 10) of said power transistor; the driving circuit comprises a timer (130) suitable for setting the switch-off period of said power transistor (M). The timer is coupled with the alternating line voltage (Vin) in input to the converter and is suitable for determining the switch-off period of the power transistor in function of the value of the alternating line voltage (Vin) in input to the converter.

IPC Classes  ?

• G05F 1/70 - Regulating power factor; Regulating reactive current or power
• H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

Abstract

Described herein is a microelectromechanical device (10) having a mobile mass (12) that undergoes a movement, in particular a spurious movement, in a first direction (z) in response to an external event; the device moreover has a stopper structure (14, 20) configured so as to stop said spurious movement. In particular, a stopper element (20) is fixedly coupled to the mobile mass (12) and is configured so as to abut against a stopper mass (14) in response to the spurious movement, thereby stopping it. In detail, the stopper element (20) is arranged on the opposite side of the stopper mass (14) with respect to a direction of the spurious movement, protrudes from the space occupied by the mobile mass (12) and extends in the space occupied by the stopper mass, in the first direction (z).

IPC Classes  ?

• B81B 7/00 - Microstructural systems
• G01P 15/08 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values

Abstract

A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.

IPC Classes  ?

• H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
• G11C 16/02 - Erasable programmable read-only memories electrically programmable

Abstract

The present invention- relates to the use of a nitroaniline derivative of Formula I for the production of nitric oxide and for the preparation of a medicament for the treatment of a disease wherein the administration of nitric oxide is beneficial. The present invention furthermore relates to a method for the production of NO irradiating a nitroaniline derivative of Formula I, a kit comprising a nitroaniline derivative of Formula I and a carrier and to a system comprising a source of radiations and a container associated to a nitroaniline derivative of Formula I. In Formula I, R and RI are each independently hydrogen or a C1-C3 alkyl group; RII is hydrogen or an alkyl group.

IPC Classes  ?

• C01B 21/24 - Nitric oxide (NO)
• A61K 33/00 - Medicinal preparations containing inorganic active ingredients
• B01J 19/12 - Processes employing the direct application of electric or wave energy, or particle radiation; Apparatus therefor employing electromagnetic waves

Abstract

A wireless communication network, such as a IEEE 802.11 WLAN, includes an access point (AP) and a plurality of stations (STAl, STA2). The Access Point (AP) sends towards the stations (STAl, STA2) periodic information arranged in time frames or beacon intervals. The stations (STAl, STA2) in the network are configured to communicate: - in a first mode, called Infrastructure Mode (IM), through the access point (AP), and - in a second mode, called Direct Link Mode (DLM), directly with each other. The time frames are partitioned into: - a first time interval (IM_SI) wherein the stations (STAl, STA2) communicate in the first mode over a first channel; - a second time interval (DLM_SI) wherein the stations (STAl, STA2) communicate in the second mode over a second channel/ and - a third time interval (MIXED_SI) wherein the stations (STAl, STA2) communicate in either of the first (IM) or the second (DLM) mode.

IPC Classes  ?

• H04L 12/28 - Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]

Abstract

A system for decoding a stream of compressed digital video images (IS) comprises a graphics accelerator (152 to 158) for reading (152) the stream of compressed digital video images, creating (154, 156), starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting (158, 160) the three-dimensional scenes to be rendered into decoded video images (OS). The graphics accelerator (152 to 158) is preferentially configured as pipeline (102) selectively switchable between operation in a graphics context and operation for decoding the stream of video images (IS) . The graphics accelerator (152 to 158) is controllable during operation for decoding the stream of compressed digital video images (IS) via a set of Application Programmer's Interfaces (APIs) comprising, in addition to new APIs, also standard APIs for operation of the graphics, accelerator (152 to 158) in a graphics context.

IPC Classes  ?

• H04N 7/26 - using bandwidth reduction (information reduction by code conversion in general H03M 7/30)
• G06T 15/00 - 3D [Three Dimensional] image rendering

Abstract

A control device of a plurality of switching converters (Convl.ConvN) is disclosed; each converter comprises at least one power switch and is associated with a control circuit (Mod1 ...ModN) of the at least one power switch. The control device comprises means (100) suitable for comparing a signal (CTRL) representative of the load of the plurality of converters (ConvL.ConvN) with a plurality of reference signals (Vref1 ...Vref(N-l)) and suitable for enabling or disabling at least one of said plurality of control circuits (Mod1...ModN) in response to said comparison.

IPC Classes  ?

• H02J 1/10 - Parallel operation of dc sources
• H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

In a microfluidic assembly (20), a microfluidic device (1') is provided with a body (4) in which at least a first inlet (7) for loading a fluid to analyse and a buried area (8) in fluidic communication with the first inlet (7) are defined. An analysis chamber (10') is in fluidic communication with the buried area (8) and an interface cover (23) is coupled in a fluid-tight manner above the microfluidic device (1'). The interface cover (23) is provided with a sealing portion (35) in correspondence to the analysis chamber (10'), adapted to assume a first configuration, at rest, in which it leaves the analysis chamber (10') open, and a second configuration, as a consequence of a stress, in which it closes in a fluid-tight manner the same analysis chamber.

IPC Classes  ?

• B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers

Abstract

A process for preparing a semiconductor substrate for biological analysis in an integrated device, the biological analysis comprising the steps of amplifying DNA and detecting amplified DNA in the same chamber, comprises the steps of a) forming a silicon dioxide surface on said semiconductor substrate b) treating said silicon dioxide surface with a silane; c) forming a silanized surface; d) grafting nucleic acid probes; e) treating said silanized surface with a deactivating agent and f) forming a deactivated substrate sequentially. Further the process can include the step of cleaning the silicon dioxide substrate before the step of treating said silicon dioxide surface with a silane and the step of reacting the terminal group of the silane with a cross-linker or alternatively the step of reacting the derivatized nucleic acid probes with a cross-linker, before the grafting step.

IPC Classes  ?

• C12Q 1/68 - Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions involving nucleic acids