A method includes transmitting a plurality of signal frames from a master device over a serial communication bus at a constant rate to a first slave device from a set of slave devices. The set of slave devices and the master device are connected in series within a master-slave communication ring. The first slave device is coupled to at least one light source. The method further includes transmitting the plurality of signal frames from the first slave device to a second slave device from the set of slave devices.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
2.
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO INTERCONNECT STRUCTURES
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/14 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A method includes using a thermistor as a temperature sensor and connecting a pull-up resistor in series to the thermistor in a voltage divider circuit. The pull-up resistor is fabricated in an integrated circuit and includes a series of resistor segments connected to selectable voltage output tabs. The method further includes selecting an output voltage tab for a selected resistance segment having a selected resistance value to match a target resistance value for the pull-up resistor that is smaller than the as-fabricated resistance value of the pull-up resistor, calculating a ratio of a voltage on the thermistor and a voltage on the selected output voltage tab in the voltage divider circuit, and mapping the calculated ratio to a temperature value of the thermistor based on a temperature-resistance relationship of the thermistor in combination with the target resistance value of the pull-up resistor.
G01K 7/22 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a non-linear resistance, e.g. thermistor
G01K 7/24 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit
Implementations of a substrate carrier may include: a top ring configured to enclose an edge of a first side of a substrate; and a bottom support configured to enclose an entire second side and an edge of the second side of the substrate.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
5.
RC TIME BASED LOCKED VOLTAGE CONTROLLED OSCILLATOR
Circuits and processes for locking a voltage-controlled oscillator (VCO) at a high frequency signal are described. A circuit may include a voltage-controlled oscillator configured to generate a high frequency signal based on a control signal, a dummy load parallel to the voltage-controlled oscillator and configured to receive the control signal via a switch, and a digital-to-analog converter coupled to the voltage-controlled oscillator where the control signal is generated based on an output of the digital-to-analog converter.
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
H03L 7/00 - Automatic control of frequency or phase; Synchronisation
In some aspects, the techniques described herein relate to a semiconductor device including: a package including a plurality of pins; a semiconductor die including: a first bond pad; a second bond pad; and a pass transistor having: a drain terminal electrically coupled with the first bond pad; and a source terminal electrically coupled with the second bond pad; a first bond wire extending between a pin of the plurality of pins and the first bond pad; and a second bond wire extending between the pin and the second bond pad, the pass transistor being configured to facilitate detection of at least one of: lack of electrical continuity between the pin and the first bond pad; or lack of electrical continuity between the pin and the second bond pad.
A driver circuit includes an output terminal adapted for driving a data signal through a coupling capacitor to an external device. A first transistor is employed to drive the signal, and an N-type metal-oxide semiconductor (NMOS) transistor couples power to the first transistor. The NMOS transistor includes a first terminal connected to a positive terminal of a voltage supply, a second terminal coupled to an output terminal through a termination resistor, a gate terminal, and a bulk terminal connected to the negative terminal of the voltage supply. A charge pump circuit supplies a voltage to a gate terminal of the NMOS transistor, and is operable to provide a first voltage higher than that of the voltage supply to activate the NMOS device, and, responsive to detecting a ramp-down of the supply voltage, transition to providing the supply voltage to the NMOS device gate terminal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Implementations of a semiconductor device may include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device may include a trench channel adjacent to the trench and two doped pillars of a second conductivity type extending on each side of the first conductivity type doped pillar where a ratio of a depth of each of the two second conductivity type doped pillars to a depth of the trench into the substrate material may be at least 1.6 to 1.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A sensor circuit includes a transimpedance amplifier, a feedback network, and a readout circuit. The transimpedance amplifier has a first input for receiving a measured signal, a second input for receiving a reference signal, and an output. The feedback network includes a capacitor and a variable resistor each coupled between the output and the first input of the transimpedance amplifier. The readout circuit is coupled to the feedback network and has an output for providing a readout signal. In a conversion mode, the readout circuit provides the readout signal based on one sample of the output of the transimpedance amplifier. In an integration mode, the readout circuit provides the readout signal based on a plurality of samples of the output of the transimpedance amplifier.
A61B 5/0537 - Measuring body composition by impedance, e.g. tissue hydration or fat content
H03F 3/08 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
A61B 5/145 - Measuring characteristics of blood in vivo, e.g. gas concentration, pH-value
A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons
10.
BANDGAP CIRCUIT WITH NOISE REDUCTION AND TEMPERATURE STABILITY
A bandgap reference circuit includes a complimentary to absolute temperature (CTAT) current generator providing a CTAT current with a source degeneration resistor, and a proportional to absolute temperature (PTAT) current generator providing a PTAT current. The PTAT current generator includes a first branch with a source degeneration resistor, a first p-type metal-oxide semiconductor (PMOS) transistor, and a first n-type metal oxide semiconductor (NMOS) transistor, a resistor, and a diode-connected transistor. A second branch includes a source degeneration resistor, a second PMOS transistor, a second NMOS transistor, and a diode-connected transistor. The second branch coupled to the first branch in a current mirror configuration. A chopper circuit alternately couples drain terminals of the first and second PMOS transistors in series to the remainder of their respective branches.
In an aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and forming a first semiconductor layer within the trench and along the sidewall. In an embodiment, the process can further include forming a barrier layer within the trench after forming the first semiconductor layer; forming a second semiconductor layer within the trench after forming the barrier layer, wherein within the trench, first and second portions of the second semiconductor layer contact each other adjacent to a vertical centerline of the trench; and exposing the second semiconductor layer to radiation sufficient to allow a void within second semiconductor layer to migrate toward the barrier layer. In another embodiment, after forming a semiconductor within the trench, the process can further include forming an insulating layer that substantially fills a remaining portion of the trench.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
Implementations of a semiconductor device may include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device may include a trench channel adjacent to the trench and two doped pillars of a second conductivity type extending on each side of the first conductivity type doped pillar where a ratio of a depth of each of the two second conductivity type doped pillars to a depth of the trench into the substrate material may be at least 1.6 to 1.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 21/76 - Making of isolation regions between components
Anti-blooming control in overflow image sensor pixel. At least one example is an image sensor pixel comprising: a photodetector positioned in a semiconductor substrate; a gate oxide layer positioned on the semiconductor substrate; a floating diffusion; a transfer gate positioned on the gate oxide layer; a first anti-blooming implant positioned in the semiconductor substrate, wherein the first anti-blooming implant is coupled to the photodetector and the floating diffusion; and a second anti-blooming implant positioned in the semiconductor substrate, wherein the second anti-blooming implant is coupled to the photodetector and a voltage source contact.
H04N 25/621 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
14.
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A COMPONENT STRUCTURE ADJACENT TO A TRENCH
A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and QRR may be achieved, leading to lower switching losses.
A vernier sensor including a coarse sensor and a fine sensor may require calibration to ensure accurate position measurements. Calibration may include determining coefficients for harmonics that can be added to the coarse sensor output and the fine sensor output to reduce harmonic distortion. The disclosure describes using the offset and variance of a difference signal as the basis for calibration. This approach is possible at least because the frequencies of the coarse sensor and fine sensor can be selected to reduce the complexity of these calculations.
G01D 18/00 - Testing or calibrating apparatus or arrangements provided for in groups
G01D 5/22 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature differentially influencing two coils
Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.
In one general aspect, an apparatus can include a substrate (110, 410) having a semiconductor region (112, 122), and a trench (10, 40) defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode (130, 430) disposed in the trench and insulated from the sidewall of the trench by a shield dielectric (SD10), the shield dielectric having a low-k dielectric portion (LK10, LK40) and a high-k dielectric portion (HK10, HK40). The apparatus can include a gate electrode (120, 420) disposed in the trench and at least partially surrounded by a gate dielectric (GD10, GD40), and an inter-electrode dielectric (IE10, IE40) disposed between the shield electrode and the gate electrode.
A tuning circuit for a near-field magnetic induction (NFMI) system suitable for near field communication (NFC) is disclosed. The NFMI system includes a tuning circuit that is configured to measure a phase across a series capacitor coupled between a resonant circuit and a transmit circuit in order to determine a resonant condition of the resonant circuit. When the resonant condition is above resonance or below resonance, the tuning circuit can tune an adjustable capacitor of the resonant circuit. The tuning can continue until the phase measurement indicates that the resonant circuit is at resonance. The phase-based tuning allows for the tuning to operate continuously and concurrently with NFC.
H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
H04B 5/02 - Near-field transmission systems, e.g. inductive loop type using transceiver
20.
Semiconductor Devices with Single-Photon Avalanche Diodes and Light Scattering Structures
An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. The light scattering structures may include a low-index material formed in trenches in the semiconductor substrate. One or more microlenses may focus light onto the semiconductor substrate. Areas of the semiconductor substrate that receive more light from the microlenses may have a higher density of light scattering structures to optimize light scattering while mitigating dark current.
H01L 31/055 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means where light is absorbed and re-emitted at a different wavelength by the optical element directly associated or integrated with the PV cell, e.g. by using luminescent material, fluorescent concentrators or up-conversion arrangements
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/0232 - Optical elements or arrangements associated with the device
G02B 3/06 - Simple or compound lenses with non-spherical faces with cylindrical or toric faces
21.
METHODS AND APPARATUS FOR A TRACK AND HOLD AMPLIFIER
Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03G 1/00 - CONTROL OF AMPLIFICATION - Details of arrangements for controlling amplification
H03K 5/08 - Shaping pulses by limiting, by thresholding, by slicing, i.e. combined limiting and thresholding
A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Described implementations provide wireless, surface mounting of at least two semiconductor die on die attach pads (DAPs) of the semiconductor package, where the at least two semiconductor die are electrically connected by a clip. A stress buffer layer may be provided on the clip, and a heatsink may be provided on the stress buffer layer. The heatsink may be secured with an external mold material.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
A method includes disposing a first direct bonded metal (DBM) substrate substantially parallel to a second DBM substrate a distance apart to enclose a space. The method further includes disposing at least a semiconductor die in the space, and bonding the semiconductor die to the first DBM substrate using a first adhesive layer without an intervening spacer block between the semiconductor die and the first DBM substrate, and bonding the semiconductor die to the second DBM substrate using a second adhesive without an intervening spacer block between the semiconductor die and the second DBM substrate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
25.
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
In an example, a semiconductor device includes a first steering diode and a second steering diode at a top side of a region of semiconductor material, a first Zener diode buried within the region of semiconductor material, and a second Zener diode at a bottom side of the region of semiconductor material. The semiconductor device is configured as a bi-directional electrostatic discharge (ESD) structure. The first Zener diode and the first steering diodes are configured to respond to a positive ESD pulse, and the second Zener diode and the second steering diode are configured to respond to a negative ESD pulse. The steering diodes are configured to have low capacitances and the Zener diodes are configured to provide enhanced ESD protection. Other related examples and methods are disclosed herein.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
In one general aspect, an apparatus can include a substrate having a semiconductor region, and a trench defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode disposed in the trench and insulated from the sidewall of the trench by a shield dielectric, the shield dielectric having a low-k dielectric portion and a high-k dielectric portion. The apparatus can include a gate electrode disposed in the trench and at least partially surrounded by a gate dielectric, and an inter-electrode dielectric disposed between the shield electrode and the gate electrode.
A position of a target is determined using a linear inductive position sensor that includes a target coil, an excitation coil, two sensors and a Vernier processor. The sensors each include two or more receive coils. The receive coils include multiple twisted loops. In the first sensor, the coils have a first period, with loops offset by first distance. In the second sensor, the coils have a second period, with loops offset by a second distance. The target coil width is a function of the first distance and the second distance. During operation, the coils output voltages in which third, fifth and/or seventh harmonics are cancelled. Based on the voltages, the sensors output respective first and second position signals, from which the Vernier processor calculates the target’s position along an axis of the position sensor.
G01B 7/00 - Measuring arrangements characterised by the use of electric or magnetic techniques
G01D 5/20 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
28.
HEARABLES AND HEARING AIDS WITH PROXIMITY-BASED ADAPTATION
An illustrative wearable hearing device or hearing aid includes: a speaker that converts a reproduced signal into reproduced audio; a microphone that converts ambient audio into a receive signal, the ambient audio potentially including a feedback component; a feedback filter that filters the reproduced signal to obtain an estimated feedback component; a combiner that derives the reproduced signal from the receive signal at least in part by subtracting the estimated feedback component; and a controller that, subject to an adaptation rate, adjusts coefficients of the feedback filter to at least partially cancel the feedback component, the controller varying the adaption rate based at least in part on one or more proximity sensor signals.
A system for attaching a terminal pin to a circuit trace on an electronic substrate. The system includes a sonotrode and a stage for holding the electronic substrate. The sonotrode is configured to direct ultrasound energy to a base region of the terminal pin placed on the circuit trace to weld the base region to the circuit trace. The system further includes a three-dimensional positioner coupled to the sonotrode. The three-dimensional positioner is configured to drive the sonotrode to lift the terminal pin from a rack and to place the terminal pin on the electronic substrate.
H01R 12/73 - Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.
Multi-port power adapters. At least one example is a method including: supplying a first bus voltage to a first device by way of a DC-DC converter coupled to a link voltage; supplying a second bus voltage to a second device by way of a second DC-DC converter coupled to the link voltage; converting an AC voltage to the link voltage by way of an AC-DC converter; selecting, by a shunt regulator, a setpoint for the link voltage based on the first bus voltage and the second bus voltage; and regulating the link voltage to the setpoint by the AC-DC converter.
A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.
Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
34.
IMAGE PIXELS HAVING IR SENSORS WITH REDUCED EXPOSURE TO VISIBLE LIGHT
Image pixels having IR sensors with reduced exposure to visible light. One example is an image sensor comprising: a photosensitive region; a lower optical filter above the photosensitive region, and the lower optical filter configured to filter visible light and to pass infrared light; and an upper optical filter above the lower optical filter, and the upper optical filter configured to filter visible light and to pass infrared light.
Imaging systems, and image pixels and related methods. At least one example is an image sensor comprising a plurality of image pixels. Each image pixel may comprise: a color router defining a router collection area on an upper surface; a first photosensitive region beneath the color router; a second photosensitive region beneath the color router; and a third photosensitive region beneath the color router. The color router may be configured to route photons of a first wavelength received at the router collection area to the first photosensitive region, route photons of a second wavelength received at the router collection area to the second photosensitive region, and route photons of a third wavelength received at the router collection area to the third photosensitive region.
H04N 25/131 - Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements including elements passing infrared wavelengths
36.
IMAGE SENSOR AMPLIFIERS WITH REDUCED INTER-CIRCULATION CURRENTS
An image sensor may include an array of image sensor pixels. The array of image sensor pixels may be controlled by row driver circuitry. The row driver circuitry may include row drivers that receive power supply signals from transconductance amplifier circuitry. The transconductance amplifier circuitry may include multiple amplifiers with output ports shorted to one another. Each amplifier may include input transistors, cross-coupled transistors with a low threshold voltage, and additional transistors coupled in series with the cross-coupled transistors and having a moderate or high threshold voltage.
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
In one general aspect, an apparatus can include a first module including a first semiconductor die, and a first heatsink coupled to the first module where the first heatsink includes a substrate and a first plurality of protrusions. The apparatus can also include a second module including a second semiconductor die, and a second heatsink coupled to the second module and including a second plurality of protrusions. The apparatus can also include a cover defining a channel where the first plurality of protrusions of the first heatsink and the second plurality of protrusions of the second heatsink are disposed within the channel.
Implementations of image sensor packages may include: an image sensor die including a first largest planar side and a second largest planar side; an optically transmissive cover including a first largest planar side and a second largest planar side where the second largest planar side coupled to the first largest planar side of the image sensor die using an adhesive; and a light block material that fully covers edges of the image sensor die located between the first largest planar side and the second largest planar side of the image sensor die and fully covers edges of the optically transmissive cover between the first largest planar side and the second largest planar side of the optically transmissive cover. The light block material may extend across a portion of the first largest planar side and second largest planar side of the optically transmissive cover.
Switching circuits, half-bridge power converters, and methods for operating a switching circuit including a switching transistor coupled to a load. The method includes applying, with a driver, a gate voltage to the switching transistor. The method also includes generating, with a feedback capacitor, a feedback current based on a change in a voltage sensed at a drain terminal of the switching transistor when the switching transistor turns on. The method further includes applying the feedback current to the driver to limit the gate voltage applied to the switching transistor. The method also includes adjusting, with a controller, a switching slew rate of the switching transistor by draining an amount of the feedback current.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H03K 17/16 - Modifications for eliminating interference voltages or currents
40.
STRAY INDUCTANCE REDUCTION IN POWER SEMICONDUCTOR DEVICE MODULES
In general aspect, a module can include a substrate having a semiconductor circuit implemented thereon, and a negative power supply terminal electrically coupled with the semiconductor circuit via the substrate. The negative power supply terminal includes a connection tab arranged in a first plane. The module also includes a first positive power supply terminal electrically and a second positive power supply terminal that are coupled with the semiconductor circuit via the substrate. The first positive power supply terminal being laterally disposed from the negative power supply terminal, and including a connection tab arranged in the first plane. The second positive power supply terminal is laterally disposed from the negative power supply terminal and arranged in the first plane, such that the negative power supply terminal is disposed between the first positive power supply terminal and the second positive power supply terminal.
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
41.
CURRENT SENSE CIRCUIT HAVING A TEMPERATURE COMPENSATED RESPONSE
A package for a current sense circuit may include a lead-frame having a shunt resistance configured to generate a shunt voltage, which can be used to measure a current through the lead-frame. The shunt resistance associated with the lead-frame may be highly variable with temperature, which can cause errors in the current measurement. Accordingly, a current sense circuit can include an amplifier with an input resistor having a composite temperature coefficient configured to match a lead-frame temperature coefficient so that an output of the amplifier is compensated to remove variations in the shunt resistance of the lead-frame due to temperature.
G01R 1/20 - Modifications of basic electric elements for use in electric measuring instruments; Structural combinations of such elements with such instruments
Multiphase power converter with CLC resonant circuit. One example is a method of operation a power converter, the method including: charging, during a first on-time, a first output inductor by way of a first switching-tank circuit defining a first switch node coupled to a first lead of a resonant inductor; creating, during the first on-time, a first current flow into the first switching-tank circuit through the resonant inductor; and then charging, during a second on-time, a second output inductor by way of a second switching-tank circuit defining a second switch node coupled to a second lead of the resonant inductor; and creating, during the second on-time, a second current flow into the second switching-tank circuit through the resonant inductor.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
43.
INSULATED GATED FIELD EFFECT TRANSISTOR STRUCTURE HAVING SHIELDED SOURCE AND METHOD
A semiconductor device includes a region of semiconductor material of a first conductivity type. A body region of a second conductivity type is in the region of semiconductor material. The body region includes a first segment with a first peak dopant concentration, and a second segment laterally adjacent to the first segment with a second peak dopant concentration. A source region of the first conductivity type is in the first segment but not in at least part of the second segment. An insulated gate electrode adjoins the first segment and is configured to provide a first channel region in the first segment, adjoins the second segment and is configured to provide a second channel region in the second segment, and adjoins the source region. During a linear mode of operation, current flows first in the second segment but not in the first segment to reduce the likelihood of thermal runaway.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Transistor structures for a transistor may include a first source-drain region, a second source-drain region, and a channel region between the first and second source-drain regions overlapped by a gate structure. Transistor structures may be formed in a well of a first doping type. Isolation structures having the first doping type may be formed within the well. A lightly doped implant region of a second doping type for each of the source-drain regions may be formed within the well and separated from the isolation structures. A heavily doped surface implant region of the first doping type may extend across the surface of the well and cover the lightly doped implant region of each source-drain region. The surface implant region may be formed by patterning or by a blanket implantation process across the transistor structures.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Active noise cancellation systems, components, and methods are provided with single-source forward cancellation using a direction-dependent filter response. One illustrative active sound cancelling device includes: a primary external microphone that produces a primary receive signal; a secondary external microphone that produces a secondary receive signal, the primary and secondary receive signals representing ambient audio that potentially includes sound having a predominate direction of arrival; a speaker that converts an output signal into internal audio to at least partly cancel said sound, the output signal including a forward cancellation signal; a forward filter that operates solely on the primary receive signal to produce the forward cancellation signal; and a direction finder that operates on the primary and secondary receive signals to derive an estimate of said predominate direction of arrival, the direction finder adjusting the forward filter to implement a filter response corresponding to said estimate.
G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effects; Masking sound by electro-acoustically regenerating the original acoustic waves in anti-phase
H04R 1/40 - Arrangements for obtaining desired frequency or directional characteristics for obtaining desired directional characteristic only by combining a number of identical transducers
A light detection and ranging (LiDAR) system may include a laser and a array of single photon avalanche diodes (SPADs) that are triggered by laser light that reflects off a target scene. The LiDAR system may use the array of SPADs to assemble a raw histogram data. A histogram valid peak detector can be used to filter the raw histogram data to extract only valid histogram peak signals exceeding a threshold value. The histogram valid peak detector may include a raw histogram sum counter, a non-zero bins counter, a background noise floor generator, summing circuits, comparators, and a gating circuit, all controlled by a sequencing circuit. By filtering out noise signals in the raw histogram while only transferring the valid peak signals, data transfer rate requirements between different chips in the overall LiDAR system can be dramatically reduced.
G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
47.
SEMICONDUCTOR DEVICES WITH SINGLE-PHOTON AVALANCHE DIODES AND HYBRID ISOLATION STRUCTURES
An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. To mitigate crosstalk, an isolation structure may be formed in a ring around the SPAD. The isolation structure may be a hybrid isolation structure with both a metal filler that absorbs light and a low-index filler that reflects light. The isolation structure may be formed as a single trench or may include a backside deep trench isolation portion and a front side deep trench isolation portion. The isolation structure may also include a color filtering material.
In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.
A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
50.
SIC MOSFET SEMICONDUCTOR PACKAGES AND RELATED METHODS
A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/367 - Cooling facilitated by shape of device
An imaging device may include single-photon avalanche diodes (SPADs). Each SPAD may be overlapped by multiple microlenses. The microlenses over each SPAD may include first microlenses having a first size over a central portion of the SPAD and second microlenses having a second size that is greater than the first size over a peripheral area of the SPAD. The second microlenses may be spherical microlenses or cylindrical microlenses. The first microlenses may be aligned with underlying light scattering structures to improve the efficiency of the light scattering structures. The second microlenses may partially overlap isolation structures to direct light away from the isolation structures and towards the SPAD.
Multiphase trans-inductor voltage regulator fault diagnostic. One example is a method of detecting electrical faults in a multiphase power converter, the method comprising: driving, by a controller of the multiphase power converter, a first phase of the power converter, the first phase comprising a phase-one transformer module; driving, by the controller, a second phase of the power converter, the second phase comprising a phase-two transformer module distinct from the phase-one transformer module; testing, by the controller of the multiphase power converter, for a phase-one electrical fault associated with the phase-one transformer module; testing, by the controller, for a phase-two electrical fault associated with the phase-two transformer module; and driving, by the controller, a fault indicator in the presence of a phase-one or phase-two electrical fault.
H02M 7/217 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
53.
SEMICONDUCTOR DEVICE HAVING A SUPER JUNCTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
54.
Electronic Device Including a Transistor Structure
In an aspect, an electronic device can include a substrate, a semiconductor layer overlying the substrate and including a mesa adjacent to a trench, and a doped region within the semiconductor layer. The doped region extends across an entire width of the mesa and contacts the lowermost point of the trench. A charge pocket can be located between an elevation of the peak concentration of the doped region and an elevation of the upper surface of the substrate. In another aspect, a process includes patterning a semiconductor layer to define a trench, forming a sacrificial layer within the trench, removing the sacrificial layer from a bottom of the trench, doping a portion of the semiconductor layer that is along the bottom of the trench while a remaining portion of the sacrificial layer is along a sidewall of the trench.
A jet impingement cooling assembly for semiconductor devices includes a heat exchange base having an inlet chamber and an outlet chamber. An inlet connection may be in fluid connection with the inlet chamber, while an outlet connection may be in fluid connection with the outlet chamber. A jet plate may be coupled to the inlet chamber, and a jet pedestal may be formed on the jet plate and having a raised surface with a jet nozzle formed therein.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
56.
STACKED POWER TERMINALS IN A POWER ELECTRONICS MODULE
A module includes a power circuit enclosed in a casing. A first power terminal and a second power terminal of the power circuit each extend to an exterior of the casing. The first power terminal and the second power terminal separated by a gap are disposed in a stack on the exterior of the casing.
Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers using masks
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
58.
MICROLENS STRUCTURES FOR SEMICONDUCTOR DEVICE WITH SINGLE-PHOTON AVALANCHE DIODE PIXELS
An imaging device may include a plurality of single-photon avalanche diode (SPAD) pixels. The SPAD pixels may be overlapped by microlenses to direct light incident on the pixels onto photosensitive regions of the pixels and a containment grid with openings that surround each of the microlenses. During formation of the microlenses, the containment grid may prevent microlens material for adjacent SPAD pixels from merging. To ensure separation between the microlenses, the containment grid may be formed from material phobic to microlens material, or phobic material may be added over the containment grid material. Additionally, the containment grid may be formed from material that can absorb stray or off-angle light so that it does not reach the associated SPAD pixel, thereby reducing crosstalk during operation of the SPAD pixels.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
59.
METHODS AND STRUCTURES FOR CONTACTING SHIELD CONDUCTOR IN A SEMICONDUCTOR DEVICE
A semiconductor device includes a region of semiconductor material comprising a shielded-gate trench structure. The shielded-gate trench structure includes an active trench, an insulated shield electrode in the lower portion of the active trench, an insulated gate electrode adjacent to the gate dielectric in an upper portion of the active trench, and an inter-pad dielectric (IPD) interposed between the gate electrode and the shield electrode. A conductive region is within the active trench and extends through the gate electrode and the IPD and is electrically connected to the shield electrode. The conductive region is electrically isolated from the gate electrode. The gate electrode comprises a shape that is uninterrupted on at least one side the conductive region in a top view so that the gate electrode.
Capacitive coupling may enable more tightly synchronized operation of components in a multi-domain distributed driver that provides slope-controlled switching of differential signal lines. One illustrative distributed driver includes: a first set of transistors each coupled to drive a first bus line; a first set of delay elements configured to enable and disable the first set of transistors sequentially; a second set of transistors each coupled to drive a second bus line; a second set of delay elements configured to enable and disable the second set of transistors sequentially; and at least one capacitance coupling a first node in the first set of delay elements to a corresponding second node in the second set of delay elements to synchronize signal transitions at the first and second nodes.
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
B60R 16/02 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric
61.
METHODS AND APPARATUS FOR REPETITIVE HISTOGRAMMING
Various embodiments of the present technology may provide methods and apparatus for repetitive histogramming. The apparatus may provide a limited number of physical bins to perform multiple histograms on a total number of virtual bins. The apparatus may provide a single physical bin that is used to sweep over the total number of virtual bins.
Differential-signal receivers. One example is a method of operating a differential-signal receiver, the method comprising: receiving a first differential signal on a differential-signal pair, the first differential signal accompanying a common-mode voltage that is positive relative to a reference voltage of the differential-signal receiver; clamping, when the first differential signal is positive, an OUT+ node at a first voltage; and clamping, when the first differential signal is negative, the OUT- node at a second voltage.
Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.
A gate driver to control a high-power switching device is disclosed. The gate driver includes a multifunction pin that allows the gate driver to be controlled by a multifunction signal to perform a number of different functions. For example, a level of the multifunction signal at the multifunction pin can enable/disable the output of the gate driver. In another example, a level of the multifunction signal that is held for a period while the gate driver is in a fault state can reset the state of the gate driver. In another example, pulsing the multifunction signal a number of times can activate a test of the fault detection capabilities of the gate driver. Utilizing one pin for this control, simplifies circuit complexity for communication between a controller and the gate driver, thereby reducing cost and increasing reliability.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
H02H 3/06 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection - Details with automatic reconnection
66.
BREAKDOWN VOLTAGE IMPROVEMENT IN VERTICAL TRENCH-GATE DEVICES
In a general aspect, a vertical transistor can include a semiconductor region of a first conductivity type, and a plurality of perpendicularly intersecting trenches having a shielded gate structure of the vertical transistor disposed therein. A mesa of the semiconductor region can be defined by the plurality of perpendicularly intersecting trenches. The mesa can include a proximal end portion having a first doping concentration of the first conductivity type, a distal end portion having the first doping concentration of the first conductivity type, and a central portion disposed between the proximal end portion and the distal end portion. The central portion can have a second doping concentration of the first conductivity type that is less than the first doping concentration.
A method includes forming an ion-implanted capping layer in a first epitaxial layer disposed on a silicon substrate. The ion-implanted capping layer is doped with a second dopant of a same conductivity type as a first dopant in the silicon substrate. The second dopant has a lower diffusivity than the diffusivity of the first dopant. The ion-implanted capping layer has a thickness configured to contain up-diffusion of the first dopant from the silicon wafer in the first epitaxial layer in thermal processes for fabricating a vertical MOSFET device in the substrate. The ion-implanted capping layer is configured to limit up-diffusion of the first dopant from the silicon wafer through the ion-implanted capping layer into a second epitaxial layer such that a concentration of the first dopant in the second epitaxial layer is lower than a concentration of the first dopant in the first epitaxial layer.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
A multifaceted capillary that can be used in a wire-bonding machine to create a multi-segment wire-bond is disclosed. The multifaceted capillary is shaped to apply added pressure and thickness to an outer segment of the multi-segment wire-bond that is closest to the wire loop. The added pressure eliminates a gap under a heel portion of the multi-segment wire-bond and the added thickness increases a mechanical strength of the heel portion. As a result, a pull test of the multi-segment wire-bond may be higher than a single-segment wire-bond and the multi-segment wire-bond may resist cracking, lifting, or breaking.
A semiconductor device includes a work piece comprising a first material, a first side, a second side opposite to the first side, and a first coefficient of thermal expansion (first CTE). Recesses extend into the work piece from the first side and includes a pattern. A second material having a second CTE is within the recesses and is over the first material between the recesses; and A third material having a third CTE is over one of the second side or the second material. The third CTE and the second CTE are different than the first CTE.
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
A MOSFET device die includes an active area formed on a semiconductor substrate. The active area includes a first active area portion and a second active area portion. At least one mesa is formed in the semiconductor substrate extending in a longitudinal direction through the active area. The at least one mesa includes a channel region extending in a longitudinal direction. The channel region includes low threshold voltage channel portions and high threshold voltage channel portions. The first active area portion includes the channel portions in a first ratio of low threshold voltage channel portions to high threshold voltage channel portions, and the second active area portion includes channel portions in a second ratio of low threshold voltage channel portions to high threshold voltage channel portions. The first ratio is larger than the second ratio.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A package includes an interposer substrate having at least one through-substrate via (TSV) electrically connecting a top surface of the interposer substrate to a bottom surface of the interposer substrate. The package further includes at least one semiconductor die having a top side, a bottom side, and a sidewall. The at least one semiconductor die is disposed on the interposer substrate with the bottom side electrically coupled to the top surface of the interposer substrate. A molding material is disposed on at least on a portion of the at least one semiconductor die, and an array of conductive material is disposed on the bottom surface of the interposer substrate. The array of conductive material forms the external contacts of the package.
Quasi-Constant On-Time Controller. At least one example embodiment is a method of operating a power converter, comprising: charging an inductor of a switching power converter, each charging has an on-time; and then discharging the inductor while providing current to the load; and repeating the charging and the discharging at a switching frequency. During the repeating, the example method may comprise: adjusting the switching frequency proportional to a voltage difference between an output voltage and a setpoint voltage; generating an on-time reference proportional to a frequency difference between the switching frequency and a setpoint frequency, the on-time of each charging of the inductor is based on the on-time reference; and modifying the on-time proportional to the voltage difference.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
76.
IMAGE SENSOR WITH ACTIVE CAPACITANCE CANCELLATION CIRCUITRY TO REDUCE PIXEL OUTPUT SETTLING TIME
An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.
H04N 5/365 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
A method includes disposing a sheet of glass on a front side of a semiconductor substrate that includes at least one image sensor die, attaching the sheet of glass to the at least one image sensor die by a bead of adhesive material disposed on an edge of the at least one image sensor die, and sawing the semiconductor substrate from a back side to form a trench along a side of the at least one image sensor die. The trench extends through a thickness of the semiconductor substrate and through a part of a thickness of the sheet of glass. The method further includes filling the trench with a molding material to form a layer of molding material on a sidewall of the at least one image sensor die, and singulating the semiconductor substrate to isolate an individual image sensor package enclosing the at least one image sensor die.
A low noise amplifier includes a plurality of serially-coupled amplifier stages. Each serially-coupled amplifier stage provides a respective amplified signal, wherein a first amplifier stage receives an input signal, and a last amplifier stage provides an amplified output signal. Each serially-coupled amplifier stage includes a single-ended amplifier having an input, and an output providing the respective amplified signal, a first passive network, and a second passive network. The first passive network has a first terminal forming an input of a respective one of said plurality of serially-coupled amplifier stages, and a second terminal coupled to said input of said single-ended amplifier, the first passive network including a first capacitor coupled in series between the first and said second terminals of the first passive network. The second passive network is coupled in parallel to the single-ended amplifier and between the input and the output of the single-ended amplifier.
A receive signal strength indicator circuit includes a low-noise amplifier, an envelope detector, and a selection circuit. The low-noise amplifier has a plurality of serially-coupled amplifier stages each providing an amplified signal, wherein a first amplifier stage receives an input signal whose signal strength is to be measured, and a last amplifier stage provides an amplified output signal. The envelope detector stage includes a plurality of envelope detector circuits, each having an input receiving the amplified signal of a corresponding one of the plurality of serially-coupled amplifier stages, and an output for providing a receive signal strength indicator component. The selection circuit is coupled to the outputs of the plurality of envelope detector circuits, and provides the receive signal strength indicator component of one of the plurality of envelope detector circuits having a desired linear range as a detected RSSI signal.
A low-noise amplifier includes a low-noise amplifier stage and a filtering and biasing stage. The low-noise amplifier stage receives an input signal and provides a first output signal in response thereto. The low-noise amplifier stage includes a gain element for proving the first output signal, and at least one lowpass filter circuit in series between a first power supply voltage terminal and the gain element having a conductivity determined by lowpass filtering a signal at a bias terminal, and a filtering and biasing stage having an input for receiving the first output signal, and an output for providing a second output signal, and at least one cascode element having a first current conduction path coupled in series between the bias terminal and the output, and having a predetermined filter characteristic.
Audio communication methods, devices, and systems, are provided with error correction overwrite for audio artifact reduction. One illustrative low-latency audio streaming method includes: receiving packets of digital audio data; applying an error correction code decoder to obtain a data stream that includes error-corrected data samples; providing a correction-limited data stream by replacing any of the error-corrected data samples that are outliers; and converting the correction-limited data stream into an audio signal.
Audio streaming devices, systems, and methods may employ adaptive differential pulse code modulation (ADPCM) techniques providing for optimum performance even while ensuring robustness against transmission errors. One illustrative device includes: a difference element that produces a sequence of prediction error values by subtracting predicted values from audio samples; a scaling element that produces scaled error values by dividing each prediction error by a corresponding envelope estimate; a quantizer that operates on the scaled error values to produce quantized error values; a multiplier that uses the corresponding envelope estimates to produce reconstructed error values; a predictor that produces the next audio sample values based on the reconstructed error values; and an envelope estimator. The envelope estimator includes: an updater that applies a dynamic gain to the reconstructed error values to produce update values; and an integrator that combines each of the update values with the corresponding envelope estimate to produce a subsequent envelope estimate.
A driver circuit drives an output terminal with an input/output voltage using an NMOS transistor and a PMOS transistor. A pre-driver for the NMOS transistor supplied with a drive voltage and receives a data signal referenced to the drive voltage. A pre-driver for the PMOS transistor has a positive supply input connected to the positive supply rail, a negative supply input receiving a second drive voltage equal to the supply voltage minus the drive voltage. A level shifter circuit, shifts the data signal to be referenced between the supply voltage and the second drive voltage. A charge pump circuit for providing second drive voltage, the charge pump circuit driven with a variable switching frequency proportional to a current of the PMOS transistor.
A high voltage is generated from a low supply voltage by a charge pump driven with a pulse generator. A comparator compares the low supply voltage to a predetermined proportion of the high voltage. A low power voltage divider creates the predetermined portion of the high voltage. The comparator output drives the pulse generator, and the pulse generator output resets the comparator. A high voltage to low voltage mode may also be employed using the same arrangement.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
85.
APPARATUS AND METHODS FOR PRODUCING STABLE CLOCK SIGNALS BASED ON A VARYING FREQUENCY SOURCE CLOCK
In some aspects, the techniques described herein relate to a system on a chip (SoC) including a first clock divider configured to: receive an oscillator signal at a first frequency; produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency, the second frequency being a division of the first frequency. The first clock divider can selectively provide the first clock signal or the second clock signal as a first output clock signal based on a scaling configuration signal. The first clock divider can produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal. The SoC can include a second clock divider configured to provide a second clock output signal based on the first output clock signal and the frequency indication signal.
An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
A low-dropout linear regulator regulates a supply voltage and includes a voltage-to-frequency circuit producing a pulse chain with a frequency based on an error voltage. A charge pump circuit receives the pulse chain and switching one or more charge pumps based on the pulse chain. A current mirror circuit is connected to the charge pump circuit and includes a first diode-connected metal-oxide semiconductor (MOS) transistor, and a second MOS transistor having a first terminal connected to the supply voltage, a second terminal providing an output, and a gate connected to the gate of the first MOS transistor. The output is fed back to the voltage-to-frequency circuit.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A near-field transmitter includes a power amplifier, a resonant network, an envelope detector, and an antenna tuning circuit. The power amplifier has an input for receiving a communication signal, and an output for providing a differential output signal. The resonant network is coupled to the output of the power amplifier and has a tunable reactive element tuned by a tuning signal. The envelope detector is coupled to the output of the power amplifier for providing an envelope signal in response to the differential output signal. The antenna tuning circuit is for adjusting the tuning signal in response to the envelope signal.
A power SiC MOSFET with a built-in Schottky rectifier provides advantages of including a Schottky rectifier, such as avoiding bipolar degradation, while reducing a parasitic capacitive charge and related power losses, as well as system cost. A lateral built-in channel layer may enable lateral spacing of the MOSFET gate oxide from a high electric field at the Schottky contact, while also providing current limiting during short-circuit events.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/80 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
91.
EPITAXIAL FIELD STOP REGION FOR SEMICONDUCTOR DEVICES
A semiconductor device includes a backside contact and a substrate. An epitaxial field stop region may be formed on the substrate with a graded doping profile that decreases with distance away from the substrate, and an epitaxial drift region may be formed adjacent to the epitaxial field stop region. A frontside device may be formed on the epitaxial drift region.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/223 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a gaseous phase
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
A circuit module includes a substrate with a patterned metal surface. The patterned metal surface includes a conductive terminal pad, a first conductive pad, and a second conductive pad that is non-adjacent to the conductive terminal pad. A first circuit portion is assembled on the first conductive pad and a second circuit portion is assembled on the second conductive pad. A conductive bridge electrically couples the conductive terminal pad and the second conductive pad. The conductive bridge includes an elevated span extending above and across the first conductive pad.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
93.
IMAGE SENSOR PACKAGE HAVING A LIGHT BLOCKING MEMBER
According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.
Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 21/786 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
A method includes attaching a power electronic substrate to a bottom of a frame. The frame has a box-like rectangular shape with an open top and an open bottom. The method further includes disposing an external conductive terminal on the frame. The external conductive terminal has at least one terminal stub that extends on to the front surface of the power electronic substrate. The method further includes welding the at least one terminal stub to at least one circuit trace disposed on the front surface of the power electronic substrate.
Implementations of a semiconductor package may include one or more power semiconductor die included in a die module; a first heat sink directly coupled to one or more source pads of the die module; a second heat sink directly coupled to one or more drain pads of the die module; a gate contact coupled with one or more gate pads of the die module; and a coating coupled directly to the die module. The gate contact may be configured to extend through an immersion cooling enclosure.
H01L 23/44 - Arrangements for cooling, heating, ventilating or temperature compensation the complete device being wholly immersed in a fluid other than air
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a photodiode and a floating diffusion region. The floating diffusion region may be coupled to a charge storage structure for a low conversion gain configuration and can be coupled to a charge storage structure for a medium conversion gain configuration. The medium conversion gain charge storage structure may be activated when transferring photodiode charge to the floating diffusion region for a high conversion gain configuration. The control circuitry may control each pixel to perform a high conversion gain readout operation, a medium conversion gain readout operation, and a low conversion gain readout operation. If desired, the medium conversion gain readout operation may be omitted.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/585 - Control of the dynamic range involving two or more exposures acquired simultaneously with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
A system may include multiple electrical components. One electrical component such as an imaging sub-system may be communicatively coupled to another electrical component such as control circuitry for the system. The imaging-subsystem may include transmitter circuitry. The transmitter circuitry can include driver circuitry configured to provide the transmitter circuitry output using a multi-level signaling scheme. To generate the control signals for the driver circuitry, pre-driver combinational logic may precede the serializer circuitry and be coupled to the word data latch circuitry. In such a manner, the generated control signals for different portions of the driver circuitry can be better synchronized with one another, thereby helping improve data EYE margin in the multi-level signal scheme.
A galvanically isolated gate driver for a power transistor is disclosed. The gate driver provides various temperature protection features that are enabled by (i) diagnostic circuitry to generate fault signals and monitoring signals, (ii) signal processing to enable communication over a shared communication channel across an isolation barrier, (iii) signal processing to reduce operating current needed for real-time thermal monitoring, and (iv) a disable circuit for unused temperature sensing pins.
