Semiconductor Components Industries, L.L.C.

United States of America

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2024 June (MTD) 7
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IPC Class
H01L 29/66 - Types of semiconductor device 459
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only 386
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices 367
H01L 27/146 - Imager structures 362
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate 299
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09 - Scientific and electric apparatus and instruments 43
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40 - Treatment of materials; recycling, air and water treatment, 20
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39 - Transport, packaging, storage and travel services 3
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1.

MICROLENSES FOR SEMICONDUCTOR DEVICE WITH SINGLE-PHOTON AVALANCHE DIODE PIXELS

      
Application Number 18441588
Status Pending
Filing Date 2024-02-14
First Publication Date 2024-06-06
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Sulfridge, Marc Allen
  • Lee, Byounghee
  • Boettiger, Ulrich

Abstract

An imaging device may include a plurality of single-photon avalanche diode (SPAD) pixels. The SPAD pixels may be overlapped by square toroidal microlenses to direct light incident on the pixels onto photosensitive regions of the pixels. The square toroidal microlenses may be formed as first and second sets of microlenses aligned with every other SPAD pixel and may allow the square toroidal microlenses to be formed without gaps between adjacent lenses. Additionally or alternatively, a central portion of each square toroidal microlenses may be filled by a fill-in microlens. Together, the square toroidal microlenses and the fill-in microlenses may form convex microlenses over each SPAD pixel. The fill-in microlenses may be formed from material having a higher index of refraction than material that forms the square toroidal microlenses.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
  • H04N 25/50 - Control of the SSIS exposure
  • H04N 25/702 - SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout
  • H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array

2.

BACKSIDE METAL PATTERNING DIE SINGULATION SYSTEM AND RELATED METHODS

      
Application Number 18443562
Status Pending
Filing Date 2024-02-16
First Publication Date 2024-06-06
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Seddon, Michael J.

Abstract

Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers using masks
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

3.

IMAGE SENSORS WITH MULTIPLE COLUMN OUTPUT LINES PER COLUMN

      
Application Number 18062130
Status Pending
Filing Date 2022-12-06
First Publication Date 2024-06-06
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Talbot, Andrew David
  • Spinks, Stephen James
  • Cowley, Nicholas Paul

Abstract

An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may include a respective plurality of column output lines. Each column output line may be coupled to a respective subset of the imaging pixels in that column of imaging pixels. Each plurality of column output lines for a given column may be coupled to readout circuitry. Each group of column output lines may share a single respective sample and hold circuit and a single respective analog-to-digital converter. Alternatively, each group of column output lines may have one sample and hold circuit per column output line and each group of column output lines may share a single respective analog-to-digital converter. Alternatively, each group of column output lines may have one sample and hold circuit per column output line and may have one analog-to-digital converter per column output line.

IPC Classes  ?

  • H04N 25/767 - Horizontal readout lines, multiplexers or registers
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

4.

DIRECT-COOLING FOR SEMICONDUCTOR DEVICE MODULES

      
Application Number 18441484
Status Pending
Filing Date 2024-02-14
First Publication Date 2024-06-06
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Eom, Jooyang
  • Yoo, Inpil
  • Im, Seungwon
  • Lee, Byoungok

Abstract

In a general aspect, an apparatus includes a substrate and a metal layer disposed on a surface of the substrate. The apparatus also includes a first recess and a second recess formed in the metal layer, and a folded cooling fin. A first portion of the folded cooling fin is disposed within the first recess and coupled with the metal layer, and a second portion of the folded cooling fin is disposed in the second recess and coupled with the metal layer.

IPC Classes  ?

  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

5.

MOLDED POWER MODULES WITH FLUIDIC-CHANNEL COOLED SUBSTRATES

      
Application Number 18491369
Status Pending
Filing Date 2023-10-20
First Publication Date 2024-06-06
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Jeon, Oseob
  • Im, Seungwon
  • Kim, Jihwan
  • Kang, Dongwook

Abstract

In a general aspect, a semiconductor device module includes a ceramic substrate having a first surface and a second surface opposite the first surface. A patterned metal layer is disposed on the first surface of the ceramic substrate, and a semiconductor die is disposed on the patterned metal layer. A cooling structure is disposed on the second surface of the ceramic substrate, where the cooling structure includes a plurality of fluidic-cooling channels. The module also includes a molding compound that encapsulates the ceramic substrate, the patterned metal layer and the semiconductor die, and partially encapsulates the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound.

IPC Classes  ?

  • H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/498 - Leads on insulating substrates
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

6.

PRE-STACKING MECHANICAL STRENGTH ENHANCEMENT OF POWER DEVICE STRUCTURES

      
Application Number 18444221
Status Pending
Filing Date 2024-02-16
First Publication Date 2024-06-06
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Lin, Yusheng
  • Carney, Francis J.
  • Chew, Chee Hiong
  • Yasuda, Shunsuke

Abstract

A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

7.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

      
Application Number US2023073298
Publication Number 2024/118238
Status In Force
Filing Date 2023-09-01
Publication Date 2024-06-06
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Franchi, Jimmy Robert Hannes
  • Domeij, Martin

Abstract

A method of making a semiconductor device (10) includes providing semiconductor region (14) of a first conductivity type. A first region (141) comprising the first conductivity type within the semiconductor region. The first region provides a JFET channel region (141A) for a JFET device (110). A second region (31) comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion (31A) and a second portion (31B) below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region (37) comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/336 - Field-effect transistors with an insulated gate
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

8.

BACKSIDE METAL PATTERNING DIE SINGULATION SYSTEMS AND RELATED METHODS

      
Application Number 18433554
Status Pending
Filing Date 2024-02-06
First Publication Date 2024-05-30
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Seddon, Michael J.

Abstract

Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

9.

PROPAGATION DELAY COMPENSATION AND INTERPOLATION FILTER

      
Application Number 18433108
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-05-30
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Bertin, Jacques Jean

Abstract

Various embodiments provide a filter for propagation delay compensation and interpolation in encoder digital signal processing. The filter can include a first low pass filter configured to reduce noise of a digital input comprising a measured angular position; a first differentiator configured to receive a filtered digital input and to calculate a speed from a difference in time of the measured angular position and a previous angular position; a second low pass filter configured to reduce noise from the speed; a second differentiator configured to receive a filtered speed and to calculate acceleration using a difference in time of the filtered speed and a previous speed; a third low pass filter configured to reduce noise of the acceleration; and a delay compensator configured to receive the filtered digit input, the filtered speed, and a filtered acceleration, and to calculate a propagation delay compensated digital output.

IPC Classes  ?

  • H03M 1/12 - Analogue/digital converters
  • G01B 7/00 - Measuring arrangements characterised by the use of electric or magnetic techniques
  • G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
  • G01D 5/14 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
  • G01D 11/24 - Housings
  • H03M 1/48 - Servo-type converters

10.

Self-Aligned Trench MOSFET Contacts Having Widths Less Than Minimum Lithography Limits

      
Application Number 18525212
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-05-30
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Soma, Mitsuru
  • Shimbo, Masahiro
  • Kuramae, Masaki
  • Uchida, Kouhei

Abstract

Semiconductor devices made by forming hard mask pillars on a surface of a substrate, forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar. The open gaps may be formed between adjacent sacrificial spacers. The semiconductor devices may also be formed by etching the hard mask pillars to form pillar gaps, etching gate trenches into the substrate through the open gaps and the pillar gaps, forming a gate electrode within the gate trenches, implanting channels and sources in the substrate below the sacrificial spacers, forming an insulator layer around the sacrificial spacers, etching the sacrificial spacers to form contact trenches within the substrate, and filling the contact trenches with a conductive material to form contacts.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 29/40 - Electrodes
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

11.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

      
Application Number 18058915
Status Pending
Filing Date 2022-11-28
First Publication Date 2024-05-30
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Franchi, Jimmy Robert Hannes
  • Domeij, Martin

Abstract

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

12.

CIRCUITRY AND METHODS FOR MITIGATING GRADIENT EFFECTS IN IMAGE SENSORS

      
Application Number 18058926
Status Pending
Filing Date 2022-11-28
First Publication Date 2024-05-30
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Engla Syam, Mukesh Rao
  • Cowley, Nicholas Paul

Abstract

An image sensor may include an array of pixels and associated delay calibration circuitry for determining an amount of delay for row control signals. The delay calibration circuitry can include circuitry for generating a calibration row control signal, circuitry for propagating the calibration row control signal down a row of dummy pixels, and one or more sampling circuits coupled to one or more tap points in the row of dummy pixels for monitoring when the calibration row control signal arrives at the one or more tap points. The array of pixels can output signals during normal operation. The image sensor may include column readout circuitry for reading out the signals from the array of pixels. The column readout circuitry can be controlled using sampling signals that are progressively delayed based on count values output from the one or more sampling circuits.

IPC Classes  ?

  • H04N 25/673 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction by using reference sources
  • H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
  • H04N 25/702 - SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

13.

AUTOMATED POWER DISCRETE AND MODULE MODEL GENERATION FOR SYSTEM LEVEL SIMULATORS

      
Application Number US2023073290
Publication Number 2024/112447
Status In Force
Filing Date 2023-09-01
Publication Date 2024-05-30
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Xiao, Yun Peng
  • Victory, James Joseph
  • Pushpakaran, Bejoy N.
  • Picha, Ondrej
  • Chu, Wai Lun
  • Vanaparthy, Sravan

Abstract

Implementations of a method of generating a product system model may include, using a first interface (120), receiving from a user a selection of a product type; selecting a product SPICE model associated with the product type from a database of product SPICE models; and using a second interface (130), receiving from the user a selection of a process condition. The method may include, using a third interface (134), receiving from the user one or more system characteristics and one or more operating characteristics; using a fourth interface (140), receiving from the user one or more circuit characteristics; using a SPICE model simulation module (110), generating a SPICE model output with the product SPICE model, and, using a formatting module (112), formatting the SPICE model output into a product system model file.

IPC Classes  ?

  • G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
  • G06F 111/10 - Numerical modelling
  • G06F 113/18 - Chip packaging
  • G06F 119/08 - Thermal analysis or thermal optimisation

14.

POWER MODULE PACKAGE WITH MOLDED VIA AND DUAL SIDE PRESS-FIT PIN

      
Application Number 18056442
Status Pending
Filing Date 2022-11-17
First Publication Date 2024-05-23
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Chi, Heejo
  • Im, Seungwon
  • Jeon, Oseob

Abstract

A module includes an assembly of a semiconductor device die, a lead frame connected to the semiconductor device die, and a substrate connected to the lead frame. The substrate includes at least one plated-through hole (PTH). A mold body encapsulates the assembly. The mold body includes a through-mold via (TMV) aligned with a portion of the substrate including the at least one PTH. The PTH is exposed in the TMV to an environment outside the mold body and is physically accessible from outside the mold body through the TMV.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

15.

CIRCUITRY AND METHODS FOR MITIGATING IMBALANCE IN IMAGE SENSORS WITH MULTIPLE READOUT PATHS

      
Application Number 18057408
Status Pending
Filing Date 2022-11-21
First Publication Date 2024-05-23
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Cowley, Nicholas Paul
  • Engla Syam, Mukesh Rao

Abstract

An image sensor may include a pixel array and associated readout paths calibration circuitry. The image sensor may include first column readout circuits formed along a first edge of the pixel array and second column readout circuits formed along a second opposing edge of the pixel array. The readout paths calibration circuitry may include one or more first calibration readout circuits located by the first edge of the array, one or more second calibration readout circuits located by the second edge of the array, and an error detection circuit configured to output an error signal based on signals output from the one or more first calibration readout circuits and the one or more second calibration readout circuits. The one or more second calibration readout circuits and the second column readout circuits can receive a reference voltage that is dynamically adjusted based on the error signal.

IPC Classes  ?

  • G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration

16.

AUTOMATED POWER DISCRETE AND MODULE MODEL GENERATION FOR SYSTEM LEVEL SIMULATORS

      
Application Number 18058382
Status Pending
Filing Date 2022-11-23
First Publication Date 2024-05-23
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Xiao, Yun Peng
  • Victory, James Joseph
  • Pushpakaran, Bejoy N.
  • Picha, Ondrej
  • Chu, Wai Lun
  • Vanaparthy, Sravan

Abstract

Implementations of a method of generating a product system model may include, using a first interface, receiving from a user a selection of a product type; selecting a product SPICE model associated with the product type from a database of product SPICE models; and using a second interface, receiving from the user a selection of a process condition. The method may include, using a third interface, receiving from the user one or more system characteristics and one or more operating characteristics; using a fourth interface, receiving from the user one or more circuit characteristics; using a SPICE model simulation module, generating a SPICE model output with the product SPICE model, and, using a formatting module, formatting the SPICE model output into a product system model file, the product system model file including one of a structured text file, a plain text file, or a delimited text file.

IPC Classes  ?

  • G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

17.

POWER ELECTRONICS PACKAGE WITH DUAL-SINGLE SIDE COOLING WATER JACKET

      
Application Number US2023076958
Publication Number 2024/107513
Status In Force
Filing Date 2023-10-16
Publication Date 2024-05-23
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Lee, Yoonsoo
  • Im, Seungwon
  • Jeon, Oseob

Abstract

A package (100) includes a frame (140) having a cooling fluid channel (155) therethrough. The frame has at least one opening (147) in a first sidewall alongside the cooling fluid channel and at least one opening (149) in a second sidewall alongside the cooling fluid channel. A first power electronics module (200A) covers the at least one opening in the first sidewall with a surface of a substrate in the first power electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the first sidewall, and a second power electronics module (200A) covers the at least one opening in the second sidewall with a surface of a substrate in the second electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the second sidewall.

IPC Classes  ?

  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids

18.

OPTICAL SENSOR TRANSPARENT COVER WITH ARRAY CONTACT GRID

      
Application Number 18056524
Status Pending
Filing Date 2022-11-17
First Publication Date 2024-05-23
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Vaartstra, Brian Anthony
  • Kinsman, Larry Duane

Abstract

A package includes an optical sensor die, a support grid structure disposed on the optical sensor die, and an optically transparent cover attached to the support grid structure. A surface of the optical sensor die includes an optically active surface area (OASA) and an edge surface portion lying outside a perimeter of the OASA. The support grid structure disposed on the surface of the optical sensor die includes at least one pillar disposed within the OASA and an edge block disposed on the edge surface portion lying outside the perimeter of the OASA. The optically transparent cover is supported by the support grid structure at a height above the optical sensor die while maintaining an air gap between the optically transparent cover and the OASA.

IPC Classes  ?

  • G01J 3/28 - Investigating the spectrum
  • G01D 5/24 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance

19.

IMAGE SENSORS HAVING DATA CONVERTERS WITH LOW NOISE COMPARATORS

      
Application Number 18056755
Status Pending
Filing Date 2022-11-18
First Publication Date 2024-05-23
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Ramakrishnan, Shankar

Abstract

An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.

IPC Classes  ?

  • H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters
  • H04N 5/369 - SSIS architecture; Circuitry associated therewith

20.

POWER MODULE PACKAGE WITH MOLDED VIA AND DUAL SIDE PRESS-FIT PIN

      
Application Number US2023076968
Publication Number 2024/107514
Status In Force
Filing Date 2023-10-16
Publication Date 2024-05-23
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Chi, Heejo
  • Im, Seungwon
  • Jeon, Oseob

Abstract

A module includes an assembly of a semiconductor device die (110), a lead frame (120, 130) connected to the semiconductor device die, and a substrate (112) connected to the lead frame. The substrate includes at least one plated-through hole (PTH) (162). A mold body (150) encapsulates the assembly. The mold body includes a through-mold via (TMV) (160) aligned with a portion of the substrate including the at least one PTH. The PTH is exposed in the TMV to an environment outside the mold body and is physically accessible from outside the mold body through the TMV.

IPC Classes  ?

  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/498 - Leads on insulating substrates

21.

SEMICONDUCTOR POWER MODULE

      
Application Number US2023079735
Publication Number 2024/107791
Status In Force
Filing Date 2023-11-15
Publication Date 2024-05-23
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Prajuckamol, Atapol
  • Chew, Chee Hiong

Abstract

In a general aspect, a power module package (400) includes a substrate (105) that has a ceramic layer (105a) with a first primary surface and a second primary surface opposite the first primary surface. The substrate also includes a patterned metal layer (110) disposed on the first primary surface. The package also includes a first plurality of semiconductor die (120) disposed on a first portion of the patterned metal layer (110a). The first plurality of semiconductor die are linearly arranged along a first axis (120a). The package further includes a second plurality of semiconductor die (125) disposed on a second portion of the patterned metal layer (110b). The second plurality of semiconductor die are linearly arranged along a second axis (125a) parallel to the first axis.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/495 - Lead-frames

22.

SEMICONDUCTOR DEVICE PACKAGE ASSEMBLIES AND METHODS OF MANUFACTURE

      
Application Number 18054229
Status Pending
Filing Date 2022-11-10
First Publication Date 2024-05-16
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Im, Seungwon
  • Kim, Jeungdae
  • Jeon, Oseob
  • Lee, Byoungok

Abstract

In a general aspect, a semiconductor device package can include a die attach paddle having a first surface and a second surface that is opposite the first surface; a semiconductor die coupled with the first surface of the die attach paddle, and a direct-bonded-metal (DBM) substrate The DBM substrate can include a ceramic layer having a first surface and a second surface that is opposite the first surface, a first metal layer disposed on the first surface of the ceramic layer and coupled with the second surface of the die attach paddle, a second metal layer disposed on the second surface of the ceramic layer, and a thermally conductive adhesive disposed on the second metal layer, At least a surface of the thermally conductive adhesive can be exposed external to the device package. The thermally conductive adhesive can be configured for coupling the device package with a thermal dissipation appliance.

IPC Classes  ?

  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
  • H01L 23/495 - Lead-frames

23.

POWER ELECTRONICS PACKAGE WITH DUAL-SINGLE SIDE COOLING WATER JACKET

      
Application Number 18055123
Status Pending
Filing Date 2022-11-14
First Publication Date 2024-05-16
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Lee, Yoonsoo
  • Im, Seungwon
  • Jeon, Oseob

Abstract

A package includes a frame having a cooling fluid channel therethrough. The frame has at least one opening in a first sidewall alongside the cooling fluid channel and at least one opening in a second sidewall alongside the cooling fluid channel. A first power electronics module covers the at least one opening in the first sidewall with a surface of a substrate in the first power electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the first sidewall, and a second power electronics module covers the at least one opening in the second sidewall with a surface of a substrate in the second electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the second sidewall.

IPC Classes  ?

  • H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

24.

SCALABLE POWER SEMICONDUCTOR DEVICE PACKAGE WITH LOW INDUCTANCE

      
Application Number 18508551
Status Pending
Filing Date 2023-11-14
First Publication Date 2024-05-16
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Prajuckamol, Atapol
  • Chew, Chee Hiong

Abstract

In a general aspect, a power module package includes a substrate that has a ceramic layer with a first primary surface and a second primary surface opposite the first primary surface. The substrate also includes a patterned metal layer disposed on the first primary surface. The package also includes a first plurality of semiconductor die disposed on a first portion of the patterned metal layer. The first plurality of semiconductor die are linearly arranged along a first axis. The package further includes a second plurality of semiconductor die disposed on a second portion of the patterned metal layer. The second plurality of semiconductor die are linearly arranged along a second axis parallel to the first axis.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/498 - Leads on insulating substrates

25.

TRANSISTORS WITH SELECTIVELY LANDED GATE ARRAY

      
Application Number US2023077770
Publication Number 2024/102579
Status In Force
Filing Date 2023-10-25
Publication Date 2024-05-16
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Franchi, Jimmy Robert Hannes
  • Gumaelius, Krister
  • An, Jaein

Abstract

A semiconductor device may include a plurality of transistors (110), with a first array (204, 206) of low-resistance material formed in a first dielectric layer (216), with a gate subset (204) of the first array formed on a plurality of gate electrodes (202) of the transistors, and a source subset (206) of the first array formed on a plurality of source regions (212) of the transistors. A second array (205, 207) of low-resistance material may be formed in a second dielectric layer (220), with a gate subset (205) of the second array formed on the gate subset (204) of the first array and thereby electrically connected to the plurality of gate electrodes (202), and a source subset (207) of the second array formed on the source subset (206) of the first array and thereby electrically connected to the plurality of source regions (212).

IPC Classes  ?

  • H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

26.

TRANSISTORS WITH SELECTIVELY LANDED GATE ARRAY

      
Application Number 18053177
Status Pending
Filing Date 2022-11-07
First Publication Date 2024-05-09
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Franchi, Jimmy Robert Hannes
  • Gumaelius, Krister
  • An, Jaein

Abstract

A semiconductor device may include a plurality of transistors, with a first array of low-resistance material formed in a first dielectric layer, with a gate subset of the first array formed on a plurality of gate electrodes of the transistors, and a source subset of the first array formed on a plurality of source regions of the transistors. A second array of low-resistance material may be formed in a second dielectric layer, with a gate subset of the second array formed on the gate subset of the first array and thereby electrically connected to the plurality of gate electrodes, and a source subset of the second array formed on the source subset of the first array and thereby electrically connected to the plurality of source regions.

IPC Classes  ?

  • H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 27/082 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form

27.

SEMICONDUCTOR CRYSTAL GROWTH USING SOURCE POWDER FROM CRUCIBLE WALL

      
Application Number 18053796
Status Pending
Filing Date 2022-11-09
First Publication Date 2024-05-09
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Jesko, Radek
  • Valek, Lukas
  • Tesik, Jan

Abstract

A crucible for manufacturing semiconductor crystals may be disposed adjacent to a heating element. The crucible may include a first seed crystal site and a second seed crystal site at opposed ends of the crucible. A compartment may be defined between an outer wall and an inner wall of the crucible, where the inner wall is formed with a porous graphite membrane. Source powder loaded into the compartment may then be heated by the heating element to sublimate and diffuse from the compartment and through the inner wall to provide crystal growth of a first seed crystal at the first seed crystal site and of a second seed crystal at the second seed crystal site.

IPC Classes  ?

  • C30B 11/00 - Single-crystal-growth by normal freezing or freezing under temperature gradient, e.g. Bridgman- Stockbarger method

28.

IMPROVED SEALS FOR SEMICONDUCTOR DEVICES WITH SINGLE-PHOTON AVALANCHE DIODE PIXELS

      
Application Number 18051600
Status Pending
Filing Date 2022-11-01
First Publication Date 2024-05-02
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Gambino, Jeffrey Peter
  • Jerome, Rick Carlton
  • Price, David T.
  • Keyes, Michael Gerard
  • Deignan, Anne

Abstract

A semiconductor device may include a plurality of single-photon avalanche diode (SPAD) pixels. The semiconductor device may be a backside device having a substrate at the backside, dielectric layers on the substrate, metal layers interleaved with the dielectric layers, and a through silicon via (TSV) formed in the backside through the substrate and the dielectric layers. TSV seal rings may be formed around the TSV to protect the semiconductor device from moisture and/or water ingress. The TSV seal rings may be coupled to a high-voltage cathode bond pad and be coupled to offset portions of one of the metal layers to reduce leakage and/or parasitic effects due to the voltage difference between the cathode and the substrate. The TSV seal rings may also be merged with die seal rings at the edge of the substrate.

IPC Classes  ?

29.

NON-PLANAR SEMICONDUCTOR PACKAGING SYSTEMS AND RELATED METHODS

      
Application Number 18398414
Status Pending
Filing Date 2023-12-28
First Publication Date 2024-05-02
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Seddon, Michael J.
  • Carney, Francis J.

Abstract

Implementations of a packaging system may include a wafer; and a curvature adjustment structure coupled thereto where the curvature adjustment structure may be configured to alter a curvature of a largest planar surface of the wafer.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • B21D 11/10 - Bending specially adapted to produce specific articles, e.g. leaf springs
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

30.

STACKED INTEGRATED CIRCUIT DIES AND INTERCONNECT STRUCTURES

      
Application Number 18558593
Status Pending
Filing Date 2022-04-27
First Publication Date 2024-05-02
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Borthakur, Swarnal
  • Pelella, Mario M.
  • Kothandaraman, Chandrasekharan
  • Sulfridge, Marc Allen
  • Lin, Yusheng
  • Kinsman, Larry Duane

Abstract

An integrated circuit package (34, 34′, 34″) may be implemented by stacked first, second, and third integrated circuit dies (40, 50, 60). The first and second dies (40, 50) may be bonded to each other using corresponding inter-die connection structures (74-1, 84-1) at respective interfacial surfaces facing the other die. The second die (50) may also include a metal layer (84-2) for connecting to the third die (60) at its interfacial surface with the first die (40). The metal layer (84-2) may be connected to a corresponding inter-die connection structure (64) on the side of the third die (60) facing the second die (50) through a conductive through-substrate via (84-2) and an additional metal layer (102) in a redistribution layer (96) between the second and third dies (50, 60). The third die (60) may have a different lateral outline than the second die (50).

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

31.

SWITCHING OSCILLATION REDUCTION FOR POWER SEMICONDUCTOR DEVICE MODULES

      
Application Number 18491456
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-04-25
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Jeon, Oseob
  • Im, Seungwon
  • Thirukoluri, Rajani Kumar
  • Paul, Roveendra

Abstract

In a general aspect, a half-bridge circuit includes a substrate having first, second and third patterned metal layers disposed on a surface. The circuit also includes first and second high-side transistors disposed on the first patterned metal layer, and first and conductive clips electrically coupling, respectively, the first and second high-side transistors with the second patterned metal layer. The circuit also includes first and second low-side transistors disposed on the second patterned metal layer, and third and fourth conductive clips electrically coupling, respectively, the first and second low-side transistors with the third patterned metal layer. The circuit further includes a DC+ terminal electrically coupled with the first patterned metal layer via a first conductive post disposed between the first and second high-side transistors, and a DC− terminal electrically coupled with the third patterned metal layer via a second conductive post disposed between the third and fourth conductive clips.

IPC Classes  ?

  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

32.

STRUCTURE AND METHOD RELATED TO A POWER MODULE USING A HYBRID SPACER

      
Application Number 18535726
Status Pending
Filing Date 2023-12-11
First Publication Date 2024-04-25
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Chen, Liangbiao
  • Liu, Yong
  • Cheng, Tzu-Hsuan
  • St. Germain, Stephen
  • Arbuthnot, Roger

Abstract

In at least one aspect, a method can include shaping a block of flexible spacer material. The method can include shaping a portion of the block of flexible spacer material to receive a solid metal block. The method can include coupling the solid metal block to the portion of the block of flexible spacer material.

IPC Classes  ?

  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

33.

MOLDED POWER MODULES WITH FLUIDIC-CHANNEL COOLED SUBSTRATES

      
Application Number US2023077543
Publication Number 2024/086850
Status In Force
Filing Date 2023-10-23
Publication Date 2024-04-25
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Im, Seungwon
  • Jeon, Oseob
  • Kim, Jihwan
  • Kang, Dongwook

Abstract

In a general aspect, a semiconductor device module (1000) includes a ceramic substrate (1005) having a first surface and a second surface opposite the first surface. A patterned metal layer (410) is disposed on the first surface of the ceramic substrate, and a semiconductor die (1011) is disposed on the patterned metal layer. A cooling structure (1020) is disposed on the second surface of the ceramic substrate, where the cooling structure includes a plurality of fluidic-cooling channels (310). The module also includes a molding compound (1060) that encapsulates the ceramic substrate, the patterned metal layer and the semiconductor die, and partially encapsulates the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
  • H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids

34.

CURRENT SHARING MISMATCH AND SWITCHING OSCILLATION REDUCTION IN POWER SEMICONDUCTOR DEVICE MODULES

      
Application Number US2023077547
Publication Number 2024/086851
Status In Force
Filing Date 2023-10-23
Publication Date 2024-04-25
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Jeon, Oseob
  • Im, Seungwon
  • Thirukoluri, Rajani Kumar
  • Paul, Roveendra

Abstract

In a general aspect, a half-bridge power module (800) includes a substrate (505) having a plurality of patterned metal layers(517a, 530a, 540) disposed thereon. The module also includes respective pluralities of high-side and low-side transistors (510, 520) disposed on the metal layers. A plurality of conductive clips (532, 542) respectively electrically couple the high-side transistors and the low-side transistors with the metal layers. ADC+ terminal (815a), a DC- terminal (825) and an output terminal (835) of the half-bridge module are also respectively, electrically coupled with the plurality of patterned metal layers.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions

35.

CURRENT SHARING MISMATCH REDUCTION IN POWER SEMICONDUCTOR DEVICE MODULES

      
Application Number 18154722
Status Pending
Filing Date 2023-01-13
First Publication Date 2024-04-25
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Jeon, Oseob
  • Im, Seungwon
  • Thirukoluri, Rajani Kumar
  • Paul, Roveendra

Abstract

In a general aspect, a power module includes a substrate having first, second and third patterned metal layers disposed on a surface of the substrate. The module also includes a first high-side transistor disposed on the first patterned metal layer, a second high-side transistor disposed on the first patterned metal layer, a first conductive clip electrically coupling the first high-side transistor with the second patterned metal layer, and a second conductive clip electrically coupling the second high-side transistor with the second patterned metal layer. The module further includes a first low-side transistor disposed on the second patterned metal layer, a second low-side transistor disposed on the second patterned metal layer, a third conductive clip electrically coupling the first low-side transistor with the third patterned metal layer, and a fourth conductive clip electrically coupling the second low-side transistor with the third patterned metal layer.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

36.

ASSEMBLIES WITH EMBEDDED SEMICONDUCTOR DEVICE MODULES AND RELATED METHODS

      
Application Number US2023077083
Publication Number 2024/086573
Status In Force
Filing Date 2023-10-17
Publication Date 2024-04-25
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Zschieschang, Olaf
  • Jeon, Oseob
  • Kim, Jihwan
  • Paul, Roveendra
  • Neumaier, Klaus
  • Teysseyre, Jerome

Abstract

In a general aspect, an assembly (200a) includes a panel of organic substrate core material (220a) having a cavity (221a, 221b) defined therein, a module substrate (212) disposed in the cavity, and a semiconductor die (216, 217) disposed on the module substrate. The assembly also includes a layer of prepreg organic substrate material (220b1), and a metal layer (240a). The module substrate and the semiconductor die are embedded in the cavity by the layer of prepreg organic substrate material and the metal layer. The metal layer is electrically coupled with at least one of the semiconductor die or the module substrate.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

37.

LOW-LATENCY COMMUNICATION PROTOCOL FOR BINAURAL APPLICATIONS

      
Application Number 18391468
Status Pending
Filing Date 2023-12-20
First Publication Date 2024-04-18
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Coenen, Ivo Leonardus
  • Mitchler, Dennis Wayne

Abstract

Hearing instruments, such as hearing aids, may improve a quality of presented audio through the use of a binaural application, such as beamforming. The binaural application may require communication between the hearing instruments so that audio from a left hearing instrument may be combined with audio from a right hearing instrument. The combining at a hearing instrument can require synchronizing audio sampled locally with sampled audio received from wireless communication. This synchronization may cause a noticeable delay of an output of the binaural application if the latency of the wireless communication is not low (e.g., a few samples of delay). Presented herein is a low-latency communication protocol that communicates packets on a sample-by-sample basis and that compensates for delays caused by overhead protocol data transmitted with the audio data.

IPC Classes  ?

38.

LOW STRESS ASYMMETRIC DUAL SIDE MODULE

      
Application Number 18398589
Status Pending
Filing Date 2023-12-28
First Publication Date 2024-04-18
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Chew, Chee Hiong
  • Prajuckamol, Atapol
  • St. Germain, Stephen
  • Lin, Yusheng

Abstract

Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

39.

SEMICONDUCTOR DEVICE WITH STACKED CONDUCTIVE LAYERS AND RELATED METHODS

      
Application Number 18485565
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-04-18
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Noma, Takashi
  • Ishibe, Shinzo

Abstract

A device may include an insulating layer disposed on a frontside of a semiconductor layer, and may include a first conductive contact disposed in a first opening in the insulating layer. The device may include a second conductive contact disposed in a second opening in the insulating layer, and may include a stacked conductive layer disposed on the first conductive contact and excluded from the second conductive contact.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

40.

ASSEMBLIES WITH EMBEDDED SEMICONDUCTOR DEVICE MODULES AND RELATED METHODS

      
Application Number 18487835
Status Pending
Filing Date 2023-10-16
First Publication Date 2024-04-18
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Zschieschang, Olaf
  • Jeon, Oseob
  • Kim, Jihwan
  • Paul, Roveendra
  • Neumaier, Klaus
  • Teysseyre, Jerome

Abstract

In a general aspect, an assembly includes a panel of organic substrate core material having a cavity defined therein, a module substrate disposed in the cavity, and a semiconductor die disposed on the module substrate. The assembly also includes a layer of prepreg organic substrate material, and a metal layer. The module substrate and the semiconductor die are embedded in the cavity by the layer of prepreg organic substrate material and the metal layer. The metal layer is electrically coupled with at least one of the semiconductor die or the module substrate.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

41.

POWER MODULE PACKAGE HAVING MIRRORED LEADS

      
Application Number 18485966
Status Pending
Filing Date 2023-10-12
First Publication Date 2024-04-18
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Im, Seungwon
  • Park, Jeonghyuk
  • Lee, Keunhyuk
  • Teysseyre, Jerome
  • Bilardo, Paolo

Abstract

In one general aspect, an apparatus can include a semiconductor die, a molding material disposed around at least a portion of the semiconductor die, and a pair of leads electrically coupled to the semiconductor die and aligned along a first direction from the molding material. The molding material can define an elongated protrusion aligned along a second direction orthogonal to the first direction, and a notch disposed between the pair of leads.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/495 - Lead-frames

42.

REFERENCE PIXEL COLUMN READOUT

      
Application Number 17938208
Status Pending
Filing Date 2022-10-05
First Publication Date 2024-04-11
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Cowley, Nicholas Paul
  • Talbot, Andrew David

Abstract

An image sensor may include an image sensor pixel array. The image sensor pixel array may include active image sensor pixels that generate image data based on incident light and reference pixels that are optically black for generating reference data for noise compensation. Sets of reference pixels in the same row may be coupled to respective shared readout paths in a source follower binning configuration. The shared readout path may be could to downstream readout circuits. The use of shared readout paths for the reference pixels can reduce the number of reference pixel readout paths. If desired, pixel circuitry may be implemented on a first die, while readout circuitry and at least a portion of the reference pixel readout paths may be implemented on a second die mounted to the first die.

IPC Classes  ?

  • H04N 5/365 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
  • H01L 27/146 - Imager structures
  • H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters

43.

NEGATIVE CHARGE EXTRACTION STRUCTURE FOR EDGE TERMINATION

      
Application Number 18137329
Status Pending
Filing Date 2023-04-20
First Publication Date 2024-04-11
Owner
  • SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
  • SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Seok, Kyoung Wook
  • Drowley, Clifford
  • Walker, Andrew J.
  • Edwards, Andrew P.

Abstract

A gallium nitride (GaN) power device includes a GaN substrate structure having a first surface and a second surface, a metallic layer coupled to the second surface of the GaN substrate structure, and an active region including an array of vertical fin-based field effect transistors (FinFETs) coupled to the GaN substrate structure. The GaN power device also includes an edge termination structure circumscribing the active region and a seal ring structure circumscribing the edge termination structure and comprising a seal ring metal pad operable to conduct charge from the edge termination structure to the metallic layer.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/66 - Types of semiconductor device

44.

INTEGRATED SUBSTRATES AND RELATED METHODS

      
Application Number 18182552
Status Pending
Filing Date 2023-03-13
First Publication Date 2024-04-11
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Jeon, Oseob
  • Kang, Dongwook
  • Im, Seungwon
  • Kim, Jihwan

Abstract

An integrated substrate may include a conductor layer; a heat sink including a plurality of fins extending therefrom; and a dielectric layer including boron nitride chemically bonded to the conductor layer and to the heat sink with an epoxy.

IPC Classes  ?

  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/495 - Lead-frames

45.

BLACK MASK ON GLASS SYSTEMS AND RELATED METHODS

      
Application Number 18473659
Status Pending
Filing Date 2023-09-25
First Publication Date 2024-04-11
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Bardel, Gregg
  • Tai, Shih-Chang
  • Yasuda, Shunsuke
  • Wu, Weng-Jin

Abstract

Implementations of a cover for an image sensor may include an optically transmissive portion and a black mask layer applied as a strip adjacent a perimeter of a largest planar surface of the optically transmissive portion. The first edge of the strip closest to the perimeter may be separated from the perimeter by a predetermined distance.

IPC Classes  ?

46.

SYSTEMS AND METHODS FOR DESIGNING A DISCRETE DEVICE PRODUCT

      
Application Number 18539697
Status Pending
Filing Date 2023-12-14
First Publication Date 2024-04-11
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Victory, James Joseph
  • Neyer, Thomas
  • Xiao, Yunpeng
  • Jang, Hyeongwoo
  • Dingenen, Peter
  • Valenta, Vaclav
  • Baghaie Yazdi, Mehrdad
  • Rexer, Christopher Lawrence
  • Benczkowski, Stanley
  • Bordignon, Thierry
  • Chu, Wai Lun
  • Sickaruk, Roman

Abstract

Implementations disclosed herein may include receiving from a user a selection of at least one die, a package type, and at least one test condition; generating, using a processor, a product die configuration and a product package configuration using a predictive modeling module and the at least one die and the package type; generating a graphic design system file; generating a package bonding diagram; generating a product spice model of the discrete device product using a technology computer aided design module; generating, using a processor, one or more datasheet characteristics of the discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file; and using a second interface generated by a computing device to provide access to the graphic design system file, the package bonding diagram, the product datasheet, and the product SPICE model.

IPC Classes  ?

  • G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
  • G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
  • G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
  • G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G06N 3/08 - Learning methods

47.

POWER MODULE PACKAGE FOR DIRECT COOLING MULTIPLE POWER MODULES

      
Application Number 18542230
Status Pending
Filing Date 2023-12-15
First Publication Date 2024-04-11
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Teysseyre, Jerome
  • Yoo, Inpil
  • Eom, Jooyang

Abstract

According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.

IPC Classes  ?

  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/467 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing gases, e.g. air
  • H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

48.

BODY BRAKE CONTROL FOR MULTISTAGE POWER CONVERTER

      
Application Number 17938397
Status Pending
Filing Date 2022-10-06
First Publication Date 2024-04-11
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Leone, Salvatore
  • Zafarana, Alessandro

Abstract

Systems for power conversion, and controllers and methods for operating a multiage power converter. The method includes determining a target body brake time period for setting a load current of the multistage power converter below a predetermined threshold. The method also includes activating a body brake condition for the multistage power converter. The method further includes turning off each stage in the multistage power converter when the body brake condition is active. The method also includes deactivating the body brake condition after the target body brake time period following an activation of the body brake condition.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters

49.

POWER SYSTEM HAVING MULTI-TRIGGER ALL-PHASE ACTIVATION

      
Application Number 18045630
Status Pending
Filing Date 2022-10-11
First Publication Date 2024-04-11
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Spillane, Margaret
  • Burke, Kieran
  • Dillon, Gary

Abstract

A multi-phase power system configured to add and remove phases according to a plurality of states can increase the efficiency of the power system, which can increase a battery life in mobile applications. After phases are shed, a load may quickly change requiring all phases to be activated before an over current protection triggers a shutdown. The response of the power system to these load transients may be improved through the use of multiple triggers, which can provide an early warning of the changing load requirements more accurately and consistently than a single trigger.

IPC Classes  ?

  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 1/32 - Means for protecting converters other than by automatic disconnection
  • H02M 1/36 - Means for starting or stopping converters

50.

INTEGRATED SUBSTRATES AND RELATED METHODS

      
Application Number US2023075599
Publication Number 2024/076880
Status In Force
Filing Date 2023-09-29
Publication Date 2024-04-11
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Jeon, Oseob
  • Kang, Dongwook
  • Im, Seungwon
  • Kim, Jihwan

Abstract

An integrated substrate (88) may include a conductor layer (92); a heat sink (94) including a plurality of fins extending therefrom; and a dielectric layer (90) including boron nitride chemically bonded to the conductor layer (92) and to the heat sink (94) with an epoxy.

IPC Classes  ?

  • C04B 37/02 - Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/495 - Lead-frames
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • C08K 3/38 - Boron-containing compounds
  • H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
  • H01L 23/367 - Cooling facilitated by shape of device

51.

A COMBINED SHORT-WAVELENGTH INFRARED AND VISIBLE LIGHT SENSOR

      
Application Number US2023076407
Publication Number 2024/077300
Status In Force
Filing Date 2023-10-10
Publication Date 2024-04-11
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Jatou, Ross, F.
  • Korobov, Vladimir
  • Borthakur, Swarnal

Abstract

A sensor includes an array of optically active pixels disposed on a semiconductor die. The array of optically active pixels includes at least one pixel (PI) configured to detect short wavelength infrared radiation (SWIR), and at least one pixel (P2) configured to detect visible light incident on the sensor.

IPC Classes  ?

  • H04N 5/33 - Transforming infrared radiation
  • G01N 21/35 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light
  • H01L 27/146 - Imager structures

52.

SILICON PHOTOMULTIPLIER (SiPM) HAVING AN IMPROVED SIGNAL-TO-NOISE RATIO

      
Application Number US2023075500
Publication Number 2024/073653
Status In Force
Filing Date 2023-09-29
Publication Date 2024-04-04
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Barry, Colin
  • Buckley, Steven John
  • Sesta, Vincenzo
  • Tadmor, Erez

Abstract

A method includes identifying a region of interest (110) on an array of single-photon avalanche photodiodes (300, 310, 320) disposed on a surface (S) of a semiconductor device (100), enabling the single-photon avalanche photodiodes in the region of interest, and disabling the single-photon avalanche photodiodes that are outside the region of interest. The method further includes, in response to illumination incident on the surface of the semiconductor device, combining photocurrent outputs of the single-photon avalanche photodiodes in the region of interest in an analog photocurrent output channel (CH A, CH, B, CH C, CH S) of the semiconductor device.

IPC Classes  ?

  • G05B 19/042 - Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]

53.

SEMICONDUCTOR DEVICES WITH SINGLE-PHOTON AVALANCHE DIODES AND LIGHT SPREADING LENSES

      
Application Number 18527753
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-03-28
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Mcgarvey, Brian Patrick

Abstract

An imaging device may include single-photon avalanche diodes (SPADs). The single-photon avalanche diodes may be arranged in a one-dimensional or two-dimensional array in a SPAD-based semiconductor device. The SPAD-based semiconductor device may also include a transparent cover glass that is formed over the array of SPADs. Each line of SPADs within the SPAD-based semiconductor device may be covered by a respective light spreading lens. The light spreading lens may be formed as a groove in an upper surface of the transparent cover glass. The light spreading lens may have a uniform cross-section along its length. The light spreading lens may be formed as a convex lens on an upper or lower surface of the transparent cover glass.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 31/0232 - Optical elements or arrangements associated with the device
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode

54.

SEMICONDUCTOR PACKAGES WITH AN ARRAY OF SINGLE-PHOTON AVALANCHE DIODES SPLIT BETWEEN MULTIPLE SEMICONDUCTOR DICE

      
Application Number 18525991
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-03-28
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Mcgarvey, Brian Patrick

Abstract

A semiconductor package may include a line array of single-photon avalanche diodes (SPADs). The line array of single-photon avalanche diodes may be split between multiple silicon dice. Each silicon die may be overlapped by at least one lens to focus light away from gaps between the dice and towards the single-photon avalanche diodes. There may be one single-photon avalanche diode for each silicon die or multiple single-photon avalanche diodes for each silicon die. When there are multiple single-photon avalanche diodes for each silicon die, lenses may be formed over only the edge single-photon avalanche diodes.

IPC Classes  ?

  • H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/146 - Imager structures
  • H01L 31/0232 - Optical elements or arrangements associated with the device

55.

Imaging systems with distributed and delay-locked control

      
Application Number 18062920
Grant Number 11943553
Status In Force
Filing Date 2022-12-07
First Publication Date 2024-03-26
Grant Date 2024-03-26
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Fadida, Gal

Abstract

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.

IPC Classes  ?

  • H04N 25/779 - Circuitry for scanning or addressing the pixel array
  • H03K 3/86 - Generating pulses by means of delay lines and not covered by the preceding subgroups
  • H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets
  • H04N 25/709 - Circuitry for control of the power supply
  • H04N 25/711 - Time delay and integration [TDI] registers; TDI shift registers
  • H04N 25/766 - Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

56.

BOOTSTRAP CLAMP CIRCUIT AND METHOD

      
Application Number 17933935
Status Pending
Filing Date 2022-09-21
First Publication Date 2024-03-21
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Ptacek, Karel
  • Chopra, Dhruv

Abstract

A driver is suitable for use with a gallium nitride (GaN) power stage, and includes a voltage regulator and a high side driver. The voltage regulator provides a boot voltage between first and second terminals thereof that varies within a range between a turn-on voltage of a GaN transistor, and a safe voltage limit between a gate and a source thereof throughout an active time of said GaN transistor. The high side driver has an input for receiving a high side drive signal, an output for coupling to said gate of said GaN transistor, a power supply terminal coupled to said first terminal of said voltage regulator, and a ground terminal for coupled to said second terminal of said voltage regulator.

IPC Classes  ?

  • H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

57.

PRECISION OPERATIONAL AMPLIFIER WITH A FLOATING INPUT STAGE

      
Application Number 18262626
Status Pending
Filing Date 2022-03-14
First Publication Date 2024-03-21
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Petroianu, Catalin Ionut

Abstract

The operational amplifier disclosed includes an input stage configured to receive power from a floating supply in a low voltage range that can float according to the common mode voltage at the input. The floating supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage includes a first gain stage including field effect transistors and a second gain stage using bipolar transistors. The gain stages can be implemented differently to accommodate different applications and fabrication capabilities.

IPC Classes  ?

58.

FREQUENCY-DEPENDENT GROUND FAULT CIRCUIT INTERRUPTER

      
Application Number 18450224
Status Pending
Filing Date 2023-08-15
First Publication Date 2024-03-21
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Singh, Rishi Pratap
  • Jensen, Colton
  • Song, Yixin
  • Back, Seunghan

Abstract

Illustrative GFCI devices and methods maintain safety while reducing the risk of unnecessary interruptions. One illustrative GFCI circuit includes: a first operational amplifier configured to couple to a first current transformer that senses a net current through multiple power conductors, the first operational amplifier configured to convert a signal current from a signal terminal of the first current transformer to a signal voltage, the signal voltage having an inverse dependence on frequency; an analog to digital converter configured to provide samples of the signal voltage; and a controller configured to interrupt at least one of the multiple power conductors when an magnitude measurement derived from the samples exceeds a frequency-independent and/or phase-independent threshold a predetermined number of times or for a predetermined time period.

IPC Classes  ?

  • H02H 3/16 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to fault current to earth, frame or mass

59.

LEADFRAME SPACER FOR DOUBLE-SIDED POWER MODULE

      
Application Number 18520361
Status Pending
Filing Date 2023-11-27
First Publication Date 2024-03-21
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Cheng, Tzu-Hsuan
  • Liu, Yong
  • Chen, Liangbiao

Abstract

A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

IPC Classes  ?

  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 21/52 - Mounting semiconductor bodies in containers
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/495 - Lead-frames
  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

60.

ACOUSTIC OBSTACLE DETECTION WITH ENHANCED RESISTANCE TO SYSTEMATIC INTERFERENCE

      
Application Number 18523726
Status Pending
Filing Date 2023-11-29
First Publication Date 2024-03-21
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Hustava, Marek
  • Kostelnik, Pavel

Abstract

An illustrative controller includes: a transmitter to drive the acoustic transducer to generate a series of acoustic bursts; a receiver coupled to the acoustic transducer to sense a response for each acoustic burst in the series; and a processing circuit to derive output data from said responses in part by determining a difference between one of the responses and at least a portion of another one of the responses. Another illustrative controller includes: a transmitter to drive the acoustic transducer to generate a series of acoustic bursts with signature sequence of frequency displacements; a receiver coupled to the acoustic transducer to sense a response for each acoustic burst in the series; and a processing circuit to derive output data from said responses in part by suppressing any peaks not conforming to the signature sequence.

IPC Classes  ?

  • G01S 15/10 - Systems for measuring distance only using transmission of interrupted, pulse-modulated waves
  • G01S 7/524 - Transmitters
  • G01S 7/527 - Extracting wanted echo signals

61.

POWER MODULE PACKAGE WITH STACKED DIRECT BONDED METAL SUBSTRATES

      
Application Number 17931665
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Baek, Jonghwan
  • Park, Jeonghyuk
  • Im, Seungwon
  • Lee, Keunhyuk
  • Lee, Dukyong

Abstract

A package includes a first direct bonded metal (DBM) substrate, a first semiconductor die disposed on a top surface of the first DBM substrate, a second DBM substrate disposed at a height above the first DBM substrate, and a second semiconductor die disposed on a top surface of the second DBM substrate. A wire bond is made between the first semiconductor die disposed on the top surface of the first DBM substrate and the second semiconductor die disposed on the top surface of the second DBM substrate.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

62.

SLEW-RATE BOOST CIRCUITRY

      
Application Number 17931947
Status Pending
Filing Date 2022-09-14
First Publication Date 2024-03-14
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Petroianu, Catalin Ionut
  • Petroianu, Alexandra-Oana

Abstract

The techniques described herein relate to a circuit including an operational amplifier that includes a differential amplifier, a capacitor, and an output stage. The differential amplifier includes a first input and a second input. The output stage is configured to generate an output voltage. The circuit includes a slew-rate boost circuitry connected to the operational amplifier. The slew-rate boost circuitry is configured to detect a voltage differential between the first input and the second input and apply, at an output of the differential amplifier, a boost current to charge the capacitor during a period of time in which the output voltage increases or decreases to a target voltage level.

IPC Classes  ?

63.

SEMICONDUCTOR DEVICE TERMINATION STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE TERMINATION STRUCTURES

      
Application Number 18454328
Status Pending
Filing Date 2023-08-23
First Publication Date 2024-03-14
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Padmanabhan, Balaji
  • Venkatraman, Prasad

Abstract

In an example, a semiconductor device includes an active trench region and an intersecting trench. The active region includes an active shield electrode and the intersecting trench includes an intersecting shield electrode. A coupling trench region connects the active trench region to the intersecting trench region. The coupling trench region includes a coupling shield electrode. The coupling shield electrode and the intersecting shield electrode are provided proximate to a termination mesa region. One or more of the coupling shield electrode or the intersecting shield electrode is thinner than the active shield electrode. The thinner shield electrode reduces depletion in the termination mesa region to improve, among other things, breakdown voltage performance.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

64.

SEMICONDUCTOR DEVICE TERMINATION STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE TERMINATION STRUCTURES

      
Application Number US2023072883
Publication Number 2024/054763
Status In Force
Filing Date 2023-08-25
Publication Date 2024-03-14
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Padmanabhan, Balaji
  • Venkatraman, Prasad

Abstract

In an example, a semiconductor device (10) includes an active trench region (22A) and an intersecting trench region (22C, 22CA, 22CB). The active trench region (22A) includes an active shield electrode (21A) and the intersecting trench region (22C, 22CA, 22CB) includes an intersecting shield electrode (21C, 21C'). A coupling trench region (22B, 22B', 22BA) connects the active trench region (21A) to the intersecting trench region (22C, 22CA, 22CB). The coupling trench region (22B, 22B', 22BA) includes a coupling shield electrode (21B, 21B'). The coupling shield electrode (21B, 21B') and the intersecting shield electrode (21C, 21C') are provided proximate to a termination mesa region (16B, 16B', 16B''). One or more of the coupling shield electrode (21B, 21B') or the intersecting shield electrode (21C, 21C') is thinner than the active shield electrode (21A). The thinner shield electrode reduces depletion in the termination mesa region to improve, among other things, breakdown voltage performance.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/40 - Electrodes
  • H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/336 - Field-effect transistors with an insulated gate

65.

TERMINATION STRUCTURES FOR MOSFETS

      
Application Number US2023073897
Publication Number 2024/055049
Status In Force
Filing Date 2023-09-11
Publication Date 2024-03-14
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Chowdhury, Sauvik
  • Hossain, Zia
  • Yedinak, Joseph Andrew

Abstract

Shielded gate semiconductor devices are disclosed for use in high power applications such as electric vehicles and industrial applications. The devices are formed as mesa (106)/trench (400) structures in which shielded gate electrodes are formed in the trenches. Various trench structures (400, 500, 600, 700) are presented that include tapered portions (401) and end tabs (502, 602, 702, 802) that can be beneficial in managing the distribution of electric charge and associated electric fields. The tapered trenches(400) can be used to increase and stabilize breakdown voltages in a termination region (104) of a semiconductor die (100).

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/283 - Deposition of conductive or insulating materials for electrodes
  • H01L 21/441 - Deposition of conductive or insulating materials for electrodes
  • H01L 21/76 - Making of isolation regions between components

66.

LEADFRAME MOUNTING WITH LEAD INSERTION FOR LEAD WALL BONDING

      
Application Number 17931651
Status Pending
Filing Date 2022-09-13
First Publication Date 2024-03-14
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Chen, Chad
  • Liu, Jiahui
  • Xia, Wuxing
  • Liu, Jingyan

Abstract

A semiconductor device package may include a substrate having an insulating layer with a patterned conductive layer formed thereon, the patterned conductive layer including at least a first pattern portion and a second pattern portion. The semiconductor device package may include a leadframe having a lead that is soldered to the substrate with solder provided in an opening between the first pattern portion and the second pattern portion and with the lead inserted into the opening.

IPC Classes  ?

  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H01L 23/495 - Lead-frames
  • H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

67.

DIE CLEANING SYSTEMS AND RELATED METHODS

      
Application Number 18505215
Status Pending
Filing Date 2023-11-09
First Publication Date 2024-03-07
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Seddon, Michael J.

Abstract

Implementations of methods of forming a plurality of semiconductor die may include forming a damage layer beneath a surface of a die street in a semiconductor substrate, singulating the semiconductor substrate along the die street into a plurality of semiconductor die, and removing one or more particulates in the die street after singulating through applying sonic energy to the plurality of semiconductor die.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

68.

SUPPORTS FOR THINNED SEMICONDUCTOR SUBSTRATES AND RELATED METHODS

      
Application Number 18507176
Status Pending
Filing Date 2023-11-13
First Publication Date 2024-03-07
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Seddon, Michael J.
  • Carney, Francis J.

Abstract

Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.

IPC Classes  ?

  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

69.

Motion-compensated distance sensing with concurrent up-chirp down-chirp waveforms

      
Application Number 17821497
Grant Number 11982740
Status In Force
Filing Date 2022-08-23
First Publication Date 2024-02-29
Grant Date 2024-05-14
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Hustava, Marek
  • Suchy, Tomas
  • Kostelnik, Pavel
  • Bartos, Dalibor

Abstract

Various sensors, sensor controllers, and sensing methods are suitable for use in a multi-channel ultrasonic sensor array such as those used in systems for parking assistance, blind spot monitoring, and driver assistance. One illustrative acoustic sensing method includes: driving an acoustic transducer to send acoustic bursts each including an up-chirp in a first frequency band and a down-chirp in a second frequency band; receiving echo signals responsive to the acoustic bursts from the transducer; and using the echo signals to determine a distance or time of flight from the transducer. Another acoustic sensing method includes: driving an acoustic transducer to send acoustic bursts each including a concurrent up-chirp and down-chirp; receiving echo signals responsive to the acoustic bursts from the transducer; and using the echo signals to determine a distance or time of flight from the transducer.

IPC Classes  ?

  • G01S 15/58 - Velocity or trajectory determination systems; Sense-of-movement determination systems
  • G01S 15/931 - Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles

70.

CYCLIC REDUNDANCY CHECK (CRC) GENERATION

      
Application Number 17822329
Status Pending
Filing Date 2022-08-25
First Publication Date 2024-02-29
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Cami Gonzalez, Sergi

Abstract

A system such as an imaging system may include Cyclic Redundancy Check (CRC) value generation circuitry. The CRC value generation circuitry may include a data splitter that splits an input data bit stream instead multiple split data bit streams each inserted with a number of bits having a value of 0. A plurality of CRC value generators may each have a corresponding input path to receive a respective one of the split data bit streams and generate corresponding partial CRC values. A data combiner coupled to the plurality of Cyclic Redundancy Check value generators may combine the partial CRC values to generate a final CRC value. A normalizer may be coupled between each of the plurality of CRC generators and the data combiner. Two CRC value data storage structures may help the plurality of Cyclic Redundancy Check value generators and the data combiner perform the desired CRC computations.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received

71.

INDUCTIVE ANGULAR POSITION SENSOR

      
Application Number 17822604
Status Pending
Filing Date 2022-08-26
First Publication Date 2024-02-29
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Bertin, Jacques Jean

Abstract

A receiver coil of an inductive angular position sensor can have circuit features that become smaller than reasonable for high resolution measurement designs. This is especially true when multiple receiver coils are used, such as in a three-phase configuration, and when each of the multiple receiver coils is in a twisted loop configuration. The disclosed inductive angular position sensor utilizes different spatial frequencies for a rotor coil and the receiver coils. For example, the spatial frequency of the receiver coils may be kept smaller than the rotor coil. In this condition, the fundamental frequency of the angular position sensor is shifted to the least common multiple of the spatial frequencies, making the angular resolution of the inductive angular position sensor high, while the circuit features of the receiver coils are maintained at a reasonable size.

IPC Classes  ?

  • G01D 5/20 - Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature

72.

SHORT-CIRCUIT DETECTOR FOR ELECTRONIC FUSE CIRCUIT

      
Application Number 18337382
Status Pending
Filing Date 2023-06-19
First Publication Date 2024-02-29
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Forejtek, Jiri
  • Rozsypal, Petr

Abstract

An electronic fuse that includes a clamp circuit to enhance the protection provided by the electronic fuse. The clamp circuit can detect a short circuit condition quickly and transmit a trigger signal to a controller so that a power transistor of the electronic fuse can be turned-OFF before the current through the power transistor causes overheating or damage. The clamp circuit is a dedicated circuit for short-circuit detection that can work with other current control circuits of the electronic fuse. The clamp circuit does not increase the power consumed by the electronic fuse while not in the short circuit condition. The clamp circuit is small and fast because it can use low-voltage devices, even as high voltages are present at the input and output of the electronic fuse.

IPC Classes  ?

  • H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for dc applications
  • H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
  • H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit

73.

SEMICONDUCTOR PACKAGE AND RELATED METHODS

      
Application Number 18490270
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-02-29
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Chew, Chee Hiong
  • Tolentino, Erik Nino
  • Ng, Vemmond Jeng Hung
  • Krishnan, Shutesh

Abstract

Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

74.

HIGH POWER MODULE PACKAGE STRUCTURES

      
Application Number 18502162
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-02-29
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Lin, Yusheng
  • Teysseyre, Jerome

Abstract

In a general aspect, a package includes a semiconductor die disposed between a first high voltage isolation carrier and a second high voltage isolation carrier. The semiconductor die is thermally coupled to the first high voltage isolation carrier. The package also includes a molding material disposed in a space between the semiconductor die and the first high voltage isolation carrier, and a conductive spacer disposed between the semiconductor die and the second high voltage isolation carrier. The conductive spacer is thermally coupled to semiconductor die and to the second high voltage isolation carrier. A longitudinal dimension of the conductive spacer is greater than a longitudinal dimension of the semiconductor die. The molding material encapsulates the semiconductor die and the conductive spacer.

IPC Classes  ?

  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 21/52 - Mounting semiconductor bodies in containers
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
  • H01L 23/498 - Leads on insulating substrates
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

75.

SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING POWER MODULE WITH INTERPOSER AND OPPOSING SUBSTRATES

      
Application Number 18503513
Status Pending
Filing Date 2023-11-07
First Publication Date 2024-02-29
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Zhou, Jinchang
  • Lin, Yusheng
  • Liu, Mingjiao

Abstract

A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
  • H10N 30/50 - Piezoelectric or electrostrictive devices having a stacked or multilayer structure

76.

BATTERY HAZARD DETECTION

      
Application Number 17821986
Status Pending
Filing Date 2022-08-24
First Publication Date 2024-02-29
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Kondo, Hideo

Abstract

A method, system, and integrated circuit are provided for testing a battery within a host device for abnormal conditions. The method includes charging the battery to a fully charged state, then, applying a known load to the battery and discharging the battery to a designated depth of voltage. The known load is removed from the battery, and the open circuit voltage (OCV) of the battery is monitored over time to determine an elapsed time over which the OCV recovers to a designated recovery voltage value. Based on the determined elapsed time, the method determines if the battery has a dangerous condition.

IPC Classes  ?

  • G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC
  • G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
  • G01R 31/374 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with means for correcting the measurement for temperature or ageing
  • G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

77.

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES SEMICONDUCTOR DEVICES

      
Application Number 17822008
Status Pending
Filing Date 2022-08-24
First Publication Date 2024-02-29
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Lysacek, David
  • Hybl, Jan
  • Postulka, Dusan
  • Jarina, Juraj
  • Janirek, Vit
  • Senkova, Alexandra

Abstract

In an example, a method of manufacturing a semiconductor device includes providing a semiconductor substrate comprising an unpolished CZ silicon substrate, a substrate upper side, and a substrate lower side opposite to the substrate upper side. The method includes first annealing the semiconductor substrate at a first temperature in an inert environment for a first time. The method includes second annealing the semiconductor substrate at a second temperature in a wet oxidation environment for a second time. The first annealing dissolves inner wall oxide in bulk region voids and the second annealing fills the voids with semiconductor interstitials. In some examples, the CZ silicon substrate is provided from a CZ ingot grown in the presence of a magnetic field and using continuous counter-doping. The method provides, among other things, a CZ silicon substrate with reduced crystal originated particle (COP) defects, reduced oxygen concentration, and reduced radial resistivity variation.

IPC Classes  ?

  • H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
  • C30B 15/18 - Heating of the melt or the crystallised materials using direct resistance heating in addition to other methods of heating, e.g. using Peltier heat
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

78.

SEALING METHOD FOR DIRECT LIQUID COOLED POWER ELECTRONICS PACKAGE

      
Application Number 18364330
Status Pending
Filing Date 2023-08-02
First Publication Date 2024-02-22
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Paul, Roveendra
  • Kim, Hyungsoo

Abstract

A package includes a power electronics module disposed between a first bracket and a second bracket with the power electronics module covering openings in the first bracket and the second bracket. Leak-proof joints are formed between surfaces of the power electronics module and the first bracket and the second bracket. A first cover beam is disposed on, and joined to, the first bracket to enclose a first cooling fluid channel for cooling fluid flow over the power electronics module. A second cover beam is disposed on, and joined to, the second bracket to enclose a second cooling fluid channel for cooling fluid flow over the power electronics module. The package includes end connectors that have input and output ports for cooling fluid flow through the first cooling fluid channel and the second cooling fluid channel.

IPC Classes  ?

  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

79.

FAST DEVICE REINITIALIZATION ON DSI3 BUS

      
Application Number 18162972
Status Pending
Filing Date 2023-02-01
First Publication Date 2024-02-22
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Hustava, Marek

Abstract

Accordingly, there is disclosed herein host device and bus communication method that enables fast sensor device reinitialization that minimizes outage time associated with an unexpected device reset. One illustrative bus communication method includes: providing each of one or more slave devices with a dynamically-determined bus address; querying each of the dynamically-determined bus addresses to obtain a unique device identifier associated with that dynamically-determined bus address; receiving a sequence of data frames each having time-division multiplexed data from the one or more slave devices; and between data frames in the sequence, checking to determine whether any of the one or more slave devices has been reset.

IPC Classes  ?

80.

PLASMA-SINGULATED, CONTAMINANT-REDUCED SEMICONDUCTOR DIE

      
Application Number 18490923
Status Pending
Filing Date 2023-10-20
First Publication Date 2024-02-15
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Hong, Jeongpyo
  • Md Sum, Mohd Akbar
  • Grivna, Gordon M.

Abstract

Described implementations include a contaminant-free plasma singulation process, in which residues of materials used during plasma singulation are fully removed from sidewalls of a resulting semiconductor die, without damaging the semiconductor die. From such a contaminant-free plasma singulation process, a semiconductor die may be manufactured. The semiconductor die may include a first plurality of sidewall recesses formed in a sidewall of a substrate of the semiconductor die between a first surface and a second surface of the substrate, each having at most a first depth, as well as a second plurality of sidewall recesses formed in the sidewall of the substrate and disposed between the first plurality of sidewall recesses and the second surface, each having at least a second depth that is greater than the first depth.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

81.

PRECISION OPERATIONAL AMPLIFIER USING FLOATING INPUT STAGE

      
Application Number 18259383
Status Pending
Filing Date 2022-02-03
First Publication Date 2024-02-15
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Petroianu, Catalin Ionut

Abstract

The operational amplifier disclosed includes an input stage configured to receive power from a floating supply circuit in in a low voltage range that can float according to the common mode voltage at the input. The low voltage supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage utilizes a first gain block and a second gain block. The first gain block is configured to have a low offset voltage while the second gain h block is configured to have a high gain. Dividing these aspects over separate gain blocks improves the precision and noise performance of the operational amplifier. The operational amplifier has high gain at low frequencies and at high frequencies due to a topology that combines a low gain, high bandwidth path with a high gain, low bandwidth path at the output.

IPC Classes  ?

  • H03F 3/45 - Differential amplifiers
  • H03G 3/32 - Automatic control in amplifiers having semiconductor devices the control being dependent upon ambient noise level or sound level
  • H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements

82.

TRANSFER MOLDED POWER MODULES AND METHODS OF MANUFACTURE

      
Application Number 18354863
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-02-15
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Im, Seungwon
  • Jeon, Oseob
  • Kim, Jihwan
  • Kang, Dongwook

Abstract

In a general aspect, an electronic device assembly includes a circuit including at least one semiconductor die, and a signal lead electrically coupled with the circuit. The signal lead has a hole defined therethrough. The assembly further includes an electrically conductive signal pin holder disposed in the hole of the signal lead. The electrically conductive signal pin holder is electrically coupled with the signal lead. The assembly also includes a molding compound encapsulating, at least, the circuit; a portion of the signal lead including the hole; and a portion of the electrically conductive signal pin holder. An open end of the electrically conductive signal pin holder is accessible outside the molding compound.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

83.

Semiconductor Devices with Single-Photon Avalanche Diodes, Light Scattering Structures, and Multiple Isolation Structures

      
Application Number 18493996
Status Pending
Filing Date 2023-10-25
First Publication Date 2024-02-15
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Sulfridge, Marc Allen
  • Deignan, Anne
  • Jedidi, Nader
  • Keyes, Michael Gerard

Abstract

An imaging device may include single-photon avalanche diodes (SPADs). To improve the sensitivity and signal-to-noise ratio of the SPADs, light scattering structures may be formed in the semiconductor substrate to increase the path length of incident light through the semiconductor substrate. To mitigate crosstalk, multiple rings of isolation structures may be formed around the SPAD. An outer deep trench isolation structure may include a metal filler such as tungsten and may be configured to absorb light. The outer deep trench isolation structure therefore prevents crosstalk between adjacent SPADs. Additionally, one or more inner deep trench isolation structures may be included. The inner deep trench isolation structures may include a low-index filler to reflect light and keep incident light in the active area of the SPAD.

IPC Classes  ?

  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
  • H01L 27/146 - Imager structures
  • H01L 31/055 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means where light is absorbed and re-emitted at a different wavelength by the optical element directly associated or integrated with the PV cell, e.g. by using luminescent material, fluorescent concentrators or up-conversion arrangements
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
  • H01L 31/0232 - Optical elements or arrangements associated with the device
  • G02B 3/06 - Simple or compound lenses with non-spherical faces with cylindrical or toric faces

84.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

      
Application Number 17818880
Status Pending
Filing Date 2022-08-10
First Publication Date 2024-02-15
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Elhami Khorasani, Arash
  • Griswold, Mark

Abstract

In an example, a semiconductor device includes a region of semiconductor material, a first dielectric over the region of semiconductor material, a first gate conductor over a first portion of the first dielectric, and a second gate conductor over a second portion of the first dielectric and laterally spaced apart from the first gate conductor. A first conductor is coupled to the first gate conductor and a second conductor coupled to the second gate conductor and laterally separated from the first conductor by a first spacing. A second dielectric is within the first spacing. The first conductor and the second conductor are laterally capacitively coupled, the first gate conductor is vertically capacitively coupled to the region of semiconductor material, and the second gate conductor is vertically capacitively coupled to the region of semiconductor material.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

85.

ADJUSTABLE CLAMP FINGER DESIGN

      
Application Number 17819469
Status Pending
Filing Date 2022-08-12
First Publication Date 2024-02-15
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Sun, Sen
  • Feng, Kun
  • Cheng, Hu
  • Wang, Naima

Abstract

Implementations of a clamp finger may include a first portion including at least one tip configured to clamp a substrate against an anvil during a bonding operation; and a second portion including a first opening therethrough configured to permit coupling of the second portion with a clamping bridge. The first portion may be slidably coupled with the second portion through a rail and the first portion may include an opening therethrough configured to receive a screw that fixedly couples the at least one tip of the first portion at a desired position relative to the second portion.

IPC Classes  ?

  • B25B 1/24 - Vices - Details, e.g. jaws of special shape, slideways

86.

Dual-channel acoustic distance measurement circuit and method

      
Application Number 17938191
Grant Number 11899106
Status In Force
Filing Date 2022-10-05
First Publication Date 2024-02-13
Grant Date 2024-02-13
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Hustava, Marek
  • Kostelnik, Pavel

Abstract

An acoustic distance measurement circuit includes a transmitter, a receiver, and a controller. The transmitter has an output adapted to be coupled to an acoustic transducer for providing a selected one of an amplitude-modulation (AM) signal in an AM mode and a chirp signal in a chirp mode. The receiver has an input adapted to be coupled to the acoustic transducer, and an output for providing a digital received signal. The controller is operative during a first measurement period to: place the transmitter into one of the AM mode and the chirp mode using a first channel, selectively detect a direct echo in the first channel of the digital received signal of the one of the AM signal and the chirp signal, and selectively detect an indirect echo in a second channel of the digital received signal of another one of the AM signal and the chirp signal.

IPC Classes  ?

  • G01S 15/931 - Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles
  • G01S 7/526 - Receivers
  • B60Q 9/00 - Arrangement or adaptation of signal devices not provided for in one of main groups

87.

JET IMPINGEMENT COOLING WITH BYPASS FLUID PORTION FOR HIGH POWER SEMICONDUCTOR DEVICES

      
Application Number 18167998
Status Pending
Filing Date 2023-02-13
First Publication Date 2024-02-08
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Mookken, John

Abstract

A jet impingement cooling assembly for semiconductor devices includes an inlet chamber configured to receive an inlet fluid flow, and a jet plate having a plurality of jet nozzles formed therein and coupled to the inlet chamber, and positioned to direct a jet fluid portion of the inlet fluid flow from the inlet chamber through the jet nozzles. The jet impingement cooling assembly may further include an outlet chamber positioned to receive the jet fluid portion once the jet fluid portion has passed through the jet nozzles, and at least one bypass nozzle in fluid connection with the inlet chamber and configured to direct a bypass fluid portion of the inlet fluid flow into the outlet chamber with the jet fluid portion to thereby define an outlet fluid flow.

IPC Classes  ?

  • H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids

88.

RESONANT CONVERTER WITH DUAL-MODE CONTROL

      
Application Number 18481779
Status Pending
Filing Date 2023-10-05
First Publication Date 2024-02-08
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Chiu, Chen-Hua
  • Moon, Sangcheol

Abstract

It may be desirable to limit the switching frequency of a pulse frequency modulated (PFM) resonant converter, however certain load conditions and/or startup condition require high switching frequencies to regulate an output voltage. The disclosed resonant converter can limit a maximum switching frequency while regulating an output voltage by shifting from PFM to phase-difference modulation based on a load condition. The appropriate modulation can be applied based on a comparison between a charge-control signal and a load-control signal.

IPC Classes  ?

  • H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

89.

METHOD OF FORMING A SEMICONDUCTOR DEVICE

      
Application Number 18489989
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-02-08
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Chen, Weize
  • Griswold, Mark

Abstract

In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 21/761 - PN junctions

90.

ELECTRICAL INTERCONNECTION OF IMAGE SENSOR PACKAGE

      
Application Number 18490217
Status Pending
Filing Date 2023-10-19
First Publication Date 2024-02-08
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Hsu, Shou-Chian

Abstract

Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side and an active area on the second side of the die. The semiconductor packages may also include two or more bumps coupled to two or more die pads on a second side of the die. The semiconductor packages may include an optically transmissive lid coupled to the semiconductor die through an adhesive, two or more bumps, and a first redistribution layer (RDL). The semiconductor package may include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. The first RDL may extend to an edge of the semiconductor die.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

91.

SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES

      
Application Number 18067973
Status Pending
Filing Date 2022-12-19
First Publication Date 2024-02-08
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Elhami Khorasani, Arash

Abstract

In an example, a semiconductor structure includes a region of semiconductor material of a first conductivity type and a first side. A doped region of a second conductivity type is within the region of semiconductor material at a first depth. A semiconductor device in a first portion of the region of semiconductor material and includes a first current carrying region of the second conductivity type and a second current carrying region. A PN diode is in a second portion of the region of semiconductor material and includes a cathode region and anode region. The cathode region is coupled to the first current carrying region, the anode region is coupled to the doped region, and the doped region is configured to electrically isolate the semiconductor device from region of semiconductor material below the doped region in response to a forward bias applied to the semiconductor.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device

92.

Image Sensor with a Bond Pad

      
Application Number 18172730
Status Pending
Filing Date 2023-02-22
First Publication Date 2024-02-01
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Sulfridge, Marc Allen
  • Crofoot, William
  • Borthakur, Swarnal

Abstract

An image sensor may include a sensor chip that is bonded to an application-specific integrated circuit (ASIC) chip. A bond pad for the image sensor may be formed in the ASIC chip and exposed through a trench in the sensor chip. The image sensor may include a conductive light shield at a periphery of the image sensor to shield optically black pixels. An opaque layer may be formed over the conductive light shield to mitigate reflections off the conductive light shield. An anti-reflective layer may be formed over the pixel array. The anti-reflective layer may have a different thickness over the pixel array than in the trench for the bond pad.

IPC Classes  ?

93.

DIRECT SUBSTRATE-SIDE COOLING IN POWER DEVICE MODULE

      
Application Number 17814949
Status Pending
Filing Date 2022-07-26
First Publication Date 2024-02-01
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Prajuckamol, Atapol
  • Chew, Chee Hiong
  • Yao, Yushuang

Abstract

A method includes disposing at least one power device between a first direct bonded metal (DBM) substrate and a second DMB substrate and thermally coupling a plurality of pipes to a top side of the first DBM substrate opposite a side of the first DBM substrate with the at least one power device. The plurality of pipes is configured to carry cooling fluids in thermal contact with the first DBM substrate.

IPC Classes  ?

  • H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

94.

MONITORING TEMPERATURE PER PHASE IN A MULTIPHASE POWER STAGE

      
Application Number 17815984
Status Pending
Filing Date 2022-07-29
First Publication Date 2024-02-01
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Spillane, Margaret
  • Kelliher, Kevin
  • Cregg, Owen
  • Harriman, Paul J.

Abstract

A multiphase power stage that includes addressing and communication techniques to read temperatures of the phases for thermal load balancing is disclosed. The disclosure describes driver modules that can be assigned addresses for serial communication on a common communication bus by temporarily communicating the addresses over dedicated pulse width modulation connections between the driver modules and the controller. After assignment, a temperature request message, addressed to a driver module, can trigger the driver module to transmit an analog temperature signal to a common temperature bus coupled between the driver modules and the controller. The temperatures of the driver modules may be collected in order to activate and deactivate driver modules based on their temperatures, which can balance a thermal load on the multiphase power stage.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/32 - Means for protecting converters other than by automatic disconnection

95.

ADDRESSING MULTIPHASE POWER STAGE MODULES FOR POWER STATE AND THERMAL MANAGEMENT

      
Application Number 17815995
Status Pending
Filing Date 2022-07-29
First Publication Date 2024-02-01
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Zou, Han
  • Cregg, Owen
  • Spillane, Margaret
  • Harriman, Paul J.
  • Kelliher, Kevin

Abstract

A power stage configured for assigning each phase a unique address is disclosed. In particular, the disclosed power stage includes temporarily using a dedicated pulse width modulation (PWM) connection between a controller and a phase to assign a unique address to the phase. Then, after the assignment, the PWM connection may be returned to use for regulation, while the phases can communicate over a common communication bus using their assigned addresses. This addressed communication can be used to control a power state of all phases, all phases of a particular rail, or a particular phase. Controlling the power state with addressed commands communicated over a communication bus can help reduce the current consumed by the power stage during light load conditions or sleep states.

IPC Classes  ?

  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

96.

METHOD AND APPARATUS FOR DIGITAL, CLOSED-LOOP CONTROL OF CRCM SWITCH-MODE POWER CONVERTERS

      
Application Number 18233255
Status Pending
Filing Date 2023-08-11
First Publication Date 2024-02-01
Owner
  • SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
  • SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Lind, Anders

Abstract

A method of setting a synchronous rectifier on-time value includes determining that a time interval has occurred, receiving a number of triangular current mode (TCM) pulses measured during the time interval, and determining a pulse comparison value equal to a number of switching period pulses during the time interval minus the number of TCM pulses during the time interval. The method also includes increasing the synchronous rectifier on-time if the pulse comparison value is greater than or equal to a threshold and decreasing the synchronous rectifier on-time if the pulse comparison value is less than the threshold.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
  • H02M 1/32 - Means for protecting converters other than by automatic disconnection
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M 7/219 - Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

97.

METHOD FOR DEFINING A GAP HEIGHT WITHIN AN IMAGE SENSOR PACKAGE

      
Application Number 18487611
Status Pending
Filing Date 2023-10-16
First Publication Date 2024-02-01
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor Hsieh, Yu-Te

Abstract

According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, a light transmitting member, and a plurality of pillar members disposed between and contacting the image sensor die and the light transmitting member. A height of the plurality of pillar members defines a gap height between an active region of the image sensor die and the light transmitting member. The image sensor package including a bonding material that couples the light transmitting member to the image sensor. The bonding material contacts a side of a pillar member, of the plurality of pillar members, that extends between a first end contacting the light transmitting member and a second end contacting the image sensor die.

IPC Classes  ?

98.

LED driver suitable for low-voltage operation and method therefor

      
Application Number 17813405
Grant Number 11985744
Status In Force
Filing Date 2022-07-19
First Publication Date 2024-01-25
Grant Date 2024-05-14
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Bras, Sebastien
  • Plojhar, Jan

Abstract

In one form, a switching controller includes a buck controller and a bypass circuit. The buck controller has an input for receiving a variable voltage, an output for providing a buck voltage by switching the variable voltage into an inductive output filter according to a switching signal having a variable duty cycle to regulate a current into a load. The bypass circuit is coupled to the buck controller for comparing the variable duty cycle of the switching signal to a threshold, for activating a bypass signal in response to the variable duty cycle exceeding the threshold, and for subsequently de-activating the bypass signal according to a predetermined algorithm.

IPC Classes  ?

  • H05B 45/375 - Switched mode power supply [SMPS] using buck topology
  • H05B 45/14 - Controlling the intensity of the light using electrical feedback from LEDs or from LED modules
  • H05B 45/44 - Circuit arrangements for operating light-emitting diodes [LED] - Details of LED load circuits with an active control inside an LED matrix

99.

SYSTEMS AND METHODS FOR DESIGNING A MODULE SEMICONDUCTOR PRODUCT

      
Application Number 18479179
Status Pending
Filing Date 2023-10-02
First Publication Date 2024-01-25
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Victory, James Joseph
  • Neumaier, Klaus
  • Xiao, Yunpeng
  • Harper, Jonathan
  • Valenta, Vaclav
  • Benczkowski, Stanley
  • Bordignon, Thierry
  • Chu, Wai Lun

Abstract

Implementations of a method of designing a module semiconductor product may include receiving a selection of a module type, one or more die, a placement of one or more wires, clips, or pins; and generating, using a processor, a module configuration file. The method may include generating a module bonding diagram using a build diagram system module; selecting one or more SPICE models corresponding with the die; and generating a product SPICE model and a three dimensional model for the module semiconductor product. The method may include generating one or more datasheet characteristics of the module semiconductor product with at least the product SPICE model and the product simulation module, generating a product datasheet for the module semiconductor product using the datasheet formation module, and providing access to at least the module bonding diagram, the product SPICE model, the three dimensional model, and the product datasheet to the user.

IPC Classes  ?

  • G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
  • G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
  • G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
  • G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G06N 3/08 - Learning methods

100.

MODULE WITH SUBSTRATE RECESS FOR CONDUCTIVE-BONDING COMPONENT

      
Application Number 18479565
Status Pending
Filing Date 2023-10-02
First Publication Date 2024-01-25
Owner SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (USA)
Inventor
  • Gu, Leo
  • Ji, Sixin
  • Chang, Jie
  • Lee, Keunhyuk
  • Liu, Yong

Abstract

In one general aspect, a method can include forming a recess and a mesa in a metal layer associated with a substrate, and disposing a first portion of a conductive-bonding component on the mesa and a second portion of the conductive-bonding component in the recess. The method can include disposing a semiconductor component on the conductive-bonding component such that the second portion of the conductive-bonding component is disposed between an edge of the semiconductor component and a bottom surface of the recess.

IPC Classes  ?

  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
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