An integrated substrate (88) may include a conductor layer (92); a heat sink (94) including a plurality of fins extending therefrom; and a dielectric layer (90) including boron nitride chemically bonded to the conductor layer (92) and to the heat sink (94) with an epoxy.
C04B 37/02 - Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/373 - Cooling facilitated by selection of materials for the device
A sensor (200, 500, 700) includes an array of optically active pixels disposed on a semiconductor die (210, 510, 710). The array of optically active pixels includes at least one pixel (P1) configured to detect short wavelength infrared radiation (SWIR), and at least one pixel (P2) configured to detect visible light incident on the sensor.
H04N 23/13 - Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths with multiple sensors
H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
3.
SILICON PHOTOMULTIPLIER (SiPM) HAVING AN IMPROVED SIGNAL-TO-NOISE RATIO
A method includes identifying a region of interest (110) on an array of single-photon avalanche photodiodes (300, 310, 320) disposed on a surface (S) of a semiconductor device (100), enabling the single-photon avalanche photodiodes in the region of interest, and disabling the single-photon avalanche photodiodes that are outside the region of interest. The method further includes, in response to illumination incident on the surface of the semiconductor device, combining photocurrent outputs of the single-photon avalanche photodiodes in the region of interest in an analog photocurrent output channel (CH A, CH, B, CH C, CH S) of the semiconductor device.
4.
SEMICONDUCTOR DEVICE TERMINATION STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE TERMINATION STRUCTURES
In an example, a semiconductor device (10) includes an active trench region (22A) and an intersecting trench region (22C, 22CA, 22CB). The active trench region (22A) includes an active shield electrode (21A) and the intersecting trench region (22C, 22CA, 22CB) includes an intersecting shield electrode (21C, 21C'). A coupling trench region (22B, 22B', 22BA) connects the active trench region (21A) to the intersecting trench region (22C, 22CA, 22CB). The coupling trench region (22B, 22B', 22BA) includes a coupling shield electrode (21B, 21B'). The coupling shield electrode (21B, 21B') and the intersecting shield electrode (21C, 21C') are provided proximate to a termination mesa region (16B, 16B', 16B''). One or more of the coupling shield electrode (21B, 21B') or the intersecting shield electrode (21C, 21C') is thinner than the active shield electrode (21A). The thinner shield electrode reduces depletion in the termination mesa region to improve, among other things, breakdown voltage performance.
Shielded gate semiconductor devices are disclosed for use in high power applications such as electric vehicles and industrial applications. The devices are formed as mesa (106)/trench (400) structures in which shielded gate electrodes are formed in the trenches. Various trench structures (400, 500, 600, 700) are presented that include tapered portions (401) and end tabs (502, 602, 702, 802) that can be beneficial in managing the distribution of electric charge and associated electric fields. The tapered trenches(400) can be used to increase and stabilize breakdown voltages in a termination region (104) of a semiconductor die (100).
H01L 29/86 - Types of semiconductor device controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
6.
DIODES WITH SCHOTTKY CONTACT INCLUDING LOCALIZED SURFACE REGIONS
In a general aspect, a diode (100) includes a substrate (102) of a first conductivity type, a semiconductor layer (104) of the first conductivity type disposed on the substrate and including a drift region (120), a shield region (110a) of a second conductivity type disposed in the semiconductor layer adjacent to the drift region, and a surface region (132a) of the first conductivity type disposed in a first portion of the drift region adjacent to the shield region. The surface region has a doping concentration greater than a doping concentration of a second portion of the drift region adjacent to the surface region. The second portion excludes the surface region. The diode includes a Schottky material (130) disposed on at least a portion of the shield region, the surface region in the first portion of the drift region; and the second portion of the drift region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
In a general aspect, a diode (100, 200) includes a substrate (102, 202) and a semiconductor layer (104, 204) of a first conductivity type disposed on the substrate and including a drift region (120, 220); a shield region (110a, 110b, 210a, 210b) of a second conductivity type disposed in the semiconductor layer adjacent to the drift region; a first Schottky material (132a, 132b, 236a, 236b) disposed on a portion of the shield region and a first portion of the drift region, and defining a first Schottky contact (142a, 142b, 246a, 246b) with the drift region; and a second Schottky material (130, 232a, 232b) disposed on a second portion of the drift region adjacent to the first Schottky material, and defining a second Schottky contact (240, 242a, 242b) with the drift region. A barrier height of the first Schottky contact is less than a barrier height of the second Schottky contact.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
8.
TRENCH CHANNEL SEMICONDUCTOR DEVICES AND RELATED METHODS
Implementations of a semiconductor device may include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device may include a trench channel adjacent to the trench and two doped pillars of a second conductivity type extending on each side of the first conductivity type doped pillar where a ratio of a depth of each of the two second conductivity type doped pillars to a depth of the trench into the substrate material may be at least 1.6 to 1.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
In one general aspect, an apparatus can include a substrate (110, 410) having a semiconductor region (112, 122), and a trench (10, 40) defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode (130, 430) disposed in the trench and insulated from the sidewall of the trench by a shield dielectric (SD10), the shield dielectric having a low-k dielectric portion (LK10, LK40) and a high-k dielectric portion (HK10, HK40). The apparatus can include a gate electrode (120, 420) disposed in the trench and at least partially surrounded by a gate dielectric (GD10, GD40), and an inter-electrode dielectric (IE10, IE40) disposed between the shield electrode and the gate electrode.
An integrated circuit package (34, 34', 34'') may be implemented by stacked first, second, and third integrated circuit dies (40, 50, 60). The first and second dies (40, 50) may be bonded to each other using corresponding inter-die connection structures (74-1, 84-1) at respective interfacial surfaces facing the other die. The second die (50) may also include a metal layer (84-2) for connecting to the third die (60) at its interfacial surface with the first die (40). The metal layer (84-2) may be connected to a corresponding inter-die connection structure (64) on the side of the third die (60) facing the second die (50) through a conductive through-substrate via (84-2) and an additional metal layer (102) in a redistribution layer (96) between the second and third dies (50, 60). The third die (60) may have a different lateral outline than the second die (50).
A method may include determining, by an access point, which stations among multiple stations are permitted access to a wireless communication medium in a subsequent uplink frame. The method may also include broadcasting an uplink map to the stations, where the uplink map identifies a first station of the multiple stations as permitted access to the wireless communication medium. The uplink map may also identify an allocation of the subsequent uplink frame for the first station. The method may also include, during the allocation of the subsequent uplink frame allocated to the first station, receiving: an acknowledgment (ACK) of downlink data transmitted to the first station, uplink data, a resource allocation request from the first station requesting access to a second subsequent uplink frame, and/or combinations thereof.
A device (100, 250) includes a mesa (102, 202, 302, 402, 502) disposed between a pair of vertical trenches (101, 201, 301, 401, 501, 801) in a semiconductor substrate (105, 210, 310). A gate electrode (104g, 201G, 301G) is disposed in each of the pair of vertical trenches (101, 201, 301, 401, 501, 801), and a shield electrode (104s, 201S, 301S) is disposed below each of the gate electrodes (104g, 201G, 301G) in the pair of vertical trenches (101, 201, 301, 401, 501, 801). The device (100, 250) further includes a bridge connection trench (205, 305, 405, 505) traversing the mesa (102, 202, 302, 402, 502). The bridge connection trench (205, 305, 405, 505) is in fluid communication with each of the pair of vertical trenches (101, 201, 301, 401, 501, 801). A bridge shield electrode (204S, 304S) is disposed in the bridge connection trench (205, 305, 405, 505) and is coupled to the shield electrode (104s, 201S, 301S) disposed below each of the gate electrodes (104g, 201G, 301G) in the pair of vertical trenches (101, 201, 301, 401, 501, 801).
A method includes defining a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of a first type that extend in a longitudinal direction in a semiconductor substrate, and defining a trench (105, 105-1, 105-2, 105-3, 105-4) of a second type extending in a lateral direction and intersecting the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type. The trench (105, 105-1, 105-2, 105-3, 105-4) of the second type is in fluid communication with each of the intersected plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type. The method further includes disposing a shield poly layer (111) in the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type and the trench (105, 105-1, 105-2, 105-3, 105-4) of the second type, disposing an inter-poly dielectric layer (112) and a gate poly layer (108) above the shield poly layer (111) in the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type and the trench (105, 105-1, 105-2, 105-3, 105-4) of the second type, and forming an electrical contact to the shield poly layer (111) through an opening (106, 16) in the inter-poly dielectric layer (112) and the gate poly layer (108) disposed in the trench of the second type.
The operational amplifier disclosed includes an input stage configured to receive power from a floating supply in a low voltage range that can float according to the common mode voltage at the input. The floating supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage includes a first gain stage including field effect transistors and a second gain stage using bipolar transistors. The gain stages can be implemented differently to accommodate different applications and fabrication capabilities.
In a general aspect, a semiconductor device can (100) include a plurality of vertical transistor segments (200, 300) disposed in an active region (110) of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes (206b, 306b). A first dielectric (415, 915, 1015) can be disposed on the active region. An electrically conductive grid (130, 230, 330, 430, 630, 930, 1030) can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts (430a, 630a, 930a, 1030a) formed through the first dielectric. A second dielectric (925) can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion (951) that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact (930a) to the electrically conductive grid formed through the second dielectric.
The operational amplifier disclosed includes an input stage configured to receive power from a floating supply circuit in a low voltage range that can float according to the common mode voltage at the input. The low voltage supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage utilizes a first gain block and a second gain block. The first gain block is configured to have a low offset voltage while the second gain block is configured to have a high gain. Dividing these aspects over separate gain blocks improves the precision and noise performance of the operational amplifier. The operational amplifier has high gain at low frequencies and at high frequencies due to a topology that combines a low gain, high bandwidth path with a high gain, low bandwidth path at the output.
Multiple-input multiple-output (MIMO) radar systems are equipped with channel extenders to further increase the number of receive and/or transmit antennas that can be supported by a given radar transceiver. One illustrative radar system includes: a radar transceiver to generate a transmit signal and to downconvert at least one receive signal; and a receive-side extender that couples to a set of multiple receive antennas to obtain a set of multiple input signals, that adjustably phase-shifts each of the multiple input signals to produce a set of phase-shifted signals, and that couples to the radar transceiver to provide the at least one receive signal, the at least one receive signal being a sum of the phase-shifted signals. An illustrative receive-side extender includes: multiple phase shifters each providing an adjustable phase shift to a respective input signal; a power combiner that forms a receive signal by combining outputs of the multiple phase shifters.
G01S 7/35 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of non-pulse systems
A centralized occupancy detection system enables monitoring of multiple seats, or more generally, multiple stations, with a single sensor. One illustrative vehicle includes: one or more stations each configured to accommodate an occupant of the vehicle, a radar-reflective surface, and a radar transceiver configured to use the radar-reflective surface to detect an occupant of at least one of the stations. Another illustrative vehicle includes: multiple stations to each accommodate an occupant of the vehicle, and a radar transceiver configured to examine each of the multiple stations to determine whether that station has an occupant.
A SiC MOSFET device with alternating p-well widths (116a, 118a), including an undulating channel (110, 110a, 110b), is described. The undulating channel (110, 110a, 110b) provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs) (112a, 112b). The multi-width JFETs (112a, 112b) enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width (112a) into a JFET of a second width (112b).
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
21.
TERMINATION STRUCTURES WITH REDUCED DYNAMIC OUTPUT CAPACITANCE LOSS
In a general aspect, a semiconductor device (100, 400, 700, 900) can include a substrate (110, 410, 710, 910) of a first conductivity type, an active region (120, 420, 720, 920) disposed in the substrate, and a termination region (T) disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (130, 420, 730, 930) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The junction termination extension can have a first depletion stopper region (132, 432, 732, 932) disposed in an upper portion of the junction termination extension, a second depletion stopper region (134, 434, 734, 934) disposed in a lower portion of the junction termination extension, and a high carrier mobility region (136, 436, 736, 936) disposed between the first depletion stopper region and the second depletion stopper region.
A data logger system is disclosed. Specific implementations include a flexible data logger system. The data logger system may include a flexible substrate and a radio-frequency identification (RFID) communications module coupled to the flexible substrate. The RFID communications module may include an antenna coupled with a RFID chip. The data logger system may also include a microprocessor and a memory module coupled to the flexible substrate, the microprocessor and the memory module electrically coupled with the RFID communications module. The data logger system may also include a temperature sensor coupled to the flexible substrate, the temperature sensor electrically coupled with the microprocessor and memory module, and a power source coupled to the flexible substrate, the power source electrically coupled with the microprocessor, the memory module, the temperature sensor, and the RFID communications module.
An example method may include receiving, from a wireless sniffer, sniffer data for a window of time, where the sniffer data may include wireless signal data. The method may also include obtaining corresponding access point data from an access point in a wireless network for at least part of the window of time for which the sniffer data is received. The method may additionally include analyzing the sniffer data and the corresponding access point data to assess performance of the wireless network.
A transceiver (103, 228) communicates with a station (105a, 105b) in a first network (101) and includes a detection circuit (236) that detects a signal in a second network (109) from a second transceiver (111, 228) to a second station (105, 105d). A coverage area of the second network (109) overlaps the first network (101). The detection circuit (236) determines a second symbol alignment of the signal in the second network (109) based on a preamble. The transceiver (103, 228) includes a precoding determination circuit (237) coupled to transmit chains (230) that determines a precoding matrix and the first symbol alignment. The first symbol alignment is synchronized with the second symbol alignment. The transmit chains (230) pre-code a signal in the first network (101) using the precoding matrix and align symbols of the signal in the first network (101) according to the first symbol alignment.
H04B 7/024 - Co-operative use of antennas at several sites, e.g. in co-ordinated multipoint or co-operative multiple-input multiple-output [MIMO] systems
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
SiC Schottky rectifiers with surge current ruggedness are described that may be configured to provide multiple types of surge current protection. Different current magnitudes and characteristics may be associated with the different types of surge current events. The described Schottky rectifier structures provide surge current protection in multiple types of surge current scenarios, while minimizing or reducing situations in which solution techniques in one context undesirably mitigate effects of solution techniques in another context.
H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
26.
EMBEDDED CAPACITIVE SENSOR WITH CORESPONDING RAIN DETECTION METHOD AND RAIN DETECTION SYSTEM
Various embodiments of the present technology may provide methods and apparatus for a capacitive sensor (101) configured to detect rain (125). The capacitive sensor may be integrated within an interior surface of a laminated glass structure (130) comprising an adhesive interlayer (1410) disposed between two glass layers (1400, 1405). The capacitive sensor electrodes (105, 110) may be arranged in a variety of configurations between the two glass layers (1400, 1405). The capacitive sensor (101) may be used with a printed circuit board (135) that is configured to electrically couple to the capacitive sensor electrodes (105, 110).
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
B60S 1/08 - Wipers or the like, e.g. scrapers characterised by the drive electrically driven
27.
CAPACITIVE SENSOR WITH GROUND ELECTRODE AND CORESPONDING RAIN DETECTION METHOD AS WELL AS RAIN DETECTION SYSTEM
The present technology may provide methods and apparatus for a capacitive sensor (101) configured to detect rain (125). The capacitive sensor (101) may provide a reception electrode (105) in communication with a drive electrode (110) to form an electric field (150) and a ground electrode (115) surrounding the reception and drive electrodes (105, 110). The ground electrode (115) may couple the rain (125) to a ground potential resulting in a decrease in the capacitance of the capacitive sensor (101).
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
B60S 1/08 - Wipers or the like, e.g. scrapers characterised by the drive electrically driven
1,111) transmitted by the radar transmitter and to derive signal measurements therefrom. At least one of the radar transmitter and the radar receiver are switchable to provide the digital signal processor with signals from each of multiple combinations of transmit antenna (301) and receive antenna (302).
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
G01S 7/03 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver
H04B 7/08 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
An electronic device (10) may include an array of pixels (52). Each pixel may include a first single photon avalanche photodiode circuit (54-1) that generates a first output signal (VIN1) on a first conductive line (76-1), a second avalanche photodiode circuit (54-2) that generates a second output signal (VIN2) on a second conductive line (76-2), and a logic NAND gate (78) having a first input coupled to the first conductive line, a second input coupled to the second conductive line, and an output coupled to an output line (80). The logic NAND gate (78) may generate a third output signal (VOUT) based on the first and second output signals that is independent of dark current generated by the avalanche photodiodes. The third output signal (VOUT) may be processed to generate range values that are further processed to generate three-dimensional images of a scene.
Image sensors (200) may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates (210). A first n-epitaxial layer (204A) may be formed on a residual substrate (202); a first p-epitaxial layer (206A) may be formed on the first n-epitaxial layer; a second n-epitaxial layer (204B) may be formed on the first p-epitaxial layer; a second p-epitaxial layer (206B) may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers (204) may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates (210) may be a deep trench that is filled with doped conductive material (212), lined with gate dielectric liner (214), and surrounded by a p-doped region (216). Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.
Image sensors (200) may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates (210). A first n-epitaxial layer (204A) may be formed on a residual substrate (202); a first p-epitaxial layer (206A) may be formed on the first n-epitaxial layer; a second n-epitaxial layer (204B) may be formed on the first p-epitaxial layer; a second p-epitaxial layer (206B) may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers (204) may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates (210) may be a deep trench that is filled with doped conductive material (212), lined with gate dielectric liner (214), and surrounded by a p-doped region (216). Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.
In electron multiplying charge coupled device (EMCCD) image sensors (14), electron traps (209) in the dielectric stack underneath charge multiplication electrodes (201) may cause undesirable gain ageing. To reduce the gain ageing drift effect, a dielectric stack (304, 305) may be formed that does not include electron traps in regions underneath charge multiplication electrodes. To accomplish this, silicon nitride (305) in the dielectric stack may be removed in regions underneath the charge multiplication electrodes. The EMCCD image sensors can thus be fabricated with a stable charge carrier multiplication gain during their operational lifetime.
Various embodiments of the present technology may comprise a method and apparatus for a power management unit (205). The power management unit (205) may be configured to operate in conjunction other integrated circuits to mitigate power dissipation. The power management unit (205) may receive temperature information from a temperature sensor (120) and deploy various power management schemes to reduce the leakage power of an SRAM (210). The power management schemes may be based on the particular characteristics of the SRAM (210).
An image sensor pixel (22) may include multiple split photodiodes (50, 52) that are covered by a single microlens. The image sensor may include a charge overflow capacitor (66) coupled to a pixel charge storage (64) within the image sensor (22) via a gain control transistor (68). The image sensor pixel (22) may have phase detection capabilities in a first mode of operation enabled by comparing phase signals generated from the split photodiodes (50, 52). The image sensor pixel (22) also may generate and readout image signals simultaneously in both rolling shutter operations and global shutter operations in a second mode of operation. The image sensor pixel (22) may also generate an image using a linear combination of at least two signals read out using the charge overflow capacitor (66) and light flickering mitigation operations. The image may be a high dynamic range image that is generated from at least a low exposure signal and a high exposure signal.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 5/359 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
In accordance with at least one embodiment, a method for detecting a liquid level includes providing a container (402) having a cavity, and disposing a sensor (102) in the cavity of the container (402), such that a ground pattern (310) on a first surface of the sensor (102) is positioned to contact a liquid in the cavity. A first electrode (104) and a second electrode (106) are located on a second surface of the sensor (102). The sensor (102) is coupled to a sensor input and a sensor driver. A cable coupling the sensor (102) to a touch sensor (116) comprises a shield line (112, 114) that is coupled to ground.
G01F 23/26 - Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of capacity or inductance of capacitors or inductors arising from the presence of liquid or fluent solid material in the electric or electromagnetic fields
G01F 25/00 - Testing or calibration of apparatus for measuring volume, volume flow or liquid level or for metering by volume
36.
IMAGE SENSOR SEMICONDUCTOR PACKAGES AND RELATED METHODS
An image sensor semiconductor package (52) includes a printed circuit board (PCB) (56) having a first surface (58) and a second surface (60) opposite the first surface. A complementary metal- oxide semiconductor (CMOS) image sensor (CIS) die (4) has a first surface (6) with a photosensitive region (8) and a second surface (10) opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover (30) is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) (42) is embedded within the PCB. One or more electrical couplers (26) electrically couple the CIS die with the PCB. A plurality of electrical contacts (36) on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.
Implementations of semiconductor packages may include: a first semiconductor die coupled to a first side of a substrate having one or more internal traces. One or more connectors coupled to the first semiconductor die and the first side of the substrate. A glass lid coupled to the first side of the substrate over the first semiconductor die. A mold compound that encapsulates at least a portion of the substrate. A second semiconductor die coupled to a second side of the substrate opposing the first side. The second semiconductor die is electrically coupled with the first semiconductor die through the one or more traces of the substrate.
An image sensor (16) may include pixels (22) having nested sub-pixels. A pixel (22) with nested sub-pixels may include an inner sub-pixel (202) that has either an elliptical or a rectangular light collecting area. The inner sub-pixel may be formed in a substrate and may be immediately surrounded by a sub-pixel group (204) that includes one or more sub-pixels. The inner sub-pixel (202) may have a light collecting area at a surface (216) that is less sensitive than the light collecting area of the one or more outer sub-pixel groups. Microlenses (1040) may be formed over the nested sub-pixels, to direct light away from the inner sub-pixel group (202) to the outer sub-pixel groups (204) in nested sub-pixels. A color filter (1250) of a single color may be formed over the nested sub-pixels. Hybrid color filters having a single color filter region (1150) over the inner sub-pixel and a portion of the one or more outer sub-pixel groups may also be used.
An imaging pixel (100) may be provided with an upper substrate layer (30), a lower substrate layer (32), a floating diffusion region (52) in the upper substrate layer, and a photodiode (36) in the upper substrate layer that is coupled to the floating diffusion region. The imaging pixel may also include a source follower transistor (62) in the lower substrate layer and an interconnect layer (34) in between the upper substrate layer and the lower substrate layer. The interconnect layer may couple the floating diffusion region directly to the source follower transistor. The imaging pixel may include a reset transistor (54) in the upper substrate layer. The imaging pixel may include a metal layer (58) in the lower substrate layer, a transfer transistor (50) in the upper substrate layer, and an interconnect layer (34-2) that couples the transfer transistor to the metal layer.
Pulse width modulated controller systems. Implementations may include: a microcontroller coupled with a memory, a switch controller coupled with the microcontroller, and a calibration unit. The calibration unit may include one or more comparators, one or more passive electrical components, and an encoder logic all operatively coupled together and coupled with the microcontroller and with the switch controller where the at least one comparator and the one or more passive electrical components are electrically coupled with a supply voltage to the semiconductor switch and with a load voltage (output voltage) from the semiconductor switch.
H03K 17/042 - Modifications for accelerating switching by feedback from the output circuit to the control circuit
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
41.
SEMICONDUCTOR PACKAGES WITH AN INTERMETALLIC LAYER HAVING A MELTING TEMPERATURE ABOVE 260°C, COMPRISING AN INTERMETALLIC CONSISTING OF SILVER AND TIN OR AN INTERMETALLIC CONSISTING OF COPPER AND TIN, AND CORRESPONDING MANUFACTURING METHODS
Methods of forming a semiconductor package (2, 12) are provided. Implementations include forming on a die backside (16) an intermediate metal layer (26) having multiple sublayers (40-46), each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer (48) is deposited onto the intermediate metal layer (26) and is then reflowed with a silver layer (52) of a substrate (50) to form an intermetallic layer (56) having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump (22) on each of a plurality of exposed pads (20) of a top side (18) of a die (14), each exposed pad (20) surrounded by a passivation layer (24), each bump (22) including an intermediate metal layer (36) as described above and a tin layer (48) coupled to the intermediate metal layer (36), the tin layer (48) being then reflowed with a silver layer (52) of a substrate (50) to form an intermetallic layer (64), as described above.
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A semiconductor package. Implementations may include a substrate including a metallic baseplate coupled with an electrically insulative layer and a plurality of metallic traces coupled to the electrically insulative layer on a surface of the electrically insulative layer opposing a surface of the electrically insulative layer coupled to the metallic baseplate. The plurality of metallic traces may include at least two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the surface of the electrically insulative layer coupled with the metallic baseplate. The package may include at least one semiconductor device coupled to the substrate, a mold compound that encapsulates the power electronic device and at least a portion of the substrate, and at least one package electrical connector coupled with the substrate.
An imaging system (100) may include an image sensor die (102) stacked on top of a digital signal processor (DSP) die (104). Through-oxide vias (TOVs) (128) may be formed in the image sensor die (102) and may extend at least partially into in the DSP die (104) to facilitate communications between the image sensor die (102) and the DSP die (104). The image sensor die (102) may include light shielding structures (126) for preventing reference photodiodes (116') in the image sensor die (102) from receiving light and in-pixel grid structures (200) for preventing cross-talk between adjacent pixels (116). The light shielding structure (126) may receive a desired biasing voltage through a corresponding TOV (128), an integral plug structure (190), and/or a connection that makes contact directly with a polysilicon gate (192). The in-pixel grid (200) may have a peripheral contact (200') that receives the desired biasing voltage through a light shield (210), a conductive strap (210), a TOV (300), and/or an aluminum pad (450).
H01L 27/14 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
In accordance with an embodiment, a method for detecting a fluid level, includes providing a fluid container (80) having a cavity and coupling a first sensor (30, 32, 34, 36 to the fluid container, the first sensor protected from a fluid in the cavity and positioned at a first vertical level of the fluid container. The method further includes causing movement of either the first sensor or the fluid container. The first sensor is used to detect the fluid level upon causing the movement of either the first sensor or the fluid container.
G01F 23/26 - Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of capacity or inductance of capacitors or inductors arising from the presence of liquid or fluent solid material in the electric or electromagnetic fields
H01L 21/66 - Testing or measuring during manufacture or treatment
Provided is a production method for a circuit device whereby a resin sealing step for sealing with a thin coat of resin on a rear surface of a circuit substrate having a circuit element integrated on an upper surface thereof is achieved at low cost. In the present invention, an upper surface and a side surface of a circuit substrate (14) having a hybrid integrated circuit are coated with a first sealing resin (18) formed by transfer molding, and a lower surface of the circuit substrate (14), and a lower surface and a side surface of the first sealing resin (18) are subsequently coated with a second sealing resin (20). Furthermore, in a step for forming the second sealing resin (20), stable transfer molding is achieved by fixing the position of the workpiece such that resin-protruding portions (12), obtained by having the first sealing resin (18) protrude partially downwards, are in contact with an inner wall of a second die (50).
Provided is a circuit device manufacturing method wherein a resin sealing step of thinly sealing the rear surface of a circuit board with a resin is performed at low cost, said circuit board having circuit elements mounted on the upper surface thereof. In the present invention, the upper surface and the side surfaces of a circuit board (14) are coated with a first sealing resin (18) that is formed by transfer molding, said upper surface having a hybrid integrated circuit mounted thereon, then, the lower surface of the circuit board (14), and the lower surface and the side surfaces of the first sealing resin (18) are coated with a second sealing resin (20). Furthermore, in a step of forming the second sealing resin (20), stable transfer molding is performed by fixing the position by having the upper surface of the first sealing resin (18) in contact with the inner wall of a second molding die (50).
An integrated circuit includes a first configuration terminal, a second configuration terminal, a bus terminal, and an auto addressing circuit coupled to the first and second configuration terminals. The auto addressing circuit is responsive to a data pattern received at the first configuration terminal to assign a node address to an operational circuit, and subsequently to couple the first configuration terminal to the second configuration terminal. The integrated circuit is subsequently responsive to the node address when the node address is received.
In a MOSFET, the lead parts of gate lead wiring that lead out a gate electrode on the periphery of a substrate constitute a non-operative region where it is impossible to dispose a MOSFET transistor cell (C) that will function as efficiently as inside an element region. If the gate lead wiring is disposed along the four edges of a chip, for example, the area of the non-operative region increases, limiting the extent to which the surface area of the element region can be enlarged and the chip surface area reduced. In the present invention, gate lead wiring and a conductor, which is connected to the gate lead wiring and a protection diode, are disposed in a non-curved, linear configuration along one edge of a chip. In addition, a first gate electrode layer that extends superimposed on the gate lead wiring and the conductor, and connects the gate lead wiring and the conductor to the protection diode, has no more than one curved part. Furthermore, the protection diode is disposed adjacent to the conductor or the gate lead wiring, and a portion of the protection diode is disposed near a gate pad.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Electronic modules with small and flexible interfaces are disclosed. One example electronic module includes a power supply terminal configured to receive power for the electronic module and circuitry configured to carry out various functions. The functions carried out by the electronic module circuitry include simultaneously receiving both of the following via the power supply terminal: a power signal for carrying out a mission mode operation of the electronic module, and a data signal.
In accordance with an embodiment, a converter includes a power factor controller that varies the switching frequency of a switching transistor in accordance with a signal representative of power at the input of the converter.
In one embodiment, a method of forming a conditioning circuit includes configuring an output biasing network to provide a biasing voltage to an MOS transistor to enable the MOS transistor to operate in a saturated operating mode for input voltages that are less than a threshold voltage.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
In accordance with an embodiment, a pixel includes at least two switches, each switch having a control terminal and first and second current carrying terminals. The control terminals of the first and second switches are commonly connected together. In accordance with another embodiment, a method for transferring charge from a first switch to a capacitance includes applying voltage to the commonly connected control terminals of the first and second switches.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 5/374 - Addressed sensors, e.g. MOS or CMOS sensors
In accordance with an embodiment, a 4T pixel includes a first switch having a control terminal and first and second current carrying terminals and an amplifier having an input terminal and an output terminal. A second switch is coupled between the first switch and the amplifier.
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
54.
METHOD AND APPARATUS FOR DETECTING HOLD CONDITION ON AN ACOUSTIC TOUCH SURFACE
A bending wave touch system (100) includes at least one sensor (106) and a touch controller (124). The at least one sensor is coupled to a substrate (104) and is responsive to vibrations in the substrate. The at least one sensor outputs signals. The controller receives the signals from the at least one sensor and identifies touch coordinates based on high frequency components of the signals when a touch on the substrate includes at least one of a tap, a drag and a lift-off. The controller identifies a status of a hold condition of the touch based on at least two different time averages of low frequency components of the signals.
In one embodiment a power supply is configured to reuse a single power supply controller to regulate two different output voltages to two voltages including two different voltage values.
H05B 41/24 - Circuit arrangements in which the lamp is fed by high-frequency ac
H02M 3/28 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
56.
PLL CIRCUIT, AND RADIO COMMUNICATION DEVICE EQUIPPED THEREWITH
NATIONAL UNIVERSITY CORPORATION GUNMA UNIVERSITY (Japan)
Inventor
Dan, Toru
Tanabe, Tomoyuki
Kobayashi, Haruo
Abstract
In an ADPLL circuit (100), a DCO gain estimation unit (20) estimates, on the basis of the gain of a digital control oscillator (10), which is estimated in the state in which the loop gain with some value is set for a loop filter (18), and the element parameter of the digital control oscillator (10), the gain of the digital control oscillator (10) in the state in which the loop gain with another value is set for the loop filter (18).
H03L 7/107 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
A method and circuit for suppressing a bias current and decreasing power consumption. A current suppression circuit is coupled to a circuit element, which is capable of conducting the bias current. Coupling the current suppression circuit to the circuit element forms a node. In one operating mode, the current suppression circuit applies a voltage to the node in response to a heavy load. In another operating mode, the current suppression circuit lowers the voltage at the node in response to a light load or no load. Lowering the voltage at the node decreases the flow of bias current through the circuit element thereby lowering power loss.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage.
A method and circuit for protecting against an over current condition. A conduction time of one or more transistors is reduced during the over current condition. The conduction time is reduced in an amount that is an increasing function of the amount of the over current. The conduction time may be reduced proportionally to the excess current.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
60.
CIRCUIT FOR GENERATING A CLOCK SIGNAL FOR INTERLEAVED PFC STAGES AND METHOD THEREOF
A method and circuit for generating a clock signal. A power factor correction circuit has n channels operating out of phase and independently. The circuit is able to generate a clock signal for each channel according to the current cycle duration of each channel.
In one embodiment, a quasi-resonant power supply controller is configured to select particular valley values of a switch voltage to determine a time to enable a power switch. The valleys values are selected responsively to a range of values of a feedback signal.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
62.
AMPLIFIER WITH REDUCED OUTPUT TRANSIENTS AND METHOD THEREFOR
An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified output signal. The output stage (330) includes a gain stage and a bias circuit. The gain stage has an input forming the input of the output stage, an output for providing the amplified output signal, and a first bias terminal. The bias circuit has a first output terminal coupled to the first bias terminal of the gain stage. During a turn-on period the bias circuit gradually ramps the first bias terminal from a first initial voltage to a first bias voltage.
In one embodiment, a power supply controller is configured to receive a sense signal (CS) having a negative value that is proportional to the input voltage. The power supply controller uses the sense signal to limit the switch (27) current through the switch responsively to the value of the input voltage.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
64.
METHOD OF FORMING A DETECTION CIRCUIT AND STRUCTURE THEREFOR
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A signal generation circuit that uses a waveform generation mechanism to generate predetermined waveform(s) when triggered. A triggering mechanism is configured to repeatedly trigger the waveform generation mechanism at times that are dependent on data provided by a data source. The predetermined waveform may be a bandwidth-limited pulse, but might also be a rising edge or a falling edge of a pulse. Various consecutive waveforms may be summed together to thereby formulate a continuous signal. The waveform may have particular characteristics by design.
A method for regulating the output voltage of a power supply. A boost PWM switching converter adjusts the gate drive signals to a switching transistor and a pass transistor so that the power supply has an operating frequency, Fs, based on a comparison between a parameter and a reference. The parameter may be a ratio of an input voltage to an output voltage, a difference between the output voltage and the input voltage, or the value of an input voltage. In accordance with the comparison between the parameter and the reference, the switching control circuit linearly decreases the operating frequency of the power supply. By changing the operating frequency, the output and input voltages of the power regulator may be almost equal to each other when operating with a control signal having a low duty cycle while maintaining a low output voltage ripple and a low inductor current ripple.
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
67.
METHOD OF FORMING A FLASH CONTROLLER FOR A CAMERA AND STRUCTURE THEREFOR
In one embodiment, a flash controller for a camera is configured with a plurality of flash control channels that each control a value of a current through a light source. The value and timing of the current is controlled responsively to control words received by the plurality of flash control channels.
A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.
A current limit circuit and a method for limiting current flow. The current limit circuit includes a transistor having a control electrode and current carrying electrodes. A wire is coupled to one of the current carrying electrodes. An output of a comparator is coupled to the control electrode of the transistor through a charge pump. One input of the comparator is coupled to the current carrying electrode of the transistor that is coupled to the wire and the other input of the comparator is coupled for receiving a voltage. Preferably the wire is a bond wire. The current flowing through the wire sets the input voltage appearing at the input of the comparator coupled to the current carrying electrode of the transistor. In response to the comparison of the voltages at the input of the comparator, the transistor remains turned-on or it is turned-off.
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
70.
METHOD AND CIRCUIT FOR BI-DIRECTIONAL OVER-VOLTAGE PROTECTION
A bi-directional over-voltage protection circuit and a method for blocking current flow therein. The bi-directional over-voltage protection circuit comprises a regulator coupled to a lockout circuit, wherein the regulator and the lockout circuit are coupled for receiving an input signal and are coupled to a charging control circuit. A reverse path control circuit has an input coupled for receiving a control signal and an output coupled to the charging control circuit. A multi-transistor switching circuit is coupled to the forward control circuit. Preferably, the gate of each n-channel MOSFET is coupled to the charging control circuit, the drains are coupled together, and the source of one of the n-channel MOSFETS is coupled to an input and the source of the other n-channel MOSFET is coupled to an output of the bi-directional over-voltage protection circuit.
In one embodiment, a charge pump converter is formed to use various values of an output voltage to selectively control a value of a charging current during a charging cycle of the charge pump converter.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
72.
METHOD AND STRUCTURE OF FORMING A FLUORESCENT LIGHTING SYSTEM
A lighting system comprising a first plurality of fluorescent lamps (17) constituted by a first and a second lamp (20, 21) having a first common terminal (18) which is connected via a first capacitor (22) to a first terminal (12) of a voltage source (11). The system further comprises a second plurality of fluorescent lamps (29) constituted by a third and a fourth lamp (32, 33) having a first common terminal (30) which is connected via a second capacitor (34) to the first terminal (12) of a voltage source (11). The second terminals of the first lamp (20) and third lamp (32) are connected to a first terminal (24) of a third capacitor (25), said third capacitor (25) being connected with its second terminal to the second terminal (13) of the voltage source (11). The second terminals of the second lamp (21) and fourth lamp (33) are connected to a first terminal (36) of a fourth capacitor (37), the fourth capacitor (37) being connected with its second terminal to the second terminal (13) of the voltage source (11).
H05B 41/282 - Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices
In one embodiment, an amplifier circuit is formed to minimize pop and click noise on the outputs of the amplifier circuit. The amplifier circuit is configured to place an output stage of the amplifier circuit in a high impedance state to minimize the pop and click noise. In another embodiment, the amplifier circuit is configured to couple the inputs of two amplifiers together to minimize the pop and click noise.
A charge pump controller (20) is configured to charge a plurality of pump capacitors (16, 17) during a charging time interval and to sequentially form a plurality of discharge time intervals with a different pump capacitor (16, 17) coupled to supply a current (18) to a load (14) for each discharge time interval.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during the erase and programming phases. The access transistors are turned on and the source select transistors turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.
G11C 11/34 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
76.
METHOD OF FORMING A CHARGE PUMP CONTROLLER AND STRUCTURE THEREFOR
In one embodiment, a charge pump controller is configured with transistors having at least two different selectable on-resistance values may be used to charge a pump capacitor.
H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03K 17/06 - Modifications for ensuring a fully conducting state
77.
METHOD OF FORMING A POWER SUPPLY CONTROLLER AND STRUCTURE THEREFOR
In one embodiment, a switching controller uses an auxiliary winding voltage of a transformer to form a signal representative of current flow through a secondary winding of the transformer.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
In one embodiment, a switching controller uses an auxiliary winding voltage of a transformer to form a signal representative of current flow through a secondary winding of the transformer. The controller id configured to limit a current through a secondary winding to a maximum value.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
79.
DC-DC CONVERTER CONTROLLER HAVING OPTIMIZED LOAD TRANSIENT RESPONSE AND METHOD THEREOF
A power supply controller (25) is configured to accurately adjust the value of an output voltage of a power supply system (10) responsively to the output voltage increasing to an undesirable value. The controller (25) accurately limits an upper value of the output voltage during a light load condition, and rapidly reduces the value of the output voltage to a desired value. The power supply controller is configured to turn off the first output transistor but inhibit turning off the second output transistor using two different control signals.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
80.
SINGLE INPUT DUAL OUTPUT VOLTAGE POWER SUPPLY AND METHOD THEREFOR
In one embodiment, a power supply controller is configured to form both positive and negative supply voltages from a single input voltage so the maximum differential voltage across a load that uses the positive and negative supply voltages is no greater than the maximum value of the input voltage
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
In one embodiment, an amplification circuit receives an analog signal and adds another signal to the analog signal to modify the minimum amplitude of the analog input signal.
A charge pump controller (20) comprises a configurable pump capacitor (15, 16). A charge pump controller (20) controls the charge supplied to a load (12) to be less than the charge stored on the pump capacitor (15, 16).
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
In one embodiment, an amplification circuit charges a filter capacitor (14) and an input capacitor (12) with a substantially constant current and subsequently forms a delay prior to operating the amplification circuit to amplify input signals.
In one embodiment, an LED current control circuit is configured with a sample and hold circuit that samples an error signal of an error amplifier during one time and holds the sampled value during a second time.
In one embodiment, two current sources are used to contraol a current mirror. The current mirror controls a second current mirror to form an output current to be substantially constant.
A charge pump controller (19) comprises: a switch matrix (25) having a plurality of switch configuration modes, the switch matrix (25) being configured to receive an input voltage and form an output voltage that is multiple of the input voltage and being configured to supply the output voltage and a load current (16) to a load (17) ; and a current controller (30) that is configured to receive a sense signal (44) that is representative of the current (16) and form a mode control signal (23) to set an operating mode of the switch matrix responsively to a first value of the load current (16).
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H05B 33/08 - Circuit arrangements for operating electroluminescent light sources
87.
METHOD OF FORMING A SIGNAL LEVEL TRANSLATOR AND STRUCTURE THEREFOR
In one embodiment, a first portion (20) of translator circuit (17) is configured to extract a first supply voltage level from a high level of an input signal, an inverter (25) is configured to operate from the first supply-voltage level and a second portion (30) of the translator circuit is configured to operate from a second supply voltage level (V2) that is greater than the first supply voltage level .
A regulator circuit and a method for regulating an output voltage. The regulator circuit includes an undervoltage protection stage capable of operating in a plurality of operating modes. In one mode, the undervoltage protection stage compensates for a low undervoltage appearing in the output voltage and in another mode it compensates for a large undervoltage appearing in the output voltage. When the output voltage has a low undervoltage, a portion of the current from a current source is routed to a feedback network to balance the input voltages of the undervoltage protection stage and to place the voltage regulator in a steady state operating mode. When the output voltage has a large undervoltage, the undervoltage protection stage turns on a current sourcing transistor that cooperates with the current from the current source to quickly charge a compensation capacitor and increase the power appearing at the output of the voltage regulator.
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
89.
METHOD FOR REGULATING A VOLTAGE AND CIRCUIT THEREFOR
A voltage regulator having an overload protection circuit and a method for protecting against an output voltage being less than a predetermined level. The voltage regulator has an overload protection circuit coupled between a feedback network and a regulation section. A power factor correction circuit is connected to the regulation section. An output voltage from the power factor correction circuit is fed back to the feedback network, which transmits a portion of the output voltage to the overload protection circuit. If the output voltage is less than the predetermined voltage level, a transconductance amplifier generates a current that sets an overload flag. Setting the overload flag initiates a delay timer. If the delay exceeds a predetermined amount of time, the overload protection circuit shuts down the voltage regulator.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02H 7/12 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from norm for rectifiers for static converters or rectifiers
90.
METHOD FOR REGULATING A VOLTAGE AND CIRCUIT THEREFOR
A voltage regulator (10) having an undervoltage protection circuit 11 and a method for protecting against an output voltage out being less than a predetermined level. The voltage regulator has an undershoot limitation circuit (11) coupled between a feedback network (30) and a regulation section (42). A power factor correction circuit (46) is connected to the regulatio section. An output voltage out from the power factor correction circuit (46) is fed back to the feedback network (30), which transmits a portion of the output voltage to the undershoot limitation circuit (11). If the output voltage is greater than the predetermined voltage level, a switching circuit portion (34) of the undershoot limitation circuit (11) transmits a normal control signal to the regulation circuit (42). If the output voltage is less than the predetermined voltage level, the switching circuit portion transmits an enhanced control signal to the regulation circuit. The enhanced control signal quickly brings the output voltage up to at least the minimum desired level.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
In one embodiment, a class-D amplifier (11) is configured to form first (DP) and second (DN) PWM signals each having a duty cycle that is proportional to a received analog input signal (12) and responsively to enable a switch (31, 32) to short the outputs (13, 14) of the class-D amplifier (11) together responsively to some states of the first (DP) and second (DN) PWM signals.
H03F 3/217 - Class D power amplifiers; Switching amplifiers
H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
H03F 1/52 - Circuit arrangements for protecting such amplifiers
H03F 3/42 - Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H05B 33/08 - Circuit arrangements for operating electroluminescent light sources
In one embodiment, a circuit is configured to operate with a communication protocol that has at least three different signal levels wherein different sequences of the three levels identify different elements of the communication protocol. In another embodiment, a modular control block may be used to select the communication protocol and the operation of the circuit.
H04L 7/06 - Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity, or frequency
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
H03M 7/40 - Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
94.
DC-DC CONVERTER CONTROLLER HAVING OPTIMIZED LOAD TRANSIENT RESPONSE AND METHOD THEREOF
A power supply controller (25) is configured to accurately adjust the value of an output voltage of a power supply system (10) responsively to the output voltage increasing to an undesirable value. The controller (25) accurately limits an upper value of the output voltage during a light load condition, and rapidly reduces the value of the output voltage during a light load condition, and different control signals to control the switching of the output transistors facilitates rapidly reducing the output voltage.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
95.
METHOD OF FORMING A CURRENT SENSE CIRCUIT AND STRUCTURE THEREFOR
In one embodiment, a current sense circuit is formed with a pair of series connected switches that are used to steer a load current and form a current sense signal.
In one embodiment, a power supply controller is configured to operate a plurality of switches in a buck-boost mode to control an output voltage wherein at least one switch of the plurality of switches is enabled for a substantially fixed portion of a cycle of the buck-boost mode.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
In one embodiment, a power supply controller is configured to reset or override a soft-start reference signal responsively to the output voltage decreasing to a value that is less than a desired regulated value of the output voltage.
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
In one embodiment, a switch capacitor controller (20) is configured to use a drive signal (45) to drive the switched capacitor (26) with a signal having a time dependent transition time.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
99.
LOW POWER VOLTAGE DETECTION CIRCUIT AND METHOD THEREFOR
In one embodiment, a low power voltage detection circuit includes a first voltage detection device that receives power from an input voltage and a second voltage detection device receives power from an output of the low power voltage detection circuit.
In an embodiment, a power supply system is configured to use a linear regulator to form a regulated voltage during a standby mode and to use the regulated voltage to form another regulated voltage.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
patents
