|
H10B 10/00
|
Static random access memory [SRAM] devices |
|
H10B 10/10
|
SRAM devices comprising bipolar components |
|
H10B 12/00
|
Dynamic random access memory [DRAM] devices |
|
H10B 12/10
|
DRAM devices comprising bipolar components |
|
H10B 20/00
|
Read-only memory [ROM] devices |
|
H10B 20/10
|
ROM devices comprising bipolar components |
|
H10B 20/20
|
Programmable ROM [PROM] devices comprising field-effect components |
|
H10B 20/25
|
One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links |
|
H10B 41/00
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates |
|
H10B 41/10
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout |
|
H10B 41/20
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels |
|
H10B 41/23
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels |
|
H10B 41/27
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels |
|
H10B 41/30
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region |
|
H10B 41/35
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND |
|
H10B 41/40
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region |
|
H10B 41/41
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND |
|
H10B 41/42
|
Simultaneous manufacture of periphery and memory cells |
|
H10B 41/43
|
Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor |
|
H10B 41/44
|
Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor |
|
H10B 41/46
|
Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor |
|
H10B 41/47
|
Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor |
|
H10B 41/48
|
Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor |
|
H10B 41/49
|
Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor |
|
H10B 41/50
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region |
|
H10B 41/60
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell |
|
H10B 41/70
|
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components |
|
H10B 43/00
|
EEPROM devices comprising charge-trapping gate insulators |
|
H10B 43/10
|
EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout |
|
H10B 43/20
|
EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels |
|
H10B 43/23
|
EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels |
|
H10B 43/27
|
EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels |
|
H10B 43/30
|
EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region |
|
H10B 43/35
|
EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND |
|
H10B 43/40
|
EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region |
|
H10B 43/50
|
EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions |
|
H10B 51/00
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors |
|
H10B 51/10
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout |
|
H10B 51/20
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels |
|
H10B 51/30
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region |
|
H10B 51/40
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region |
|
H10B 51/50
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the boundary region between the core and peripheral circuit regions |
|
H10B 53/00
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors |
|
H10B 53/10
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout |
|
H10B 53/20
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels |
|
H10B 53/30
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region |
|
H10B 53/40
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region |
|
H10B 53/50
|
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the boundary region between the core and peripheral circuit regions |
|
H10B 61/00
|
Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices |
|
H10B 63/00
|
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices |
|
H10B 63/10
|
Phase change RAM [PCRAM, PRAM] devices |
|
H10B 69/00
|
Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices |
|
H10B 80/00
|
Assemblies of multiple devices comprising at least one memory device covered by this subclass |
|
H10B 99/00
|
Subject matter not provided for in other groups of this subclass |
