MINIMIZE DELAY TIMES FOR STATUS CHECKS TO FLASH MEMORY
| Register | WIPO Patent |
|---|---|
| Application Number | US2021043682 |
| Publication Number | 2023/009122 |
| Status | In Force |
| Filing Date | 2021-07-29 |
| Publication Date | 2023-02-02 |
| Owner | HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (USA) |
| Inventor |
|
Abstract
An example device includes a flash memory and a controller. The controller is to vary delay times between sending commands to the flash memory and status checks to determine when the flash memory has completed implementing the commands. The controller is further to, when a single status check, following a respective delay time, results in the flash memory indicating that a respective command has been implemented, use the respective delay time in determining further delay times for later commands similar to the respective command.IPC Classes ?
- G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures