Register USPTO Patent
Application Number 17961476
Status Pending
Filing Date 2022-10-06
First Publication Date 2023-02-02
Publication Date 2023-02-02
  • Ng, Boon Bing
  • Gardner, James Michael
  • Linn, Scott A.


A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

IPC Classes  ?

  • B41J 2/045 - Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
  • G06F 3/12 - Digital output to print unit
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers